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cpu/stm32l4wb: cleanup clock initialization

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This commit is contained in:
Alexandre Abadie 2020-09-17 08:28:06 +02:00
parent 23000ce452
commit 00ea7ffa55
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GPG Key ID: 1C919A403CAE1405
2 changed files with 49 additions and 18 deletions
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3
boards/common/stm32/include/l4/cfg_clock_default.h
View File

@ -152,9 +152,6 @@ extern "C" {
#define CLOCK_CORECLOCK (CLOCK_HSI)
#elif IS_ACTIVE(CONFIG_USE_CLOCK_HSE)
#if !IS_ACTIVE(CONFIG_BOARD_HAS_HSE)
#error "The board doesn't provide an HSE oscillator"
#endif
#define CLOCK_CORECLOCK (CLOCK_HSE)
#elif IS_ACTIVE(CONFIG_USE_CLOCK_MSI)

64
cpu/stm32/stmclk/stmclk_l4wb.c
View File

@ -218,7 +218,10 @@
#define CLOCK_ENABLE_48MHZ 0
#endif
/* Check if PLL is required */
/* Check if PLL is required
- When used as system clock
- When PLLQ is used as 48MHz clock source
*/
#if IS_ACTIVE(CONFIG_USE_CLOCK_PLL) || \
(IS_ACTIVE(CLOCK_ENABLE_48MHZ) && IS_ACTIVE(CLOCK48MHZ_USE_PLLQ))
#define CLOCK_ENABLE_PLL 1
@ -226,7 +229,38 @@
#define CLOCK_ENABLE_PLL 0
#endif
/* Check if MSI is required */
/* Check if HSE is required:
- When used as system clock
- When used as PLL input clock
*/
#if IS_ACTIVE(CONFIG_USE_CLOCK_HSE) || \
(IS_ACTIVE(CLOCK_ENABLE_PLL) && IS_ACTIVE(CONFIG_CLOCK_PLL_SRC_HSE))
#define CLOCK_ENABLE_HSE 1
#else
#define CLOCK_ENABLE_HSE 0
#endif
/* HSE cannot be enabled if not provided by the board */
#if IS_ACTIVE(CLOCK_ENABLE_HSE) && !IS_ACTIVE(CONFIG_BOARD_HAS_HSE)
#error "HSE is required by the clock configuration but is not provided by the board."
#endif
/* Check if HSI is required:
- When used as system clock
- When used as PLL input clock
*/
#if IS_ACTIVE(CONFIG_USE_CLOCK_HSI) || \
(IS_ACTIVE(CLOCK_ENABLE_PLL) && IS_ACTIVE(CONFIG_CLOCK_PLL_SRC_HSI))
#define CLOCK_ENABLE_HSI 1
#else
#define CLOCK_ENABLE_HSI 0
#endif
/* Check if MSI is required
- When used as system clock
- When used as PLL input clock
- When used as 48MHz clock source
*/
#if IS_ACTIVE(CONFIG_USE_CLOCK_MSI) || \
(IS_ACTIVE(CLOCK_ENABLE_PLL) && IS_ACTIVE(CONFIG_CLOCK_PLL_SRC_MSI)) || \
(IS_ACTIVE(CLOCK_ENABLE_48MHZ) && IS_ACTIVE(CLOCK48MHZ_USE_MSI))
@ -292,8 +326,7 @@ void stmclk_init_sysclk(void)
- Use HSE as system clock
- Use HSE as PLL input clock
*/
if (IS_ACTIVE(CONFIG_BOARD_HAS_HSE) &&
(IS_ACTIVE(CONFIG_USE_CLOCK_HSE) || IS_ACTIVE(CONFIG_CLOCK_PLL_SRC_HSE))) {
if (IS_ACTIVE(CLOCK_ENABLE_HSE)) {
RCC->CR |= (RCC_CR_HSEON);
while (!(RCC->CR & RCC_CR_HSERDY)) {}
}
@ -308,14 +341,12 @@ void stmclk_init_sysclk(void)
}
if (IS_ACTIVE(CLOCK_ENABLE_PLL)) {
if (IS_ACTIVE(CONFIG_CLOCK_PLL_SRC_MSI)) {
if (IS_ACTIVE(CONFIG_BOARD_HAS_LSE)) {
/* configure the low speed clock domain */
stmclk_enable_lfclk();
/* now we can enable the MSI PLL mode to enhance accuracy of the MSI */
RCC->CR |= RCC_CR_MSIPLLEN;
while (!(RCC->CR & RCC_CR_MSIRDY)) {}
}
if (IS_ACTIVE(CONFIG_CLOCK_PLL_SRC_MSI) && IS_ACTIVE(CONFIG_BOARD_HAS_LSE)) {
/* configure the low speed clock domain */
stmclk_enable_lfclk();
/* now we can enable the MSI PLL mode to enhance accuracy of the MSI */
RCC->CR |= RCC_CR_MSIPLLEN;
while (!(RCC->CR & RCC_CR_MSIRDY)) {}
}
/* now we can safely configure and start the PLL */
@ -334,8 +365,12 @@ void stmclk_init_sysclk(void)
while (!(RCC->CR & RCC_CR_PLLRDY)) {}
}
/* Disable the current SYSCLK source (HSI), only if not used */
if (!IS_ACTIVE(CLOCK_ENABLE_HSI)) {
RCC->CFGR &= ~RCC_CFGR_SW;
}
/* Configure the system clock (SYSCLK) */
RCC->CFGR &= ~RCC_CFGR_SW;
if (IS_ACTIVE(CONFIG_USE_CLOCK_HSE)) {
/* Select HSE as system clock */
RCC->CFGR |= RCC_CFGR_SW_HSE;
@ -357,8 +392,7 @@ void stmclk_init_sysclk(void)
RCC->CCIPR = CLOCK48MHZ_SELECT;
}
if (!IS_ACTIVE(CONFIG_USE_CLOCK_HSI) ||
(IS_ACTIVE(CONFIG_USE_CLOCK_PLL) && !IS_ACTIVE(CONFIG_CLOCK_PLL_SRC_HSI))) {
if (!IS_ACTIVE(CLOCK_ENABLE_HSI)) {
/* Disable HSI only if not used */
stmclk_disable_hsi();
}