From 01c573c61256127ceca4e24a5dd6a87c3b612e86 Mon Sep 17 00:00:00 2001 From: Benjamin Valentin Date: Thu, 2 Apr 2020 23:48:42 +0200 Subject: [PATCH] cpu/samd21: pwm: allow to use channels > 3 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Channels 4…7 are on the CCB register. --- cpu/samd21/periph/pwm.c | 12 ++++++++++-- 1 file changed, 10 insertions(+), 2 deletions(-) diff --git a/cpu/samd21/periph/pwm.c b/cpu/samd21/periph/pwm.c index ceaf7ec9f0..8cf442eb78 100644 --- a/cpu/samd21/periph/pwm.c +++ b/cpu/samd21/periph/pwm.c @@ -167,8 +167,16 @@ void pwm_set(pwm_t dev, uint8_t channel, uint16_t value) (pwm_config[dev].chan[channel].pin == GPIO_UNDEF)) { return; } - _tcc(dev)->CC[_chan(dev, channel)].reg = value; - while (_tcc(dev)->SYNCBUSY.reg & (TCC_SYNCBUSY_CC0 << _chan(dev, channel))) {} + + uint8_t chan = _chan(dev, channel); + if (chan < 4) { + _tcc(dev)->CC[chan].reg = value; + while (_tcc(dev)->SYNCBUSY.reg & (TCC_SYNCBUSY_CC0 << chan)) {} + } else { + chan -= 4; + _tcc(dev)->CCB[chan].reg = value; + while (_tcc(dev)->SYNCBUSY.reg & (TCC_SYNCBUSY_CCB0 << chan)) {} + } } void pwm_poweron(pwm_t dev)