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cpu/stm32_common: enable EXTI interrupt for rtt

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Vincent Dupont 2019-03-26 19:19:29 +01:00 committed by Alexandre Abadie
parent 15dc9fe0de
commit 08286f7e41
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GPG Key ID: 1C919A403CAE1405
1 changed files with 30 additions and 0 deletions
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30
cpu/stm32_common/periph/rtt.c
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@ -67,6 +67,23 @@
#endif
#endif
#if defined(CPU_FAM_STM32L4) || defined(CPU_FAM_STM32WB)
#define IMR_REG IMR2
#define EXTI_IMR_BIT EXTI_IMR2_IM32
#elif defined(CPU_FAM_STM32L0)
#define IMR_REG IMR
#define EXTI_IMR_BIT EXTI_IMR_IM29
#else
#define IMR_REG IMR
#define FTSR_REG FTSR
#define RTSR_REG RTSR
#define PR_REG PR
#define EXTI_FTSR_BIT EXTI_FTSR_TR23
#define EXTI_RTSR_BIT EXTI_RTSR_TR23
#define EXTI_IMR_BIT EXTI_IMR_MR23
#define EXTI_PR_BIT EXTI_PR_PR23
#endif
/* allocate memory for overflow and alarm callbacks + args */
static rtt_cb_t ovf_cb = NULL;
@ -91,6 +108,15 @@ void rtt_init(void)
LPTIM1->CFGR = PRE;
/* enable overflow and compare interrupts */
LPTIM1->IER = (LPTIM_IER_ARRMIE | LPTIM_IER_CMPMIE);
/* configure the EXTI channel, as RTT interrupts are routed through it.
* Needs to be configured to trigger on rising edges. */
EXTI->IMR_REG |= EXTI_IMR_BIT;
#if !defined(CPU_FAM_STM32L4) && !defined(CPU_FAM_STM32L0) && \
!defined(CPU_FAM_STM32WB)
EXTI->FTSR_REG &= ~(EXTI_FTSR_BIT);
EXTI->RTSR_REG |= EXTI_RTSR_BIT;
EXTI->PR_REG |= EXTI_PR_BIT;
#endif
NVIC_EnableIRQ(LPTIM1_IRQn);
/* enable timer */
LPTIM1->CR = LPTIM_CR_ENABLE;
@ -178,6 +204,10 @@ void isr_lptim1(void)
}
}
LPTIM1->ICR = (LPTIM_ICR_ARRMCF | LPTIM_ICR_CMPMCF);
#if !defined(CPU_FAM_STM32L4) && !defined(CPU_FAM_STM32L0) && \
!defined(CPU_FAM_STM32WB)
EXTI->PR_REG |= EXTI_PR_BIT;
#endif
cortexm_isr_end();
}