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kinetis: GPIO: Enable the correct IRQn on CM0+

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This commit is contained in:
Joakim Nohlgård 2018-05-16 22:16:34 +02:00
parent 9d83b60f3b
commit 09e0e8953d
2 changed files with 6 additions and 2 deletions
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1
cpu/kinetis/include/cpu_conf_kinetis.h
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@ -155,6 +155,7 @@ extern "C"
#define LPTMR0_IRQn LPTimer_IRQn
#define PIT_TCTRL_CHN_MASK (0x4u)
#define PIT_TCTRL_CHN_SHIFT (2)
#define PORT_IRQS { PORTA_IRQn, PORTB_IRQn, PORTC_IRQn, PORTD_IRQn, PORTE_IRQn }
#endif /* MK20D7_H_ */
/** @} */

7
cpu/kinetis/periph/gpio.c
View File

@ -113,6 +113,7 @@ static isr_ctx_t isr_ctx[CTX_NUMOF];
*/
static uint32_t isr_map[ISR_MAP_SIZE];
static const uint8_t port_irqs[] = PORT_IRQS;
static inline PORT_Type *port(gpio_t pin)
{
@ -217,9 +218,11 @@ int gpio_init_int(gpio_t pin, gpio_mode_t mode, gpio_flank_t flank,
/* clear interrupt flags */
port(pin)->ISFR &= ~(1 << pin_num(pin));
/* enable global port interrupts in the NVIC */
NVIC_EnableIRQ(PORTA_IRQn + port_num(pin));
/* finally, enable the interrupt for the select pin */
NVIC_EnableIRQ(port_irqs[port_num(pin)]);
/* finally, enable the interrupt for the selected pin */
port(pin)->PCR[pin_num(pin)] |= flank;
return 0;
}