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samd21: tidy up peripheral clocks and fix potential bugs in pwm and i2c clocks

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This commit is contained in:
daniel-k 2015-09-17 15:57:51 +02:00
parent 669043c435
commit 0b6da4609e
4 changed files with 25 additions and 16 deletions
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6
cpu/samd21/cpu.c
View File

@ -83,6 +83,12 @@ static void clk_init(void)
/* make sure we synchronize clock generator 0 before we go on */
while (GCLK->STATUS.reg & GCLK_STATUS_SYNCBUSY);
/* redirect all peripherals to a disabled clock generator (7) by default */
for (int i = 0x3; i <= 0x22; i++) {
GCLK->CLKCTRL.reg = ( GCLK_CLKCTRL_ID(i) | GCLK_CLKCTRL_GEN_GCLK7 );
while (GCLK->STATUS.bit.SYNCBUSY);
}
}
void cpu_init(void)

5
cpu/samd21/periph/gpio.c
View File

@ -146,7 +146,10 @@ int gpio_init_int(gpio_t pin, gpio_pp_t pullup, gpio_flank_t flank,
gpio_init_mux(pin, GPIO_MUX_A);
/* enable clocks for the EIC module */
PM->APBAMASK.reg |= PM_APBAMASK_EIC;
GCLK->CLKCTRL.reg = (EIC_GCLK_ID | GCLK_CLKCTRL_CLKEN);
GCLK->CLKCTRL.reg = (EIC_GCLK_ID |
GCLK_CLKCTRL_CLKEN |
GCLK_CLKCTRL_GEN_GCLK0);
while (GCLK->STATUS.bit.SYNCBUSY);
/* configure the active flank */
EIC->CONFIG[exti >> 3].reg &= ~(0xf << ((exti & 0x7) * 4));
EIC->CONFIG[exti >> 3].reg |= (flank << ((exti & 0x7) * 4));

12
cpu/samd21/periph/i2c.c
View File

@ -102,14 +102,14 @@ int i2c_init_master(i2c_t dev, i2c_speed_t speed)
PM->APBCMASK.reg |= (PM_APBCMASK_SERCOM0 << (sercom_core - 20));
/* I2C using CLK GEN 0 */
GCLK->CLKCTRL.reg = (uint32_t)(GCLK_CLKCTRL_CLKEN
| GCLK_CLKCTRL_GEN_GCLK0 << GCLK_CLKCTRL_GEN_Pos
| (sercom_core << GCLK_CLKCTRL_ID_Pos));
GCLK->CLKCTRL.reg = (GCLK_CLKCTRL_CLKEN |
GCLK_CLKCTRL_GEN_GCLK0 |
GCLK_CLKCTRL_ID(sercom_core));
while (GCLK->STATUS.bit.SYNCBUSY);
GCLK->CLKCTRL.reg = (uint16_t)(GCLK_CLKCTRL_CLKEN
| GCLK_CLKCTRL_GEN_GCLK0 << GCLK_CLKCTRL_GEN_Pos
| (sercom_gclk_id_slow << GCLK_CLKCTRL_ID_Pos));
GCLK->CLKCTRL.reg = (GCLK_CLKCTRL_CLKEN |
GCLK_CLKCTRL_GEN_GCLK0 |
GCLK_CLKCTRL_ID(sercom_gclk_id_slow));
while (GCLK->STATUS.bit.SYNCBUSY);

18
cpu/samd21/periph/pwm.c
View File

@ -121,11 +121,7 @@ int pwm_init(pwm_t dev, pwm_mode_t mode,
/* power on the device */
pwm_poweron(dev);
/* configure generic clock 0 to feed the PWM */
GCLK->CLKCTRL.reg = (GCLK_CLKCTRL_CLKEN
| GCLK_CLKCTRL_GEN_GCLK0
| (_clk_id(dev) << GCLK_CLKCTRL_ID_Pos));
while (GCLK->STATUS.bit.SYNCBUSY);
/* reset TCC module */
_tcc(dev)->CTRLA.reg = TCC_CTRLA_SWRST;
while (_tcc(dev)->SYNCBUSY.reg & TCC_SYNCBUSY_SWRST);
@ -184,9 +180,11 @@ void pwm_poweron(pwm_t dev)
if (num < 0) {
return;
}
GCLK->CLKCTRL.reg = (GCLK_CLKCTRL_CLKEN
| (_clk_id(dev) << GCLK_CLKCTRL_ID_Pos));
PM->APBCMASK.reg |= (PM_APBCMASK_TCC0 << num);
GCLK->CLKCTRL.reg = (GCLK_CLKCTRL_CLKEN |
GCLK_CLKCTRL_GEN_GCLK0 |
GCLK_CLKCTRL_ID(_clk_id(dev)));
while (GCLK->STATUS.bit.SYNCBUSY);
}
void pwm_poweroff(pwm_t dev)
@ -195,8 +193,10 @@ void pwm_poweroff(pwm_t dev)
if (num < 0) {
return;
}
GCLK->CLKCTRL.reg = ((_clk_id(dev) << GCLK_CLKCTRL_ID_Pos));
PM->APBCMASK.reg &= ~(1 << num);
PM->APBCMASK.reg &= ~(PM_APBCMASK_TCC0 << num);
GCLK->CLKCTRL.reg = (GCLK_CLKCTRL_GEN_GCLK7 |
GCLK_CLKCTRL_ID(_clk_id(dev)));
while (GCLK->STATUS.bit.SYNCBUSY);
}
#endif /* PWM_NUMOF */