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cpu/stm32: adapt Kconfig clock configuration for f1/f3

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Alexandre Abadie 2020-10-31 17:17:18 +01:00
parent 229291ef01
commit 0f23c875a2
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GPG Key ID: 1C919A403CAE1405
1 changed files with 12 additions and 7 deletions
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19
cpu/stm32/kconfigs/Kconfig.clk
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@ -6,7 +6,7 @@
#
menu "STM32 clock configuration"
depends on CPU_FAM_G0 || CPU_FAM_G4 || CPU_FAM_F0 || CPU_FAM_L0 || CPU_FAM_L1 || CPU_FAM_L4 || CPU_FAM_L5 || CPU_FAM_WB
depends on !CPU_FAM_F2 && !CPU_FAM_F4 && !CPU_FAM_F7
choice
bool "Clock source selection"
@ -112,19 +112,23 @@ endif # CPU_FAM_G4 || CPU_FAM_L4 || CPU_FAM_L5
endif # CPU_FAM_G0 || CPU_FAM_G4 || CPU_FAM_L4 || CPU_FAM_L5 || CPU_FAM_WB
if CPU_FAM_F0
if CPU_FAM_F0 || CPU_FAM_F1 || CPU_FAM_F3
config CLOCK_PLL_PREDIV
int "PLLIN division factor" if CUSTOM_PLL_PARAMS && !CPU_LINE_STM32F031X6 && !CPU_LINE_STM32F042X6
default 2 if CPU_LINE_STM32F031X6 || CPU_LINE_STM32F042X6
int "PLLIN division factor" if CUSTOM_PLL_PARAMS && !CPU_LINE_STM32F031X6 && !CPU_LINE_STM32F042X6 && !CPU_LINE_STM32F303X8
# iotlab based boards provide a 16MHz HSE so they need a predivider of 2
# to remain with a 72MHz sysclk by default.
default 2 if CPU_LINE_STM32F031X6 || CPU_LINE_STM32F042X6 || CPU_LINE_STM32F303X8 || (CPU_FAM_F1 && (BOARD_IOTLAB_M3 || BOARD_IOTLAB_A8_M3 || BOARD_FOX))
default 1
range 1 16
config CLOCK_PLL_MUL
int "PLLIN multiply factor" if CUSTOM_PLL_PARAMS
default 16 if CPU_LINE_STM32F303X8
default 12 if CPU_LINE_STM32F031X6 || CPU_LINE_STM32F042X6
default 6
default 9 if CPU_FAM_F1 || CPU_FAM_F3
default 6 if CPU_FAM_F0
range 2 16
endif
endif # CPU_FAM_F0 || CPU_FAM_F1 || CPU_FAM_F3
if CPU_FAM_L0 || CPU_FAM_L1
config CLOCK_PLL_DIV
@ -307,6 +311,7 @@ endif # CPU_FAM_L0 || CPU_FAM_L1 || CPU_FAM_L4 || CPU_FAM_L5 || CPU_FAM_WB
choice
bool "APB1 prescaler (division factor of HCLK to produce PCLK1)"
default CLOCK_APB1_DIV_4 if CPU_FAM_L4 || CPU_FAM_L5 || CPU_FAM_WB
default CLOCK_APB1_DIV_2 if CPU_FAM_F1 || CPU_FAM_F3
default CLOCK_APB1_DIV_1
config CLOCK_APB1_DIV_1
@ -336,7 +341,7 @@ config CLOCK_APB1_DIV
choice
bool "APB2 prescaler (division factor of HCLK to produce PCLK2)"
depends on CPU_FAM_G4 || CPU_FAM_L0 || CPU_FAM_L1 || CPU_FAM_L4 || CPU_FAM_L5 || CPU_FAM_WB
depends on !CPU_FAM_G0 && !CPU_FAM_F0
default CLOCK_APB2_DIV_2 if CPU_FAM_L4 || CPU_FAM_L5 || CPU_FAM_WB
default CLOCK_APB2_DIV_1