From ac4c4d61328ffdc64cf4ae37974c68879b0adb26 Mon Sep 17 00:00:00 2001 From: iosabi Date: Sat, 5 Dec 2020 19:49:38 +0100 Subject: [PATCH] cpu/qn908x: Fix triggering GPIO IRQ. The IRQ for each GPIO port needs to be enabled in the NVIC on top of enabling the corresponding bit in the GPIO port. This was not caught in tests before because I was testing with a larger stack of commits (including UART and timers) which also had this fix. Manually poking the GPIOs while using tests/periph_gpio now properly fires the interrupts. --- cpu/qn908x/periph/gpio.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/cpu/qn908x/periph/gpio.c b/cpu/qn908x/periph/gpio.c index 6d9880a4ba..1ed86b4e7b 100644 --- a/cpu/qn908x/periph/gpio.c +++ b/cpu/qn908x/periph/gpio.c @@ -117,6 +117,9 @@ typedef struct { */ #define TOTAL_GPIO_PINS (35) +/* The IRQ number in the NVIC for each GPIO port. */ +static const uint32_t gpio_nvic_irqs[GPIO_PORTS_NUMOF] = GPIO_IRQS; + static gpio_isr_cb_state_t gpio_isr_state[TOTAL_GPIO_PINS] = {}; int gpio_init_int(gpio_t pin, gpio_mode_t mode, gpio_flank_t flank, @@ -162,6 +165,7 @@ int gpio_init_int(gpio_t pin, gpio_mode_t mode, gpio_flank_t flank, /* Handled above */ break; } + NVIC_EnableIRQ(gpio_nvic_irqs[GPIO_T_PORT(pin)]); gpio_irq_enable(pin); return 0; }