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https://github.com/RIOT-OS/RIOT.git
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cpu/lpc2387+boards: adapted to new SPI API
- adapted the SPI driver - adapted all boards using the CPU
This commit is contained in:
Hauke Petersen
parent
b097e0840b
commit
10b0013315
@ -82,10 +82,12 @@ extern "C" {
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/**
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* @brief SPI configuration
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*
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* The SPI implementation is very much fixed, so we don't need to configure
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* anything besides the mandatory SPI_NUMOF.
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* @{
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*/
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#define SPI_NUMOF (1)
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#define SPI_0_EN (1)
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/** @} */
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#ifdef __cplusplus
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@ -74,11 +74,24 @@ typedef enum {
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* @brief Declare needed generic SPI functions
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* @{
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*/
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#define PERIPH_SPI_NEEDS_TRANSFER_BYTES
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#define PERIPH_SPI_NEEDS_INIT_CS
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#define PERIPH_SPI_NEEDS_TRANSFER_BYTE
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#define PERIPH_SPI_NEEDS_TRANSFER_REG
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#define PERIPH_SPI_NEEDS_TRANSFER_REGS
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/* @} */
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/**
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* @brief Override SPI clock speed values
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*/
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#define HAVE_SPI_CLK_T
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typedef enum {
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SPI_CLK_100KHZ = 100, /**< drive the SPI bus with 100KHz */
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SPI_CLK_400KHZ = 400, /**< drive the SPI bus with 400KHz */
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SPI_CLK_1MHZ = 1000, /**< drive the SPI bus with 1MHz */
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SPI_CLK_5MHZ = 5000, /**< drive the SPI bus with 5MHz */
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SPI_CLK_10MHZ = 10000 /**< drive the SPI bus with 10MHz */
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} spi_clk_t;
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/* @} */
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#ifdef __cplusplus
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}
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@ -1,9 +1,10 @@
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/*
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* Copyright (C) 2015 Kaspar Schleiser <kaspar@schleiser.de>
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* 2016 Freie Universität Berlin
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*
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* This file is subject to the terms and conditions of the GNU Lesser General
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* Public License v2.1. See the file LICENSE in the top level directory for more
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* details.
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* This file is subject to the terms and conditions of the GNU Lesser
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* General Public License v2.1. See the file LICENSE in the top level
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* directory for more details.
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*/
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/**
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@ -13,22 +14,25 @@
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* @file
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* @brief Low-level SPI driver implementation
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*
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* This implementation is very basic and only supports a single SPI device with
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* limited configuration options.
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*
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* @todo This implementation needs a major rework
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*
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* @author Kaspar Schleiser <kaspar@schleiser.de>
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* @author Hauke Petersen <hauke.petersen@fu-berlin.de>
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*
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* @}
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*/
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#include "cpu.h"
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#include "mutex.h"
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#include "periph/gpio.h"
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#include "assert.h"
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#include "periph/spi.h"
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#include "periph_conf.h"
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#include "board.h"
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#define ENABLE_DEBUG (0)
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#include "debug.h"
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#if SPI_0_EN
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#define SPI_TX_EMPTY (SSP0SR & SSPSR_TFE)
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#define SPI_BUSY (SSP0SR & SSPSR_BSY)
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#define SPI_RX_AVAIL (SSP0SR & SSPSR_RNE)
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@ -36,178 +40,94 @@
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/**
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* @brief Array holding one pre-initialized mutex for each SPI device
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*/
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static mutex_t locks[] = {
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#if SPI_0_EN
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[SPI_0] = MUTEX_INIT,
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#endif
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#if SPI_1_EN
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[SPI_1] = MUTEX_INIT,
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#endif
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#if SPI_2_EN
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[SPI_2] = MUTEX_INIT
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#endif
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};
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static mutex_t lock = MUTEX_INIT;
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int spi_init_master(spi_t dev, spi_conf_t conf, spi_speed_t speed)
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void spi_init(spi_t bus)
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{
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(void ) conf;
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if (dev) {
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return -1;
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}
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assert(bus == SPI_DEV(0));
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uint32_t f_baud = 0;
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switch(speed)
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{
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case SPI_SPEED_100KHZ:
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f_baud = 100;
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break;
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case SPI_SPEED_400KHZ:
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f_baud = 400;
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break;
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case SPI_SPEED_1MHZ:
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f_baud = 1000;
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break;
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case SPI_SPEED_5MHZ:
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f_baud = 5000;
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break;
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case SPI_SPEED_10MHZ:
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f_baud = 10000;
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break;
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}
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#if 0
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/* TODO */
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switch(conf)
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{
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case SPI_CONF_FIRST_RISING:
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/**< first data bit is transacted on the first rising SCK edge */
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cpha = 0;
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cpol = 0;
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break;
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case SPI_CONF_SECOND_RISING:
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/**< first data bit is transacted on the second rising SCK edge */
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cpha = 1;
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cpol = 0;
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break;
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case SPI_CONF_FIRST_FALLING:
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/**< first data bit is transacted on the first falling SCK edge */
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cpha = 0;
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cpol = 1;
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break;
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case SPI_CONF_SECOND_FALLING:
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/**< first data bit is transacted on the second falling SCK edge */
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cpha = 1;
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cpol = 1;
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break;
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}
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#endif
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/* Power*/
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PCONP |= PCSSP0; /* Enable power for SSP0 (default is on)*/
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/* PIN Setup*/
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spi_conf_pins(dev);
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/* Interface Setup*/
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/* interface setup */
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SSP0CR0 = 7;
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/* configure pins */
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spi_init_pins(bus);
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/* power off the bus (default is on) */
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PCONP &= ~(PCSSP0);
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}
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/* Clock Setup*/
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void spi_init_pins(spi_t bus)
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{
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PINSEL3 |= (BIT8 | BIT9); /* SCLK */
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PINSEL3 |= (BIT14 | BIT15); /* MISO */
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PINSEL3 |= (BIT16 | BIT17); /* MOSI */
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}
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int spi_acquire(spi_t bus, spi_cs_t cs, spi_mode_t mode, spi_clk_t clk)
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{
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uint32_t pclksel;
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uint32_t cpsr;
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lpc2387_pclk_scale(CLOCK_CORECLOCK / 1000, f_baud, &pclksel, &cpsr);
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/* only support for mode 0 at the moment */
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if (mode != SPI_MODE_0) {
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return SPI_NOMODE;
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}
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/* lock bus */
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mutex_lock(&lock);
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/* power on */
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PCONP |= (PCSSP0);
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/* configure bus clock */
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lpc2387_pclk_scale(CLOCK_CORECLOCK / 1000, (uint32_t)clk, &pclksel, &cpsr);
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PCLKSEL1 &= ~(BIT10 | BIT11); /* CCLK to PCLK divider*/
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PCLKSEL1 |= pclksel << 10;
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SSP0CPSR = cpsr;
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/* Enable*/
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SSP0CR1 |= BIT1; /* SSP-Enable*/
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/* enable the bus */
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SSP0CR1 |= BIT1;
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/* clear RxFIFO */
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int dummy;
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while (SPI_RX_AVAIL) { /* while RNE (Receive FIFO Not Empty)...*/
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dummy = SSP0DR; /* read data*/
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}
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(void) dummy; /* to suppress unused-but-set-variable */
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/* Clear RxFIFO:*/
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while (SPI_RX_AVAIL) { /* while RNE (Receive FIFO Not Empty)...*/
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dummy = SSP0DR; /* read data*/
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return SPI_OK;
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}
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void spi_release(spi_t bus)
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{
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/* disable, power off, and release the bus */
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SSP0CR1 &= ~(BIT1);
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PCONP &= ~(PCSSP0);
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mutex_unlock(&lock);
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}
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void spi_transfer_bytes(spi_t bus, spi_cs_t cs, bool cont,
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const void *out, void *in, size_t len)
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{
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uint8_t *out_buf = (uint8_t *)out;
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uint8_t *in_buf = (uint8_t *)in;
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assert(out_buf || in_buf);
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if (cs != SPI_CS_UNDEF) {
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gpio_clear((gpio_t)cs);
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}
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/* to suppress unused-but-set-variable */
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(void) dummy;
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return 0;
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}
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int spi_init_slave(spi_t dev, spi_conf_t conf, char (*cb)(char))
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{
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(void)dev;
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(void)conf;
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(void)cb;
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printf("%s:%s(): stub\n", RIOT_FILE_RELATIVE, __func__);
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/* TODO */
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return -1;
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}
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void spi_transmission_begin(spi_t dev, char reset_val)
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{
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(void)dev;
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(void)reset_val;
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printf("%s:%s(): stub\n", RIOT_FILE_RELATIVE, __func__);
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/* TODO*/
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}
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int spi_acquire(spi_t dev)
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{
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if (dev >= SPI_NUMOF) {
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return -1;
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}
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mutex_lock(&locks[dev]);
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return 0;
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}
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int spi_release(spi_t dev)
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{
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if (dev >= SPI_NUMOF) {
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return -1;
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}
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mutex_unlock(&locks[dev]);
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return 0;
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}
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int spi_transfer_byte(spi_t dev, char out, char *in)
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{
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(void) dev;
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while (!SPI_TX_EMPTY) {}
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SSP0DR = out;
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while (SPI_BUSY) {}
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while (!SPI_RX_AVAIL) {}
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char tmp = (char)SSP0DR;
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if (in != NULL) {
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*in = tmp;
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for (size_t i = 0; i < len; i++) {
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uint8_t tmp = (out_buf) ? out_buf[i] : 0;
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while (!SPI_TX_EMPTY) {}
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SSP0DR = tmp;
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while (SPI_BUSY) {}
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while (!SPI_RX_AVAIL) {}
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tmp = (uint8_t)SSP0DR;
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if (in_buf) {
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in_buf[i] = tmp;
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}
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}
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return 1;
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}
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void spi_poweron(spi_t dev)
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{
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(void) dev;
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}
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void spi_poweroff(spi_t dev)
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{
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(void) dev;
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(void) dev;
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}
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int spi_conf_pins(spi_t dev)
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{
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switch (dev) {
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case 0:
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PINSEL3 |= BIT8 + BIT9; /* SCLK */
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PINSEL3 |= BIT14 + BIT15; /* MISO */
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PINSEL3 |= BIT16 + BIT17; /* MOSI */
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return 0;
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default:
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return -1;
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if ((!cont) && cs != SPI_CS_UNDEF) {
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gpio_set((gpio_t)cs);
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}
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}
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#endif /* SPI_0_EN */
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