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Merge pull request #18322 from gschorcht/cpu/esp32/split_sdkconfig_into_common_and_specific

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cpu/esp32: split sdkconfig.h into ESP32x common and ESP32 specific parts
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benpicco 2022-07-19 02:57:06 +02:00 committed by GitHub
commit 14292bdce2
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GPG Key ID: 4AEE18F83AFDEB23
4 changed files with 104 additions and 31 deletions
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8
cpu/esp32/bootloader/sdkconfig.h
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@ -30,7 +30,13 @@
#ifndef DOXYGEN
#include "esp_idf_ver.h"
#include "sdkconfig_default.h"
#if defined(CPU_FAM_ESP32)
#include "sdkconfig_default_esp32.h"
#else
#error "ESP32x family implementation missing"
#endif
#ifdef __cplusplus
extern "C" {

30
cpu/esp32/bootloader/sdkconfig_default.h → cpu/esp32/bootloader/sdkconfig_default_esp32.h
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@ -1,10 +1,23 @@
/*
* Generated by ./update_mk.sh, don't modify directly.
* Default CONFIG_ parameters from the SDK package.
* Copyright (C) 2022 Gunar Schorcht
*
* This file is subject to the terms and conditions of the GNU Lesser
* General Public License v2.1. See the file LICENSE in the top level
* directory for more details.
*/
#ifndef SDKCONFIG_DEFAULT_H
#define SDKCONFIG_DEFAULT_H
/**
* @ingroup cpu_esp32
* @{
*
* @file
* @brief Default SDK configuration for the ESP32 SoC bootloader
*
* @author Gunar Schorcht <gunar@schorcht.net>
*/
#ifndef SDKCONFIG_DEFAULT_ESP32_H
#define SDKCONFIG_DEFAULT_ESP32_H
#ifndef DOXYGEN
@ -22,14 +35,20 @@ extern "C" {
#define CONFIG_CONSOLE_UART_NUM 0
#define CONFIG_EFUSE_CODE_SCHEME_COMPAT_3_4 1
#define CONFIG_EFUSE_MAX_BLK_LEN 192
#define CONFIG_CONSOLE_UART_NUM 0
#define CONFIG_ESP_CONSOLE_UART 1
#define CONFIG_ESP_CONSOLE_UART_NUM 0
#define CONFIG_ESP32_DEBUG_OCDAWARE 1
#define CONFIG_ESP32_XTAL_FREQ 40
#define CONFIG_IDF_FIRMWARE_CHIP_ID 0x0000
#define CONFIG_LOG_DEFAULT_LEVEL 3
#define CONFIG_LOG_TIMESTAMP_SOURCE_RTOS 1
#define CONFIG_PARTITION_TABLE_OFFSET 0x8000
#define CONFIG_SPI_FLASH_ROM_DRIVER_PATCH 1
#ifdef __cplusplus
@ -37,4 +56,5 @@ extern "C" {
#endif
#endif /* DOXYGEN */
#endif /* SDKCONFIG_DEFAULT_H */
#endif /* SDKCONFIG_DEFAULT_ESP32_H */
/** @} */

62
cpu/esp32/include/sdkconfig.h Normal file
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@ -0,0 +1,62 @@
/*
* Copyright (C) 2022 Gunar Schorcht
*
* This file is subject to the terms and conditions of the GNU Lesser
* General Public License v2.1. See the file LICENSE in the top level
* directory for more details.
*/
/**
* @ingroup cpu_esp32
* @{
*
* @file
* @brief SDK configuration used by ESP-IDF for ESP32x SoCs
*
* The SDK configuration can be partially overridden by application-specific
* board configuration.
*
* @author Gunar Schorcht <gunar@schorcht.net>
*/
#ifndef SDKCONFIG_H
#define SDKCONFIG_H
/*
* The SoC capability definitions are often included indirectly in the
* ESP-IDF files, although all ESP-IDF files require them. Since not all
* ESP-IDF header files are included in RIOT, the SoC capability definitions
* are unknown if they are only indirectly included. Therefore, the SoC
* capabilities are included in this file and are thus available to all
* ESP-IDF files. This avoids to update vendor code.
*/
#include "soc/soc_caps.h"
/**
* @brief SDK version number
*
* Determined with `git describe --tags` in `$ESP32_SDK_DIR`
*/
#if !defined(IDF_VER) || DOXYGEN
#include "esp_idf_ver.h"
#endif
/**
* @brief Include ESP32x family specific SDK configuration
*/
#if defined(CPU_FAM_ESP32)
#include "sdkconfig_esp32.h"
#else
#error "ESP32x family implementation missing"
#endif
#ifdef __cplusplus
extern "C" {
#endif
#ifdef __cplusplus
}
#endif
#endif /* SDKCONFIG_H */
/** @} */

35
cpu/esp32/esp-idf/include/sdkconfig.h → cpu/esp32/include/sdkconfig_esp32.h
View File

@ -11,7 +11,7 @@
* @{
*
* @file
* @brief SDK configuration compatible to the ESP-IDF
* @brief SDK configuration used by the ESP-IDF for ESP32
*
* The SDK configuration can be partially overridden by application-specific
* board configuration.
@ -19,18 +19,8 @@
* @author Gunar Schorcht <gunar@schorcht.net>
*/
#ifndef SDKCONFIG_H
#define SDKCONFIG_H
/*
* The SoC capability definitions are often included indirectly in the
* ESP-IDF files, although all ESP-IDF files require them. Since not all
* ESP-IDF header files are included in RIOT, the SoC capability definitions
* are unknown if they are only indirectly included. Therefore, the SoC
* capabilities are included in this file and are thus available to all
* ESP-IDF files. This avoids to update vendor code.
*/
#include "soc/soc_caps.h"
#ifndef SDKCONFIG_ESP32_H
#define SDKCONFIG_ESP32_H
#ifndef DOXYGEN
@ -38,24 +28,20 @@
extern "C" {
#endif
/**
* @brief SDK version number
*
* Determined with `git describe --tags` in `$ESP32_SDK_DIR`
*/
#if !defined(IDF_VER) || DOXYGEN
#include "esp_idf_ver.h"
#endif
/**
* @name Clock configuration
* @{
*/
#ifndef DOXYGEN
/* Mapping of Kconfig defines to the respective enumeration values */
#if CONFIG_ESP32_DEFAULT_CPU_FREQ_MHZ_2
#define CONFIG_ESP32_DEFAULT_CPU_FREQ_MHZ 2
#elif CONFIG_ESP32_DEFAULT_CPU_FREQ_MHZ_5
#define CONFIG_ESP32_DEFAULT_CPU_FREQ_MHZ 5
#elif CONFIG_ESP32_DEFAULT_CPU_FREQ_MHZ_10
#define CONFIG_ESP32_DEFAULT_CPU_FREQ_MHZ 10
#elif CONFIG_ESP32_DEFAULT_CPU_FREQ_MHZ_20
#define CONFIG_ESP32_DEFAULT_CPU_FREQ_MHZ 20
#elif CONFIG_ESP32_DEFAULT_CPU_FREQ_MHZ_40
#define CONFIG_ESP32_DEFAULT_CPU_FREQ_MHZ 40
#elif CONFIG_ESP32_DEFAULT_CPU_FREQ_MHZ_80
@ -65,7 +51,6 @@ extern "C" {
#elif CONFIG_ESP32_DEFAULT_CPU_FREQ_MHZ_240
#define CONFIG_ESP32_DEFAULT_CPU_FREQ_MHZ 240
#endif
#endif
/**
* @brief Defines the CPU frequency [values = 2, 40, 80, 160 and 240]
@ -273,5 +258,5 @@ extern "C" {
#endif
#endif /* DOXYGEN */
#endif /* SDKCONFIG_H */
#endif /* SDKCONFIG_ESP32_H */
/** @} */