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makefiles: always link with gcc even if TOOLCHAIN is set to LLVM

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Fixes #8356
This commit is contained in:
Sören Tempel 2018-01-15 13:51:25 +01:00
parent 490a72ee5a
commit 18f99ef708
1 changed files with 7 additions and 4 deletions
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11
makefiles/toolchain/llvm.inc.mk
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@ -9,12 +9,14 @@ endif
export CC = clang
export CXX = clang++
export CCAS ?= $(CC)
export LINK = $(CC)
export AS = $(LLVMPREFIX)as
export AR = $(LLVMPREFIX)ar
export NM = $(LLVMPREFIX)nm
# There is no LLVM linker yet, use GNU binutils.
#export LINKER = $(LLVMPREFIX)ld
# LLVM does have a linker, however, it is not entirely
# compatible with GCC. For instance spec files as used in
# `makefiles/libc/newlib.mk` are not supported. Therefore
# we just use GCC for now.
export LINK = $(PREFIX)gcc
# objcopy does not have a clear substitute in LLVM, use GNU binutils
#export OBJCOPY = $(LLVMPREFIX)objcopy
export OBJCOPY ?= $(shell command -v $(PREFIX)objcopy gobjcopy objcopy | head -n 1)
@ -52,7 +54,8 @@ ifneq (,$(TARGET_ARCH))
# Tell clang to cross compile
export CFLAGS += -target $(TARGET_ARCH)
export CXXFLAGS += -target $(TARGET_ARCH)
export LINKFLAGS += -target $(TARGET_ARCH)
# We currently don't use LLVM for linking (see comment above).
#export LINKFLAGS += -target $(TARGET_ARCH)
# Use the wildcard Makefile function to search for existing directories matching
# the patterns above. We use the -isystem gcc/clang argument to add the include