Merge pull request #17665 from PeterKietzmann/pr_puf_sram_riscv

cpu/riscv_common: enable puf_sram feature

cpu/riscv_common/Kconfig

@@ -12,6 +12,7 @@ config CPU_ARCH_RISCV
     select HAS_NEWLIB
     select HAS_PERIPH_CORETIMER
     select HAS_PICOLIBC if '$(RIOT_CI_BUILD)' != '1'
+    select HAS_PUF_SRAM
     select HAS_RUST_TARGET
     select HAS_SSP
 

cpu/riscv_common/Makefile.features

@@ -8,6 +8,7 @@ FEATURES_PROVIDED += cpp
 FEATURES_PROVIDED += libstdcpp
 FEATURES_PROVIDED += newlib
 FEATURES_PROVIDED += periph_coretimer
+FEATURES_PROVIDED += puf_sram
 FEATURES_PROVIDED += rust_target
 FEATURES_PROVIDED += ssp
 

cpu/riscv_common/include/cpu_conf_common.h

@@ -37,6 +37,11 @@
 #endif
 /** @} */
 
+/**
+ * @brief   Attribute for memory sections required by SRAM PUF
+ */
+#define PUF_SRAM_ATTRIBUTES __attribute__((used, section(".noinit")))
+
 /**
  * @brief   Declare the heap_stats function as available
  */

cpu/riscv_common/ldscripts/riscv_base.ld

@@ -205,6 +205,17 @@ SECTIONS
     *(COMMON)
     . = ALIGN(4);
   } >ram AT>ram :ram
+  PROVIDE( __bss_end = . );
+
+  .noinit (NOLOAD) :
+  {
+      __noinit_begin__ = .;
+
+      *(.noinit .noinit.*)
+
+        . = ALIGN(4) ;
+      __noinit_end__ = .;
+  } >ram AT>ram :ram
 
   . = ALIGN(8);
   PROVIDE( _end = . );

cpu/riscv_common/riscv_init.c

@@ -21,6 +21,17 @@
 #include "cpu_conf_common.h"
 #include "periph_cpu_common.h"
 
+#ifdef MODULE_PUF_SRAM
+#include "puf_sram.h"
+
+extern unsigned _sheap;
+
+void riscv_puf_sram_init(void)
+{
+    puf_sram_init((uint8_t *)&_sheap, SEED_RAM_LEN);
+}
+#endif /* MODULE_PUF_SRAM */
+
 void riscv_fpu_init(void)
 {
     /* Enable FPU if present */

cpu/riscv_common/start.S

@@ -27,6 +27,10 @@ _start_real:
 .option pop
     la sp, _sp
 
+#ifdef MODULE_PUF_SRAM
+    /* PUF */
+    call riscv_puf_sram_init
+#endif
 
     /* Load data section */
     la a0, _data_lma
@@ -41,9 +45,10 @@ _start_real:
     bltu a1, a2, 1b
 2:
 
+
     /* Clear bss section */
     la a0, __bss_start
-    la a1, _end
+    la a1, __bss_end
     bgeu a0, a1, 2f
 1:
     sw zero, (a0)