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cpu/stm32f2: cleanup interrupt vectors definitions
This commit is contained in:
Alexandre Abadie
parent
de343a4c4f
commit
1bcb13d6ef
@ -118,102 +118,167 @@ ISR_VECTORS const void *interrupt_vector[] = {
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(void*) (&_estack), /* pointer to the top of the stack */
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/* Cortex-M3 handlers */
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(void*) reset_handler_default, /* entry point of the program */
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(void*) nmi_default, /* non maskable interrupt handler */
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(void*) hard_fault_default, /* hard fault exception */
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(void*) mem_manage_default, /* memory manage exception */
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(void*) bus_fault_default, /* bus fault exception */
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(void*) usage_fault_default, /* usage fault exception */
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(void*) (0UL), /* Reserved */
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(void*) (0UL), /* Reserved */
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(void*) (0UL), /* Reserved */
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(void*) (0UL), /* Reserved */
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(void*) isr_svc, /* system call interrupt, in RIOT used for
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* switching into thread context on boot */
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(void*) debug_mon_default, /* debug monitor exception */
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(void*) (0UL), /* Reserved */
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(void*) isr_pendsv, /* pendSV interrupt, in RIOT the actual
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* context switching is happening here */
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(void*) isr_systick, /* SysTick interrupt, not used in RIOT */
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(void*) nmi_default, /* [-14] non maskable interrupt handler */
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(void*) hard_fault_default, /* [-13] hard fault exception */
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(void*) mem_manage_default, /* [-12] memory manage exception */
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(void*) bus_fault_default, /* [-11] bus fault exception */
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(void*) usage_fault_default, /* [-10] usage fault exception */
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(void*) (0UL), /* [-9] Reserved */
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(void*) (0UL), /* [-8] Reserved */
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(void*) (0UL), /* [-7] Reserved */
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(void*) (0UL), /* [-6] Reserved */
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(void*) isr_svc, /* [-5] system call interrupt, in RIOT used for
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switching into thread context on boot */
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(void*) debug_mon_default, /* [-4] debug monitor exception */
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(void*) (0UL), /* [-3] Reserved */
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(void*) isr_pendsv, /* [-2] pendSV interrupt, in RIOT the actual
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context switching is happening here */
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(void*) isr_systick, /* [-1] SysTick interrupt, not used in RIOT */
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/* STM specific peripheral handlers */
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(void*) isr_wwdg, /* Window WatchDog */
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(void*) isr_pvd, /* PVD through EXTI Line detection */
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(void*) isr_tamp_stamp, /* Tamper and TimeStamps through the EXTI line */
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(void*) isr_rtc_wkup, /* RTC Wakeup through the EXTI line */
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(void*) isr_flash, /* FLASH */
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(void*) isr_rcc, /* RCC */
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(void*) isr_exti, /* EXTI Line0 */
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(void*) isr_exti, /* EXTI Line1 */
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(void*) isr_exti, /* EXTI Line2 */
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(void*) isr_exti, /* EXTI Line3 */
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(void*) isr_exti, /* EXTI Line4 */
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(void*) isr_dma1_stream0, /* DMA1 Stream 0 */
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(void*) isr_dma1_stream1, /* DMA1 Stream 1 */
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(void*) isr_dma1_stream2, /* DMA1 Stream 2 */
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(void*) isr_dma1_stream3, /* DMA1 Stream 3 */
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(void*) isr_dma1_stream4, /* DMA1 Stream 4 */
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(void*) isr_dma1_stream5, /* DMA1 Stream 5 */
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(void*) isr_dma1_stream6, /* DMA1 Stream 6 */
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(void*) isr_adc, /* ADC1, ADC2 and ADC3s */
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(void*) isr_can1_tx, /* CAN1 TX */
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(void*) isr_can1_rx0, /* CAN1 RX0 */
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(void*) isr_can1_rx1, /* CAN1 RX1 */
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(void*) isr_can1_sce, /* CAN1 SCE */
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(void*) isr_exti, /* External Line[9:5]s */
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(void*) isr_tim1_brk_tim9, /* TIM1 Break and TIM9 */
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(void*) isr_tim1_up_tim10, /* TIM1 Update and TIM10 */
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(void*) isr_tim1_trg_com_tim11, /* TIM1 Trigger and Commutation and TIM11 */
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(void*) isr_tim1_cc, /* TIM1 Capture Compare */
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(void*) isr_tim2, /* TIM2 */
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(void*) isr_tim3, /* TIM3 */
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(void*) isr_tim4, /* TIM4 */
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(void*) isr_i2c1_ev, /* I2C1 Event */
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(void*) isr_i2c1_er, /* I2C1 Error */
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(void*) isr_i2c2_ev, /* I2C2 Event */
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(void*) isr_i2c2_er, /* I2C2 Error */
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(void*) isr_spi1, /* SPI1 */
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(void*) isr_spi2, /* SPI2 */
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(void*) isr_usart1, /* USART1 */
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(void*) isr_usart2, /* USART2 */
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(void*) isr_usart3, /* USART3 */
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(void*) isr_exti, /* External Line[15:10]s */
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(void*) isr_rtc_alarm, /* RTC Alarm (A and B) through EXTI Line */
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(void*) isr_otg_fs_wkup, /* USB OTG FS Wakeup through EXTI line */
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(void*) isr_tim8_brk_tim12, /* TIM8 Break and TIM12 */
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(void*) isr_tim8_up_tim13, /* TIM8 Update and TIM13 */
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(void*) isr_tim8_trg_com_tim14, /* TIM8 Trigger and Commutation and TIM14 */
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(void*) isr_tim8_cc, /* TIM8 Capture Compare */
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(void*) isr_dma1_stream7, /* DMA1 Stream7 */
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(void*) isr_fsmc, /* FSMC */
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(void*) isr_sdio, /* SDIO */
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(void*) isr_tim5, /* TIM5 */
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(void*) isr_spi3, /* SPI3 */
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(void*) isr_uart4, /* UART4 */
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(void*) isr_uart5, /* UART5 */
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(void*) isr_tim6_dac, /* TIM6 and DAC1&2 underrun errors */
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(void*) isr_tim7, /* TIM7 */
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(void*) isr_dma2_stream0, /* DMA2 Stream 0 */
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(void*) isr_dma2_stream1, /* DMA2 Stream 1 */
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(void*) isr_dma2_stream2, /* DMA2 Stream 2 */
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(void*) isr_dma2_stream3, /* DMA2 Stream 3 */
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(void*) isr_dma2_stream4, /* DMA2 Stream 4 */
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(void*) isr_eth, /* Ethernet */
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(void*) isr_eth_wkup, /* Ethernet Wakeup through EXTI line */
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(void*) isr_can2_tx, /* CAN2 TX */
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(void*) isr_can2_rx0, /* CAN2 RX0 */
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(void*) isr_can2_rx1, /* CAN2 RX1 */
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(void*) isr_can2_sce, /* CAN2 SCE */
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(void*) isr_otg_fs, /* USB OTG FS */
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(void*) isr_dma2_stream5, /* DMA2 Stream 5 */
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(void*) isr_dma2_stream6, /* DMA2 Stream 6 */
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(void*) isr_dma2_stream7, /* DMA2 Stream 7 */
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(void*) isr_usart6, /* USART6 */
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(void*) isr_i2c3_ev, /* I2C3 event */
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(void*) isr_i2c3_er, /* I2C3 error */
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(void*) isr_otg_hs_ep1_out, /* USB OTG HS End Point 1 Out */
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(void*) isr_otg_hs_ep1_in, /* USB OTG HS End Point 1 In */
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(void*) isr_otg_hs_wkup, /* USB OTG HS Wakeup through EXTI */
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(void*) isr_otg_hs, /* USB OTG HS */
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(void*) isr_dcmi, /* DCMI */
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(void*) isr_cryp, /* CRYP crypto */
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(void*) isr_hash_rng, /* Hash and Rng */
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(void*) isr_wwdg, /* [0] Window WatchDog */
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(void*) isr_pvd, /* [1] PVD through EXTI Line detection */
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(void*) isr_tamp_stamp, /* [2] Tamper and TimeStamps through the EXTI line */
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(void*) isr_rtc_wkup, /* [3] RTC Wakeup through the EXTI line */
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(void*) isr_flash, /* [4] FLASH */
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(void*) isr_rcc, /* [5] RCC */
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(void*) isr_exti, /* [6] EXTI Line0 */
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(void*) isr_exti, /* [7] EXTI Line1 */
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(void*) isr_exti, /* [8] EXTI Line2 */
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(void*) isr_exti, /* [9] EXTI Line3 */
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(void*) isr_exti, /* [10] EXTI Line4 */
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(void*) isr_dma1_stream0, /* [11] DMA1 Stream 0 */
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(void*) isr_dma1_stream1, /* [12] DMA1 Stream 1 */
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(void*) isr_dma1_stream2, /* [13] DMA1 Stream 2 */
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(void*) isr_dma1_stream3, /* [14] DMA1 Stream 3 */
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(void*) isr_dma1_stream4, /* [15] DMA1 Stream 4 */
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(void*) isr_dma1_stream5, /* [16] DMA1 Stream 5 */
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(void*) isr_dma1_stream6, /* [17] DMA1 Stream 6 */
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(void*) isr_adc, /* [18] ADC1, ADC2 and ADC3s */
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(void*) isr_can1_tx, /* [19] CAN1 TX */
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(void*) isr_can1_rx0, /* [20] CAN1 RX0 */
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(void*) isr_can1_rx1, /* [21] CAN1 RX1 */
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(void*) isr_can1_sce, /* [22] CAN1 SCE */
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(void*) isr_exti, /* [23] External Line[9:5]s */
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(void*) isr_tim1_brk_tim9, /* [24] TIM1 Break and TIM9 */
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(void*) isr_tim1_up_tim10, /* [25] TIM1 Update and TIM10 */
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(void*) isr_tim1_trg_com_tim11, /* [26] TIM1 Trigger and Commutation and TIM11 */
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(void*) isr_tim1_cc, /* [27] TIM1 Capture Compare */
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(void*) isr_tim2, /* [28] TIM2 */
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(void*) isr_tim3, /* [29] TIM3 */
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(void*) isr_tim4, /* [30] TIM4 */
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(void*) isr_i2c1_ev, /* [31] I2C1 Event */
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(void*) isr_i2c1_er, /* [32] I2C1 Error */
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(void*) isr_i2c2_ev, /* [33] I2C2 Event */
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(void*) isr_i2c2_er, /* [34] I2C2 Error */
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(void*) isr_spi1, /* [35] SPI1 */
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(void*) isr_spi2, /* [36] SPI2 */
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(void*) isr_usart1, /* [37] USART1 */
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(void*) isr_usart2, /* [38] USART2 */
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(void*) isr_usart3, /* [39] USART3 */
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(void*) isr_exti, /* [40] External Line[15:10]s */
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(void*) isr_rtc_alarm, /* [41] RTC Alarm (A and B) through EXTI Line */
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(void*) isr_otg_fs_wkup, /* [42] USB OTG FS Wakeup through EXTI line */
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(void*) isr_tim8_brk_tim12, /* [43] TIM8 Break and TIM12 */
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(void*) isr_tim8_up_tim13, /* [44] TIM8 Update and TIM13 */
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(void*) isr_tim8_trg_com_tim14, /* [45] TIM8 Trigger and Commutation and TIM14 */
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(void*) isr_tim8_cc, /* [46] TIM8 Capture Compare */
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(void*) isr_dma1_stream7, /* [47] DMA1 Stream7 */
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(void*) isr_fsmc, /* [48] FSMC */
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(void*) isr_sdio, /* [49] SDIO */
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(void*) isr_tim5, /* [50] TIM5 */
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(void*) isr_spi3, /* [51] SPI3 */
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(void*) isr_uart4, /* [52] UART4 */
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(void*) isr_uart5, /* [53] UART5 */
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(void*) isr_tim6_dac, /* [54] TIM6 and DAC1&2 underrun errors */
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(void*) isr_tim7, /* [55] TIM7 */
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(void*) isr_dma2_stream0, /* [56] DMA2 Stream 0 */
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(void*) isr_dma2_stream1, /* [57] DMA2 Stream 1 */
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(void*) isr_dma2_stream2, /* [58] DMA2 Stream 2 */
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(void*) isr_dma2_stream3, /* [59] DMA2 Stream 3 */
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(void*) isr_dma2_stream4, /* [60] DMA2 Stream 4 */
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#if defined(CPU_MODEL_STM32F205RG)
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(void*) (0UL), /* [61] Reserved */
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(void*) (0UL), /* [62] Reserved */
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(void*) isr_can2_tx, /* [63] CAN2 TX */
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(void*) isr_can2_rx0, /* [64] CAN2 RX0 */
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(void*) isr_can2_rx1, /* [65] CAN2 RX1 */
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(void*) isr_can2_sce, /* [66] CAN2 SCE */
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(void*) isr_otg_fs, /* [67] USB OTG FS */
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(void*) isr_dma2_stream5, /* [68] DMA2 Stream 5 */
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(void*) isr_dma2_stream6, /* [69] DMA2 Stream 6 */
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(void*) isr_dma2_stream7, /* [70] DMA2 Stream 7 */
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(void*) isr_usart6, /* [71] USART6 */
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(void*) isr_i2c3_ev, /* [72] I2C3 event */
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(void*) isr_i2c3_er, /* [73] I2C3 error */
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(void*) isr_otg_hs_ep1_out, /* [74] USB OTG HS End Point 1 Out */
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(void*) isr_otg_hs_ep1_in, /* [75] USB OTG HS End Point 1 In */
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(void*) isr_otg_hs_wkup, /* [76] USB OTG HS Wakeup through EXTI */
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(void*) isr_otg_hs, /* [77] USB OTG HS */
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(void*) (0UL), /* [78] Reserved */
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(void*) (0UL), /* [79] Reserved */
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(void*) isr_hash_rng, /* [80] Hash and Rng */
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#elif defined(CPU_MODEL_STM32F207ZG)
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(void*) isr_eth, /* [61] Ethernet */
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(void*) isr_eth_wkup, /* [62] Ethernet Wakeup through EXTI line */
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(void*) isr_can2_tx, /* [63] CAN2 TX */
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(void*) isr_can2_rx0, /* [64] CAN2 RX0 */
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(void*) isr_can2_rx1, /* [65] CAN2 RX1 */
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(void*) isr_can2_sce, /* [66] CAN2 SCE */
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(void*) isr_otg_fs, /* [67] USB OTG FS */
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(void*) isr_dma2_stream5, /* [68] DMA2 Stream 5 */
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(void*) isr_dma2_stream6, /* [69] DMA2 Stream 6 */
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(void*) isr_dma2_stream7, /* [70] DMA2 Stream 7 */
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(void*) isr_usart6, /* [71] USART6 */
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(void*) isr_i2c3_ev, /* [72] I2C3 event */
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(void*) isr_i2c3_er, /* [73] I2C3 error */
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(void*) isr_otg_hs_ep1_out, /* [74] USB OTG HS End Point 1 Out */
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(void*) isr_otg_hs_ep1_in, /* [75] USB OTG HS End Point 1 In */
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(void*) isr_otg_hs_wkup, /* [76] USB OTG HS Wakeup through EXTI */
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(void*) isr_otg_hs, /* [77] USB OTG HS */
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(void*) isr_dcmi, /* [78] DCMI */
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(void*) (0UL), /* [79] Reserved */
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(void*) isr_hash_rng, /* [80] Hash and Rng */
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#elif defined(CPU_MODEL_STM32F215RG) || defined (CPU_MODEL_STM32F215VG)
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(void*) (0UL), /* [61] Reserved */
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(void*) (0UL), /* [62] Reserved */
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(void*) isr_can2_tx, /* [63] CAN2 TX */
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(void*) isr_can2_rx0, /* [64] CAN2 RX0 */
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(void*) isr_can2_rx1, /* [65] CAN2 RX1 */
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(void*) isr_can2_sce, /* [66] CAN2 SCE */
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(void*) isr_otg_fs, /* [67] USB OTG FS */
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(void*) isr_dma2_stream5, /* [68] DMA2 Stream 5 */
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(void*) isr_dma2_stream6, /* [69] DMA2 Stream 6 */
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(void*) isr_dma2_stream7, /* [70] DMA2 Stream 7 */
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(void*) isr_usart6, /* [71] USART6 */
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(void*) isr_i2c3_ev, /* [72] I2C3 event */
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(void*) isr_i2c3_er, /* [73] I2C3 error */
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(void*) isr_otg_hs_ep1_out, /* [74] USB OTG HS End Point 1 Out */
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(void*) isr_otg_hs_ep1_in, /* [75] USB OTG HS End Point 1 In */
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(void*) isr_otg_hs_wkup, /* [76] USB OTG HS Wakeup through EXTI */
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(void*) isr_otg_hs, /* [77] USB OTG HS */
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(void*) (0UL), /* [78] Reserved */
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(void*) isr_cryp, /* [79] CRYP crypto */
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(void*) isr_hash_rng, /* [80] Hash and Rng */
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#else /* CPU_MODEL_STM32F217ZG */
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(void*) isr_eth, /* [61] Ethernet */
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(void*) isr_eth_wkup, /* [62] Ethernet Wakeup through EXTI line */
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(void*) isr_can2_tx, /* [63] CAN2 TX */
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(void*) isr_can2_rx0, /* [64] CAN2 RX0 */
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(void*) isr_can2_rx1, /* [65] CAN2 RX1 */
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(void*) isr_can2_sce, /* [66] CAN2 SCE */
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(void*) isr_otg_fs, /* [67] USB OTG FS */
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(void*) isr_dma2_stream5, /* [68] DMA2 Stream 5 */
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(void*) isr_dma2_stream6, /* [69] DMA2 Stream 6 */
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(void*) isr_dma2_stream7, /* [70] DMA2 Stream 7 */
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(void*) isr_usart6, /* [71] USART6 */
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(void*) isr_i2c3_ev, /* [72] I2C3 event */
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(void*) isr_i2c3_er, /* [73] I2C3 error */
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(void*) isr_otg_hs_ep1_out, /* [74] USB OTG HS End Point 1 Out */
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(void*) isr_otg_hs_ep1_in, /* [75] USB OTG HS End Point 1 In */
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(void*) isr_otg_hs_wkup, /* [76] USB OTG HS Wakeup through EXTI */
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(void*) isr_otg_hs, /* [77] USB OTG HS */
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(void*) isr_dcmi, /* [78] DCMI */
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(void*) isr_cryp, /* [79] CRYP crypto */
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(void*) isr_hash_rng, /* [80] Hash and Rng */
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#endif
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};
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