From 264a7c8ef979c357cccdd67fbbbc6f88cd66991e Mon Sep 17 00:00:00 2001 From: Joshua DeWeese Date: Fri, 7 Oct 2022 15:35:47 -0400 Subject: [PATCH] cpu/stm32/periph/dma: fix DMA2 on STMF3 families As it was, the calculation of DMA2's IRQ number was inccrorect for some STM families. The implmentation alocates streams numbers 0 to 7 for the first DMA controller and 8 and up for the second DMA controller. This offset of +8 was not accounted for when IRQ's of the second DMA controller was calculated. This patch corrects this. --- cpu/stm32/include/periph/cpu_dma.h | 2 +- cpu/stm32/periph/dma.c | 14 ++++++++++---- 2 files changed, 11 insertions(+), 5 deletions(-) diff --git a/cpu/stm32/include/periph/cpu_dma.h b/cpu/stm32/include/periph/cpu_dma.h index 74dd58e8cd..bcdfc1ce95 100644 --- a/cpu/stm32/include/periph/cpu_dma.h +++ b/cpu/stm32/include/periph/cpu_dma.h @@ -38,7 +38,7 @@ typedef struct { * - 8: DAM2 / Stream0 * - ... * - 15: DMA2 / Stream7 - * STM32F0/1/L0/1/4: + * STM32F0/1/3/L0/1/4: * - 0: DMA1 / Channel1 * - ... * - 4: DMA1 / Channel5 diff --git a/cpu/stm32/periph/dma.c b/cpu/stm32/periph/dma.c index c61106f6b8..8f4d7b9f43 100644 --- a/cpu/stm32/periph/dma.c +++ b/cpu/stm32/periph/dma.c @@ -193,22 +193,28 @@ static IRQn_Type dma_get_irqn(int stream) return ((IRQn_Type)((int)DMA1_Channel1_IRQn + stream)); } #if defined(DMA2_BASE) + /* stream 7 is invalid for these CPU families */ + else if (stream == 7) { + return -1; + } #if defined(CPU_FAM_STM32F1) else if (stream < 11) { #else else if (stream < 13 ) { #endif - return ((IRQn_Type)((int)DMA2_Channel1_IRQn + stream)); + /* magic number 8 is first DMA2 stream */ + return ((IRQn_Type)((int)DMA2_Channel1_IRQn + stream - 8)); } -#if !defined(CPU_FAM_STM32L1) +#if !defined(CPU_FAM_STM32L1) && !defined(CPU_FAM_STM32F3) else { #if defined(CPU_FAM_STM32F1) return (DMA2_Channel4_5_IRQn); #else - return ((IRQn_Type)((int)DMA2_Channel6_IRQn + stream)); + /* magic number 13 is 8 (first DMA2 stream) + 5 (Channel6) */ + return ((IRQn_Type)((int)DMA2_Channel6_IRQn + stream - 13)); #endif } -#endif /* !defined(CPU_FAM_STM32L1) */ +#endif /* !defined(CPU_FAM_STM32L1) && !defined(CPU_FAM_STM32F3) */ #endif /* defined(DMA2_BASE) */ #endif