From 28c131eaeee0252d4764d6a2eae8699cc1d03d33 Mon Sep 17 00:00:00 2001
From: Michel Rottleuthner <michel.rottleuthner@haw-hamburg.de>
Date: Mon, 15 Jan 2018 14:41:06 +0100
Subject: [PATCH] boards/b-l475e-iot01a: add defines for MSI/LSE-trimming

---
 boards/b-l475e-iot01a/include/periph_conf.h | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/boards/b-l475e-iot01a/include/periph_conf.h b/boards/b-l475e-iot01a/include/periph_conf.h
index 2045267b41..d5bebd9ce8 100644
--- a/boards/b-l475e-iot01a/include/periph_conf.h
+++ b/boards/b-l475e-iot01a/include/periph_conf.h
@@ -35,6 +35,12 @@ extern "C" {
 /* 0: no external low speed crystal available,
  * 1: external crystal available (always 32.768kHz) */
 #define CLOCK_LSE           (1)
+/* 0: enable MSI only if HSE isn't available
+ * 1: always enable MSI (e.g. if USB or RNG is used)*/
+#define CLOCK_MSI_ENABLE    (1)
+/* 0: disable Hardware auto calibration with LSE
+ * 1: enable Hardware auto calibration with LSE (PLL-mode)*/
+#define CLOCK_MSI_LSE_PLL   (1)
 /* give the target core clock (HCLK) frequency [in Hz], maximum: 80MHz */
 #define CLOCK_CORECLOCK     (80000000U)
 /* PLL configuration: make sure your values are legit!