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cpu/stm32f0: Add support for stm32f030cc CPU

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This commit is contained in:
Wojciech Nizinski 2019-03-06 14:37:07 +01:00
parent 7b9181ea6f
commit 292e979e61
4 changed files with 5877 additions and 1 deletions
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4
cpu/stm32f0/include/cpu_conf.h
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@ -45,6 +45,7 @@ extern "C" {
#else
#define CPU_IRQ_NUMOF (32U)
#endif
#define CPU_FLASH_BASE FLASH_BASE
/** @} */
/**
@ -55,7 +56,8 @@ extern "C" {
*
* @{
*/
#if defined(CPU_LINE_STM32F091xC) || defined(CPU_LINE_STM32F072xB)
#if defined(CPU_LINE_STM32F091xC) || defined(CPU_LINE_STM32F072xB) \
|| defined(CPU_LINE_STM32F030xC)
#define FLASHPAGE_SIZE (2048U)
#elif defined(CPU_LINE_STM32F051x8) || defined(CPU_LINE_STM32F042x6) \
|| defined(CPU_LINE_STM32F070xB) || defined(CPU_LINE_STM32F030x8)

5852
cpu/stm32f0/include/vendor/stm32f030xc.h vendored Normal file
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File diff suppressed because it is too large Load Diff

2
cpu/stm32f0/stm32_line.mk
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@ -11,6 +11,8 @@ ifneq (, $(filter $(TYPE), 030 031 042 070))
CPU_LINE = STM32F$(TYPE)x8
else ifneq (, $(filter $(MODEL2), B))
CPU_LINE = STM32F$(TYPE)xB
else ifneq (, $(filter $(MODEL2), C))
CPU_LINE = STM32F$(TYPE)xC
endif
else ifneq (, $(filter $(TYPE), 051))
CPU_LINE = STM32F$(TYPE)x8

20
cpu/stm32f0/vectors.c
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@ -63,6 +63,7 @@ WEAK_DEFAULT void isr_tsc(void);
WEAK_DEFAULT void isr_usart1(void);
WEAK_DEFAULT void isr_usart2(void);
WEAK_DEFAULT void isr_usart3_4(void);
WEAK_DEFAULT void isr_usart3_6(void);
WEAK_DEFAULT void isr_usart3_8(void);
WEAK_DEFAULT void isr_usb(void);
WEAK_DEFAULT void isr_wwdg(void);
@ -218,5 +219,24 @@ ISR_VECTOR(1) const isr_t vector_cpu[CPU_IRQ_NUMOF] = {
[28] = isr_usart2, /* [28] USART2 global Interrupt & EXTI Line26 Interrupt (USART2 wakeup) */
[29] = isr_usart3_8, /* [29] USART3 to USART8 global Interrupts */
[30] = isr_cec_can, /* [30] CEC and CAN global Interrupts & EXTI Line27 Interrupt */
#elif defined(CPU_LINE_STM32F030xC)
[ 4] = isr_rcc, /* [ 4] RCC global Interrupt */
[ 5] = isr_exti, /* [ 5] EXTI Line 0 and 1 Interrupt */
[ 6] = isr_exti, /* [ 6] EXTI Line 2 and 3 Interrupt */
[ 7] = isr_exti, /* [ 7] EXTI Line 4 to 15 Interrupt */
[ 9] = isr_dma1_channel1, /* [ 9] DMA1 Channel 1 Interrupt */
[10] = isr_dma1_channel2_3, /* [10] DMA1 Channel 2 and Channel 3 Interrupt */
[11] = isr_dma1_channel4_5, /* [11] DMA1 Channel 4 and Channel 5 Interrupt */
[12] = isr_adc1, /* [12] ADC1 Interrupt */
[13] = isr_tim1_brk_up_trg_com, /* [13] TIM1 Break, Update, Trigger and Commutation Interrupt */
[17] = isr_tim6, /* [17] TIM6 global Interrupt */
[18] = isr_tim7, /* [18] TIM7 global Interrupt */
[20] = isr_tim15, /* [20] TIM15 global Interrupt */
[23] = isr_i2c1, /* [23] I2C1 Event Interrupt & EXTI Line23 Interrupt (I2C1 wakeup) */
[24] = isr_i2c2, /* [24] I2C2 Event Interrupt */
[26] = isr_spi2, /* [26] SPI2 global Interrupt */
[27] = isr_usart1, /* [27] USART1 global Interrupt */
[28] = isr_usart2, /* [28] USART2 global Interrupt */
[29] = isr_usart3_6, /* [29] USART3..6 global Interrupt */
#endif
};