diff --git a/cpu/k22f/include/vendor/MK22F12810.h b/cpu/k22f/include/vendor/MK22F12810.h index 60a54873e9..13159c2a60 100644 --- a/cpu/k22f/include/vendor/MK22F12810.h +++ b/cpu/k22f/include/vendor/MK22F12810.h @@ -1,21 +1,25 @@ /* ** ################################################################### +** Processors: MK22FN128VDC10 +** MK22FN128VLH10 +** MK22FN128VLL10 +** MK22FN128VMP10 +** ** Compilers: Keil ARM C/C++ Compiler ** Freescale C/C++ for Embedded ARM ** GNU C Compiler -** GNU C Compiler - CodeSourcery Sourcery G++ ** IAR ANSI C/C++ Compiler for ARM +** MCUXpresso Compiler ** ** Reference manual: K22P121M100SF9RM, Rev. 1, April 25, 2014 ** Version: rev. 1.6, 2015-02-19 -** Build: b150225 +** Build: b170112 ** ** Abstract: ** CMSIS Peripheral Access Layer for MK22F12810 ** -** Copyright (c) 1997 - 2015 Freescale Semiconductor, Inc. -** All rights reserved. -** +** Copyright (c) 1997 - 2016 Freescale Semiconductor, Inc. +** Copyright 2016 - 2017 NXP ** Redistribution and use in source and binary forms, with or without modification, ** are permitted provided that the following conditions are met: ** @@ -26,7 +30,7 @@ ** list of conditions and the following disclaimer in the documentation and/or ** other materials provided with the distribution. ** -** o Neither the name of Freescale Semiconductor, Inc. nor the names of its +** o Neither the name of the copyright holder nor the names of its ** contributors may be used to endorse or promote products derived from this ** software without specific prior written permission. ** @@ -41,8 +45,8 @@ ** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ** -** http: www.freescale.com -** mail: support@freescale.com +** http: www.nxp.com +** mail: support@nxp.com ** ** Revisions: ** - rev. 1.0 (2013-11-01) @@ -75,29 +79,14 @@ * CMSIS Peripheral Access Layer for MK22F12810 */ - -/* ---------------------------------------------------------------------------- - -- MCU activation - ---------------------------------------------------------------------------- */ - -/* Prevention from multiple including the same memory map */ -#if !defined(MK22F12810_H_) /* Check if memory map has not been already included */ -#define MK22F12810_H_ -#define MCU_MK22F12810 - -/* Check if another memory map has not been also included */ -#if (defined(MCU_ACTIVE)) - #error MK22F12810 memory map: There is already included another memory map. Only one memory map can be included. -#endif /* (defined(MCU_ACTIVE)) */ -#define MCU_ACTIVE - -#include +#ifndef _MK22F12810_H_ +#define _MK22F12810_H_ /**< Symbol preventing repeated inclusion */ /** Memory map major version (memory maps with equal major version number are * compatible) */ -#define MCU_MEM_MAP_VERSION 0x0100u +#define MCU_MEM_MAP_VERSION 0x0100U /** Memory map minor version */ -#define MCU_MEM_MAP_VERSION_MINOR 0x0006u +#define MCU_MEM_MAP_VERSION_MINOR 0x0006U /** * @brief Macro to calculate address of an aliased word in the peripheral @@ -116,8 +105,8 @@ * @param Bit Bit number to access. * @return Value of the targeted bit in the bit band region. */ -#define BITBAND_REG32(Reg,Bit) (*((uint32_t volatile*)(BITBAND_REGADDR(Reg,Bit)))) -#define BITBAND_REG(Reg,Bit) (BITBAND_REG32(Reg,Bit)) +#define BITBAND_REG32(Reg,Bit) (*((uint32_t volatile*)(BITBAND_REGADDR((Reg),(Bit))))) +#define BITBAND_REG(Reg,Bit) (BITBAND_REG32((Reg),(Bit))) /** * @brief Macro to access a single bit of a peripheral register (bit band region * 0x40000000 to 0x400FFFFF) using the bit-band alias region access. Can @@ -126,7 +115,7 @@ * @param Bit Bit number to access. * @return Value of the targeted bit in the bit band region. */ -#define BITBAND_REG16(Reg,Bit) (*((uint16_t volatile*)(BITBAND_REGADDR(Reg,Bit)))) +#define BITBAND_REG16(Reg,Bit) (*((uint16_t volatile*)(BITBAND_REGADDR((Reg),(Bit))))) /** * @brief Macro to access a single bit of a peripheral register (bit band region * 0x40000000 to 0x400FFFFF) using the bit-band alias region access. Can @@ -135,7 +124,7 @@ * @param Bit Bit number to access. * @return Value of the targeted bit in the bit band region. */ -#define BITBAND_REG8(Reg,Bit) (*((uint8_t volatile*)(BITBAND_REGADDR(Reg,Bit)))) +#define BITBAND_REG8(Reg,Bit) (*((uint8_t volatile*)(BITBAND_REGADDR((Reg),(Bit))))) /* ---------------------------------------------------------------------------- -- Interrupt vector numbers @@ -279,6 +268,108 @@ typedef enum IRQn { */ /* end of group Cortex_Core_Configuration */ +/* ---------------------------------------------------------------------------- + -- Mapping Information + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup Mapping_Information Mapping Information + * @{ + */ + +/** Mapping Information */ +/*! + * @addtogroup edma_request + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! + * @brief Structure for the DMA hardware request + * + * Defines the structure for the DMA hardware request collections. The user can configure the + * hardware request into DMAMUX to trigger the DMA transfer accordingly. The index + * of the hardware request varies according to the to SoC. + */ +typedef enum _dma_request_source +{ + kDmaRequestMux0Disable = 0|0x100U, /**< DMAMUX TriggerDisabled. */ + kDmaRequestMux0Reserved1 = 1|0x100U, /**< Reserved1 */ + kDmaRequestMux0UART0Rx = 2|0x100U, /**< UART0 Receive. */ + kDmaRequestMux0UART0Tx = 3|0x100U, /**< UART0 Transmit. */ + kDmaRequestMux0UART1Rx = 4|0x100U, /**< UART1 Receive. */ + kDmaRequestMux0UART1Tx = 5|0x100U, /**< UART1 Transmit. */ + kDmaRequestMux0UART2Rx = 6|0x100U, /**< UART2 Receive. */ + kDmaRequestMux0UART2Tx = 7|0x100U, /**< UART2 Transmit. */ + kDmaRequestMux0Reserved8 = 8|0x100U, /**< Reserved8 */ + kDmaRequestMux0Reserved9 = 9|0x100U, /**< Reserved9 */ + kDmaRequestMux0Reserved10 = 10|0x100U, /**< Reserved10 */ + kDmaRequestMux0Reserved11 = 11|0x100U, /**< Reserved11 */ + kDmaRequestMux0I2S0Rx = 12|0x100U, /**< I2S0 Receive. */ + kDmaRequestMux0I2S0Tx = 13|0x100U, /**< I2S0 Transmit. */ + kDmaRequestMux0SPI0Rx = 14|0x100U, /**< SPI0 Receive. */ + kDmaRequestMux0SPI0Tx = 15|0x100U, /**< SPI0 Transmit. */ + kDmaRequestMux0SPI1 = 16|0x100U, /**< SPI1 Transmit or Receive. */ + kDmaRequestMux0Reserved17 = 17|0x100U, /**< Reserved17 */ + kDmaRequestMux0I2C0 = 18|0x100U, /**< I2C0. */ + kDmaRequestMux0I2C1 = 19|0x100U, /**< I2C1. */ + kDmaRequestMux0FTM0Channel0 = 20|0x100U, /**< FTM0 C0V. */ + kDmaRequestMux0FTM0Channel1 = 21|0x100U, /**< FTM0 C1V. */ + kDmaRequestMux0FTM0Channel2 = 22|0x100U, /**< FTM0 C2V. */ + kDmaRequestMux0FTM0Channel3 = 23|0x100U, /**< FTM0 C3V. */ + kDmaRequestMux0FTM0Channel4 = 24|0x100U, /**< FTM0 C4V. */ + kDmaRequestMux0FTM0Channel5 = 25|0x100U, /**< FTM0 C5V. */ + kDmaRequestMux0FTM0Channel6 = 26|0x100U, /**< FTM0 C6V. */ + kDmaRequestMux0FTM0Channel7 = 27|0x100U, /**< FTM0 C7V. */ + kDmaRequestMux0FTM1Channel0 = 28|0x100U, /**< FTM1 C0V. */ + kDmaRequestMux0FTM1Channel1 = 29|0x100U, /**< FTM1 C1V. */ + kDmaRequestMux0FTM2Channel0 = 30|0x100U, /**< FTM2 C0V. */ + kDmaRequestMux0FTM2Channel1 = 31|0x100U, /**< FTM2 C1V. */ + kDmaRequestMux0Reserved32 = 32|0x100U, /**< Reserved32 */ + kDmaRequestMux0Reserved33 = 33|0x100U, /**< Reserved33 */ + kDmaRequestMux0Reserved34 = 34|0x100U, /**< Reserved34 */ + kDmaRequestMux0Reserved35 = 35|0x100U, /**< Reserved35 */ + kDmaRequestMux0Reserved36 = 36|0x100U, /**< Reserved36 */ + kDmaRequestMux0Reserved37 = 37|0x100U, /**< Reserved37 */ + kDmaRequestMux0Reserved38 = 38|0x100U, /**< Reserved38 */ + kDmaRequestMux0Reserved39 = 39|0x100U, /**< Reserved39 */ + kDmaRequestMux0ADC0 = 40|0x100U, /**< ADC0. */ + kDmaRequestMux0ADC1 = 41|0x100U, /**< ADC1. */ + kDmaRequestMux0CMP0 = 42|0x100U, /**< CMP0. */ + kDmaRequestMux0CMP1 = 43|0x100U, /**< CMP1. */ + kDmaRequestMux0Reserved44 = 44|0x100U, /**< Reserved44 */ + kDmaRequestMux0DAC0 = 45|0x100U, /**< DAC0. */ + kDmaRequestMux0Reserved46 = 46|0x100U, /**< Reserved46 */ + kDmaRequestMux0Reserved47 = 47|0x100U, /**< Reserved47 */ + kDmaRequestMux0PDB = 48|0x100U, /**< PDB0. */ + kDmaRequestMux0PortA = 49|0x100U, /**< PTA. */ + kDmaRequestMux0PortB = 50|0x100U, /**< PTB. */ + kDmaRequestMux0PortC = 51|0x100U, /**< PTC. */ + kDmaRequestMux0PortD = 52|0x100U, /**< PTD. */ + kDmaRequestMux0PortE = 53|0x100U, /**< PTE. */ + kDmaRequestMux0Reserved54 = 54|0x100U, /**< Reserved54 */ + kDmaRequestMux0Reserved55 = 55|0x100U, /**< Reserved55 */ + kDmaRequestMux0Reserved56 = 56|0x100U, /**< Reserved56 */ + kDmaRequestMux0Reserved57 = 57|0x100U, /**< Reserved57 */ + kDmaRequestMux0LPUART0Rx = 58|0x100U, /**< LPUART0 Receive. */ + kDmaRequestMux0LPUART0Tx = 59|0x100U, /**< LPUART0 Transmit. */ + kDmaRequestMux0AlwaysOn60 = 60|0x100U, /**< DMAMUX Always Enabled slot. */ + kDmaRequestMux0AlwaysOn61 = 61|0x100U, /**< DMAMUX Always Enabled slot. */ + kDmaRequestMux0AlwaysOn62 = 62|0x100U, /**< DMAMUX Always Enabled slot. */ + kDmaRequestMux0AlwaysOn63 = 63|0x100U, /**< DMAMUX Always Enabled slot. */ +} dma_request_source_t; + +/* @} */ + + +/*! + * @} + */ /* end of group Mapping_Information */ + + /* ---------------------------------------------------------------------------- -- Device Peripheral Access Layer ---------------------------------------------------------------------------- */ @@ -344,51 +435,7 @@ typedef struct { __IO uint32_t CLM2; /**< ADC Minus-Side General Calibration Value Register, offset: 0x64 */ __IO uint32_t CLM1; /**< ADC Minus-Side General Calibration Value Register, offset: 0x68 */ __IO uint32_t CLM0; /**< ADC Minus-Side General Calibration Value Register, offset: 0x6C */ -} ADC_Type, *ADC_MemMapPtr; - -/* ---------------------------------------------------------------------------- - -- ADC - Register accessor macros - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup ADC_Register_Accessor_Macros ADC - Register accessor macros - * @{ - */ - - -/* ADC - Register accessors */ -#define ADC_SC1_REG(base,index) ((base)->SC1[index]) -#define ADC_SC1_COUNT 2 -#define ADC_CFG1_REG(base) ((base)->CFG1) -#define ADC_CFG2_REG(base) ((base)->CFG2) -#define ADC_R_REG(base,index) ((base)->R[index]) -#define ADC_R_COUNT 2 -#define ADC_CV1_REG(base) ((base)->CV1) -#define ADC_CV2_REG(base) ((base)->CV2) -#define ADC_SC2_REG(base) ((base)->SC2) -#define ADC_SC3_REG(base) ((base)->SC3) -#define ADC_OFS_REG(base) ((base)->OFS) -#define ADC_PG_REG(base) ((base)->PG) -#define ADC_MG_REG(base) ((base)->MG) -#define ADC_CLPD_REG(base) ((base)->CLPD) -#define ADC_CLPS_REG(base) ((base)->CLPS) -#define ADC_CLP4_REG(base) ((base)->CLP4) -#define ADC_CLP3_REG(base) ((base)->CLP3) -#define ADC_CLP2_REG(base) ((base)->CLP2) -#define ADC_CLP1_REG(base) ((base)->CLP1) -#define ADC_CLP0_REG(base) ((base)->CLP0) -#define ADC_CLMD_REG(base) ((base)->CLMD) -#define ADC_CLMS_REG(base) ((base)->CLMS) -#define ADC_CLM4_REG(base) ((base)->CLM4) -#define ADC_CLM3_REG(base) ((base)->CLM3) -#define ADC_CLM2_REG(base) ((base)->CLM2) -#define ADC_CLM1_REG(base) ((base)->CLM1) -#define ADC_CLM0_REG(base) ((base)->CLM0) - -/*! - * @} - */ /* end of group ADC_Register_Accessor_Macros */ - +} ADC_Type; /* ---------------------------------------------------------------------------- -- ADC Register Masks @@ -399,211 +446,197 @@ typedef struct { * @{ */ -/* SC1 Bit Fields */ -#define ADC_SC1_ADCH_MASK 0x1Fu -#define ADC_SC1_ADCH_SHIFT 0 -#define ADC_SC1_ADCH_WIDTH 5 -#define ADC_SC1_ADCH(x) (((uint32_t)(((uint32_t)(x))<CR0) -#define CMP_CR1_REG(base) ((base)->CR1) -#define CMP_FPR_REG(base) ((base)->FPR) -#define CMP_SCR_REG(base) ((base)->SCR) -#define CMP_DACCR_REG(base) ((base)->DACCR) -#define CMP_MUXCR_REG(base) ((base)->MUXCR) - -/*! - * @} - */ /* end of group CMP_Register_Accessor_Macros */ - +} CMP_Type; /* ---------------------------------------------------------------------------- -- CMP Register Masks @@ -763,100 +692,84 @@ typedef struct { * @{ */ -/* CR0 Bit Fields */ -#define CMP_CR0_HYSTCTR_MASK 0x3u -#define CMP_CR0_HYSTCTR_SHIFT 0 -#define CMP_CR0_HYSTCTR_WIDTH 2 -#define CMP_CR0_HYSTCTR(x) (((uint8_t)(((uint8_t)(x))<ACCESS16BIT.DATAL) -#define CRC_DATAH_REG(base) ((base)->ACCESS16BIT.DATAH) -#define CRC_DATA_REG(base) ((base)->DATA) -#define CRC_DATALL_REG(base) ((base)->ACCESS8BIT.DATALL) -#define CRC_DATALU_REG(base) ((base)->ACCESS8BIT.DATALU) -#define CRC_DATAHL_REG(base) ((base)->ACCESS8BIT.DATAHL) -#define CRC_DATAHU_REG(base) ((base)->ACCESS8BIT.DATAHU) -#define CRC_GPOLYL_REG(base) ((base)->GPOLY_ACCESS16BIT.GPOLYL) -#define CRC_GPOLYH_REG(base) ((base)->GPOLY_ACCESS16BIT.GPOLYH) -#define CRC_GPOLY_REG(base) ((base)->GPOLY) -#define CRC_GPOLYLL_REG(base) ((base)->GPOLY_ACCESS8BIT.GPOLYLL) -#define CRC_GPOLYLU_REG(base) ((base)->GPOLY_ACCESS8BIT.GPOLYLU) -#define CRC_GPOLYHL_REG(base) ((base)->GPOLY_ACCESS8BIT.GPOLYHL) -#define CRC_GPOLYHU_REG(base) ((base)->GPOLY_ACCESS8BIT.GPOLYHU) -#define CRC_CTRL_REG(base) ((base)->CTRL) -#define CRC_CTRLHU_REG(base) ((base)->CTRL_ACCESS8BIT.CTRLHU) - -/*! - * @} - */ /* end of group CRC_Register_Accessor_Macros */ - +} CRC_Type; /* ---------------------------------------------------------------------------- -- CRC Register Masks @@ -1005,134 +852,122 @@ typedef struct { * @{ */ -/* DATAL Bit Fields */ -#define CRC_DATAL_DATAL_MASK 0xFFFFu -#define CRC_DATAL_DATAL_SHIFT 0 -#define CRC_DATAL_DATAL_WIDTH 16 -#define CRC_DATAL_DATAL(x) (((uint16_t)(((uint16_t)(x))<DAT[index].DATL) -#define DAC_DATL_COUNT 16 -#define DAC_DATH_REG(base,index) ((base)->DAT[index].DATH) -#define DAC_DATH_COUNT 16 -#define DAC_SR_REG(base) ((base)->SR) -#define DAC_C0_REG(base) ((base)->C0) -#define DAC_C1_REG(base) ((base)->C1) -#define DAC_C2_REG(base) ((base)->C2) - -/*! - * @} - */ /* end of group DAC_Register_Accessor_Macros */ - +} DAC_Type; /* ---------------------------------------------------------------------------- -- DAC Register Masks @@ -1244,88 +1019,81 @@ typedef struct { * @{ */ -/* DATL Bit Fields */ -#define DAC_DATL_DATA0_MASK 0xFFu -#define DAC_DATL_DATA0_SHIFT 0 -#define DAC_DATL_DATA0_WIDTH 8 -#define DAC_DATL_DATA0(x) (((uint8_t)(((uint8_t)(x))<CR) -#define DMA_ES_REG(base) ((base)->ES) -#define DMA_ERQ_REG(base) ((base)->ERQ) -#define DMA_EEI_REG(base) ((base)->EEI) -#define DMA_CEEI_REG(base) ((base)->CEEI) -#define DMA_SEEI_REG(base) ((base)->SEEI) -#define DMA_CERQ_REG(base) ((base)->CERQ) -#define DMA_SERQ_REG(base) ((base)->SERQ) -#define DMA_CDNE_REG(base) ((base)->CDNE) -#define DMA_SSRT_REG(base) ((base)->SSRT) -#define DMA_CERR_REG(base) ((base)->CERR) -#define DMA_CINT_REG(base) ((base)->CINT) -#define DMA_INT_REG(base) ((base)->INT) -#define DMA_ERR_REG(base) ((base)->ERR) -#define DMA_HRS_REG(base) ((base)->HRS) -#define DMA_EARS_REG(base) ((base)->EARS) -#define DMA_DCHPRI3_REG(base) ((base)->DCHPRI3) -#define DMA_DCHPRI2_REG(base) ((base)->DCHPRI2) -#define DMA_DCHPRI1_REG(base) ((base)->DCHPRI1) -#define DMA_DCHPRI0_REG(base) ((base)->DCHPRI0) -#define DMA_SADDR_REG(base,index) ((base)->TCD[index].SADDR) -#define DMA_SADDR_COUNT 4 -#define DMA_SOFF_REG(base,index) ((base)->TCD[index].SOFF) -#define DMA_SOFF_COUNT 4 -#define DMA_ATTR_REG(base,index) ((base)->TCD[index].ATTR) -#define DMA_ATTR_COUNT 4 -#define DMA_NBYTES_MLNO_REG(base,index) ((base)->TCD[index].NBYTES_MLNO) -#define DMA_NBYTES_MLNO_COUNT 4 -#define DMA_NBYTES_MLOFFNO_REG(base,index) ((base)->TCD[index].NBYTES_MLOFFNO) -#define DMA_NBYTES_MLOFFNO_COUNT 4 -#define DMA_NBYTES_MLOFFYES_REG(base,index) ((base)->TCD[index].NBYTES_MLOFFYES) -#define DMA_NBYTES_MLOFFYES_COUNT 4 -#define DMA_SLAST_REG(base,index) ((base)->TCD[index].SLAST) -#define DMA_SLAST_COUNT 4 -#define DMA_DADDR_REG(base,index) ((base)->TCD[index].DADDR) -#define DMA_DADDR_COUNT 4 -#define DMA_DOFF_REG(base,index) ((base)->TCD[index].DOFF) -#define DMA_DOFF_COUNT 4 -#define DMA_CITER_ELINKNO_REG(base,index) ((base)->TCD[index].CITER_ELINKNO) -#define DMA_CITER_ELINKNO_COUNT 4 -#define DMA_CITER_ELINKYES_REG(base,index) ((base)->TCD[index].CITER_ELINKYES) -#define DMA_CITER_ELINKYES_COUNT 4 -#define DMA_DLAST_SGA_REG(base,index) ((base)->TCD[index].DLAST_SGA) -#define DMA_DLAST_SGA_COUNT 4 -#define DMA_CSR_REG(base,index) ((base)->TCD[index].CSR) -#define DMA_CSR_COUNT 4 -#define DMA_BITER_ELINKNO_REG(base,index) ((base)->TCD[index].BITER_ELINKNO) -#define DMA_BITER_ELINKNO_COUNT 4 -#define DMA_BITER_ELINKYES_REG(base,index) ((base)->TCD[index].BITER_ELINKYES) -#define DMA_BITER_ELINKYES_COUNT 4 - -/*! - * @} - */ /* end of group DMA_Register_Accessor_Macros */ - +} DMA_Type; /* ---------------------------------------------------------------------------- -- DMA Register Masks @@ -1548,517 +1190,478 @@ typedef struct { * @{ */ -/* CR Bit Fields */ -#define DMA_CR_EDBG_MASK 0x2u -#define DMA_CR_EDBG_SHIFT 1 -#define DMA_CR_EDBG_WIDTH 1 -#define DMA_CR_EDBG(x) (((uint32_t)(((uint32_t)(x))<CHCFG[index]) -#define DMAMUX_CHCFG_COUNT 4 - -/*! - * @} - */ /* end of group DMAMUX_Register_Accessor_Macros */ - +} DMAMUX_Type; /* ---------------------------------------------------------------------------- -- DMAMUX Register Masks @@ -2241,19 +1709,20 @@ typedef struct { * @{ */ -/* CHCFG Bit Fields */ -#define DMAMUX_CHCFG_SOURCE_MASK 0x3Fu -#define DMAMUX_CHCFG_SOURCE_SHIFT 0 -#define DMAMUX_CHCFG_SOURCE_WIDTH 6 -#define DMAMUX_CHCFG_SOURCE(x) (((uint8_t)(((uint8_t)(x))<CTRL) -#define EWM_SERV_REG(base) ((base)->SERV) -#define EWM_CMPL_REG(base) ((base)->CMPL) -#define EWM_CMPH_REG(base) ((base)->CMPH) -#define EWM_CLKPRESCALER_REG(base) ((base)->CLKPRESCALER) - -/*! - * @} - */ /* end of group EWM_Register_Accessor_Macros */ - +} EWM_Type; /* ---------------------------------------------------------------------------- -- EWM Register Masks @@ -2351,43 +1772,40 @@ typedef struct { * @{ */ -/* CTRL Bit Fields */ -#define EWM_CTRL_EWMEN_MASK 0x1u -#define EWM_CTRL_EWMEN_SHIFT 0 -#define EWM_CTRL_EWMEN_WIDTH 1 -#define EWM_CTRL_EWMEN(x) (((uint8_t)(((uint8_t)(x))<PFAPR) -#define FMC_PFB0CR_REG(base) ((base)->PFB0CR) -#define FMC_PFB1CR_REG(base) ((base)->PFB1CR) -#define FMC_TAGVDW0S_REG(base,index) ((base)->TAGVDW0S[index]) -#define FMC_TAGVDW0S_COUNT 8 -#define FMC_TAGVDW1S_REG(base,index) ((base)->TAGVDW1S[index]) -#define FMC_TAGVDW1S_COUNT 8 -#define FMC_TAGVDW2S_REG(base,index) ((base)->TAGVDW2S[index]) -#define FMC_TAGVDW2S_COUNT 8 -#define FMC_TAGVDW3S_REG(base,index) ((base)->TAGVDW3S[index]) -#define FMC_TAGVDW3S_COUNT 8 -#define FMC_DATA_U_REG(base,index,index2) ((base)->SET[index][index2].DATA_U) -#define FMC_DATA_U_COUNT 4 -#define FMC_DATA_U_COUNT2 8 -#define FMC_DATA_L_REG(base,index,index2) ((base)->SET[index][index2].DATA_L) -#define FMC_DATA_L_COUNT 4 -#define FMC_DATA_L_COUNT2 8 - -/*! - * @} - */ /* end of group FMC_Register_Accessor_Macros */ - +} FMC_Type; /* ---------------------------------------------------------------------------- -- FMC Register Masks @@ -2504,191 +1864,180 @@ typedef struct { * @{ */ -/* PFAPR Bit Fields */ -#define FMC_PFAPR_M0AP_MASK 0x3u -#define FMC_PFAPR_M0AP_SHIFT 0 -#define FMC_PFAPR_M0AP_WIDTH 2 -#define FMC_PFAPR_M0AP(x) (((uint32_t)(((uint32_t)(x))<FSTAT) -#define FTFA_FCNFG_REG(base) ((base)->FCNFG) -#define FTFA_FSEC_REG(base) ((base)->FSEC) -#define FTFA_FOPT_REG(base) ((base)->FOPT) -#define FTFA_FCCOB3_REG(base) ((base)->FCCOB3) -#define FTFA_FCCOB2_REG(base) ((base)->FCCOB2) -#define FTFA_FCCOB1_REG(base) ((base)->FCCOB1) -#define FTFA_FCCOB0_REG(base) ((base)->FCCOB0) -#define FTFA_FCCOB7_REG(base) ((base)->FCCOB7) -#define FTFA_FCCOB6_REG(base) ((base)->FCCOB6) -#define FTFA_FCCOB5_REG(base) ((base)->FCCOB5) -#define FTFA_FCCOB4_REG(base) ((base)->FCCOB4) -#define FTFA_FCCOBB_REG(base) ((base)->FCCOBB) -#define FTFA_FCCOBA_REG(base) ((base)->FCCOBA) -#define FTFA_FCCOB9_REG(base) ((base)->FCCOB9) -#define FTFA_FCCOB8_REG(base) ((base)->FCCOB8) -#define FTFA_FPROT3_REG(base) ((base)->FPROT3) -#define FTFA_FPROT2_REG(base) ((base)->FPROT2) -#define FTFA_FPROT1_REG(base) ((base)->FPROT1) -#define FTFA_FPROT0_REG(base) ((base)->FPROT0) -#define FTFA_XACCH3_REG(base) ((base)->XACCH3) -#define FTFA_XACCH2_REG(base) ((base)->XACCH2) -#define FTFA_XACCH1_REG(base) ((base)->XACCH1) -#define FTFA_XACCH0_REG(base) ((base)->XACCH0) -#define FTFA_XACCL3_REG(base) ((base)->XACCL3) -#define FTFA_XACCL2_REG(base) ((base)->XACCL2) -#define FTFA_XACCL1_REG(base) ((base)->XACCL1) -#define FTFA_XACCL0_REG(base) ((base)->XACCL0) -#define FTFA_SACCH3_REG(base) ((base)->SACCH3) -#define FTFA_SACCH2_REG(base) ((base)->SACCH2) -#define FTFA_SACCH1_REG(base) ((base)->SACCH1) -#define FTFA_SACCH0_REG(base) ((base)->SACCH0) -#define FTFA_SACCL3_REG(base) ((base)->SACCL3) -#define FTFA_SACCL2_REG(base) ((base)->SACCL2) -#define FTFA_SACCL1_REG(base) ((base)->SACCL1) -#define FTFA_SACCL0_REG(base) ((base)->SACCL0) -#define FTFA_FACSS_REG(base) ((base)->FACSS) -#define FTFA_FACSN_REG(base) ((base)->FACSN) - -/*! - * @} - */ /* end of group FTFA_Register_Accessor_Macros */ - +} FTFA_Type; /* ---------------------------------------------------------------------------- -- FTFA Register Masks @@ -2953,236 +2121,226 @@ typedef struct { * @{ */ -/* FSTAT Bit Fields */ -#define FTFA_FSTAT_MGSTAT0_MASK 0x1u -#define FTFA_FSTAT_MGSTAT0_SHIFT 0 -#define FTFA_FSTAT_MGSTAT0_WIDTH 1 -#define FTFA_FSTAT_MGSTAT0(x) (((uint8_t)(((uint8_t)(x))<SC) -#define FTM_CNT_REG(base) ((base)->CNT) -#define FTM_MOD_REG(base) ((base)->MOD) -#define FTM_CnSC_REG(base,index) ((base)->CONTROLS[index].CnSC) -#define FTM_CnSC_COUNT 8 -#define FTM_CnV_REG(base,index) ((base)->CONTROLS[index].CnV) -#define FTM_CnV_COUNT 8 -#define FTM_CNTIN_REG(base) ((base)->CNTIN) -#define FTM_STATUS_REG(base) ((base)->STATUS) -#define FTM_MODE_REG(base) ((base)->MODE) -#define FTM_SYNC_REG(base) ((base)->SYNC) -#define FTM_OUTINIT_REG(base) ((base)->OUTINIT) -#define FTM_OUTMASK_REG(base) ((base)->OUTMASK) -#define FTM_COMBINE_REG(base) ((base)->COMBINE) -#define FTM_DEADTIME_REG(base) ((base)->DEADTIME) -#define FTM_EXTTRIG_REG(base) ((base)->EXTTRIG) -#define FTM_POL_REG(base) ((base)->POL) -#define FTM_FMS_REG(base) ((base)->FMS) -#define FTM_FILTER_REG(base) ((base)->FILTER) -#define FTM_FLTCTRL_REG(base) ((base)->FLTCTRL) -#define FTM_QDCTRL_REG(base) ((base)->QDCTRL) -#define FTM_CONF_REG(base) ((base)->CONF) -#define FTM_FLTPOL_REG(base) ((base)->FLTPOL) -#define FTM_SYNCONF_REG(base) ((base)->SYNCONF) -#define FTM_INVCTRL_REG(base) ((base)->INVCTRL) -#define FTM_SWOCTRL_REG(base) ((base)->SWOCTRL) -#define FTM_PWMLOAD_REG(base) ((base)->PWMLOAD) - -/*! - * @} - */ /* end of group FTM_Register_Accessor_Macros */ - +} FTM_Type; /* ---------------------------------------------------------------------------- -- FTM Register Masks @@ -3357,759 +2414,608 @@ typedef struct { * @{ */ -/* SC Bit Fields */ -#define FTM_SC_PS_MASK 0x7u -#define FTM_SC_PS_SHIFT 0 -#define FTM_SC_PS_WIDTH 3 -#define FTM_SC_PS(x) (((uint32_t)(((uint32_t)(x))<PDOR) -#define GPIO_PSOR_REG(base) ((base)->PSOR) -#define GPIO_PCOR_REG(base) ((base)->PCOR) -#define GPIO_PTOR_REG(base) ((base)->PTOR) -#define GPIO_PDIR_REG(base) ((base)->PDIR) -#define GPIO_PDDR_REG(base) ((base)->PDDR) - -/*! - * @} - */ /* end of group GPIO_Register_Accessor_Macros */ - +} GPIO_Type; /* ---------------------------------------------------------------------------- -- GPIO Register Masks @@ -4316,36 +3075,36 @@ typedef struct { * @{ */ -/* PDOR Bit Fields */ -#define GPIO_PDOR_PDO_MASK 0xFFFFFFFFu -#define GPIO_PDOR_PDO_SHIFT 0 -#define GPIO_PDOR_PDO_WIDTH 32 -#define GPIO_PDOR_PDO(x) (((uint32_t)(((uint32_t)(x))<A1) -#define I2C_F_REG(base) ((base)->F) -#define I2C_C1_REG(base) ((base)->C1) -#define I2C_S_REG(base) ((base)->S) -#define I2C_D_REG(base) ((base)->D) -#define I2C_C2_REG(base) ((base)->C2) -#define I2C_FLT_REG(base) ((base)->FLT) -#define I2C_RA_REG(base) ((base)->RA) -#define I2C_SMB_REG(base) ((base)->SMB) -#define I2C_A2_REG(base) ((base)->A2) -#define I2C_SLTH_REG(base) ((base)->SLTH) -#define I2C_SLTL_REG(base) ((base)->SLTL) - -/*! - * @} - */ /* end of group I2C_Register_Accessor_Macros */ - +} I2C_Type; /* ---------------------------------------------------------------------------- -- I2C Register Masks @@ -4503,190 +3176,159 @@ typedef struct { * @{ */ -/* A1 Bit Fields */ -#define I2C_A1_AD_MASK 0xFEu -#define I2C_A1_AD_SHIFT 1 -#define I2C_A1_AD_WIDTH 7 -#define I2C_A1_AD(x) (((uint8_t)(((uint8_t)(x))<TCSR) -#define I2S_TCR1_REG(base) ((base)->TCR1) -#define I2S_TCR2_REG(base) ((base)->TCR2) -#define I2S_TCR3_REG(base) ((base)->TCR3) -#define I2S_TCR4_REG(base) ((base)->TCR4) -#define I2S_TCR5_REG(base) ((base)->TCR5) -#define I2S_TDR_REG(base,index) ((base)->TDR[index]) -#define I2S_TDR_COUNT 1 -#define I2S_TFR_REG(base,index) ((base)->TFR[index]) -#define I2S_TFR_COUNT 1 -#define I2S_TMR_REG(base) ((base)->TMR) -#define I2S_RCSR_REG(base) ((base)->RCSR) -#define I2S_RCR1_REG(base) ((base)->RCR1) -#define I2S_RCR2_REG(base) ((base)->RCR2) -#define I2S_RCR3_REG(base) ((base)->RCR3) -#define I2S_RCR4_REG(base) ((base)->RCR4) -#define I2S_RCR5_REG(base) ((base)->RCR5) -#define I2S_RDR_REG(base,index) ((base)->RDR[index]) -#define I2S_RDR_COUNT 1 -#define I2S_RFR_REG(base,index) ((base)->RFR[index]) -#define I2S_RFR_COUNT 1 -#define I2S_RMR_REG(base) ((base)->RMR) -#define I2S_MCR_REG(base) ((base)->MCR) -#define I2S_MDR_REG(base) ((base)->MDR) - -/*! - * @} - */ /* end of group I2S_Register_Accessor_Macros */ - +} I2S_Type; /* ---------------------------------------------------------------------------- -- I2S Register Masks @@ -4850,398 +3406,337 @@ typedef struct { * @{ */ -/* TCSR Bit Fields */ -#define I2S_TCSR_FRDE_MASK 0x1u -#define I2S_TCSR_FRDE_SHIFT 0 -#define I2S_TCSR_FRDE_WIDTH 1 -#define I2S_TCSR_FRDE(x) (((uint32_t)(((uint32_t)(x))<PE1) -#define LLWU_PE2_REG(base) ((base)->PE2) -#define LLWU_PE3_REG(base) ((base)->PE3) -#define LLWU_PE4_REG(base) ((base)->PE4) -#define LLWU_ME_REG(base) ((base)->ME) -#define LLWU_F1_REG(base) ((base)->F1) -#define LLWU_F2_REG(base) ((base)->F2) -#define LLWU_F3_REG(base) ((base)->F3) -#define LLWU_FILT1_REG(base) ((base)->FILT1) -#define LLWU_FILT2_REG(base) ((base)->FILT2) - -/*! - * @} - */ /* end of group LLWU_Register_Accessor_Macros */ - +} LLWU_Type; /* ---------------------------------------------------------------------------- -- LLWU Register Masks @@ -5370,232 +3793,188 @@ typedef struct { * @{ */ -/* PE1 Bit Fields */ -#define LLWU_PE1_WUPE0_MASK 0x3u -#define LLWU_PE1_WUPE0_SHIFT 0 -#define LLWU_PE1_WUPE0_WIDTH 2 -#define LLWU_PE1_WUPE0(x) (((uint8_t)(((uint8_t)(x))<CSR) -#define LPTMR_PSR_REG(base) ((base)->PSR) -#define LPTMR_CMR_REG(base) ((base)->CMR) -#define LPTMR_CNR_REG(base) ((base)->CNR) - -/*! - * @} - */ /* end of group LPTMR_Register_Accessor_Macros */ - +} LPTMR_Type; /* ---------------------------------------------------------------------------- -- LPTMR Register Masks @@ -5695,58 +4024,50 @@ typedef struct { * @{ */ -/* CSR Bit Fields */ -#define LPTMR_CSR_TEN_MASK 0x1u -#define LPTMR_CSR_TEN_SHIFT 0 -#define LPTMR_CSR_TEN_WIDTH 1 -#define LPTMR_CSR_TEN(x) (((uint32_t)(((uint32_t)(x))<BAUD) -#define LPUART_STAT_REG(base) ((base)->STAT) -#define LPUART_CTRL_REG(base) ((base)->CTRL) -#define LPUART_DATA_REG(base) ((base)->DATA) -#define LPUART_MATCH_REG(base) ((base)->MATCH) -#define LPUART_MODIR_REG(base) ((base)->MODIR) - -/*! - * @} - */ /* end of group LPUART_Register_Accessor_Macros */ - +} LPUART_Type; /* ---------------------------------------------------------------------------- -- LPUART Register Masks @@ -5844,344 +4119,267 @@ typedef struct { * @{ */ -/* BAUD Bit Fields */ -#define LPUART_BAUD_SBR_MASK 0x1FFFu -#define LPUART_BAUD_SBR_SHIFT 0 -#define LPUART_BAUD_SBR_WIDTH 13 -#define LPUART_BAUD_SBR(x) (((uint32_t)(((uint32_t)(x))<C1) -#define MCG_C2_REG(base) ((base)->C2) -#define MCG_C3_REG(base) ((base)->C3) -#define MCG_C4_REG(base) ((base)->C4) -#define MCG_C5_REG(base) ((base)->C5) -#define MCG_C6_REG(base) ((base)->C6) -#define MCG_S_REG(base) ((base)->S) -#define MCG_SC_REG(base) ((base)->SC) -#define MCG_ATCVH_REG(base) ((base)->ATCVH) -#define MCG_ATCVL_REG(base) ((base)->ATCVL) -#define MCG_C7_REG(base) ((base)->C7) -#define MCG_C8_REG(base) ((base)->C8) - -/*! - * @} - */ /* end of group MCG_Register_Accessor_Macros */ - +} MCG_Type; /* ---------------------------------------------------------------------------- -- MCG Register Masks @@ -6296,153 +4440,130 @@ typedef struct { * @{ */ -/* C1 Bit Fields */ -#define MCG_C1_IREFSTEN_MASK 0x1u -#define MCG_C1_IREFSTEN_SHIFT 0 -#define MCG_C1_IREFSTEN_WIDTH 1 -#define MCG_C1_IREFSTEN(x) (((uint8_t)(((uint8_t)(x))<PLASC) -#define MCM_PLAMC_REG(base) ((base)->PLAMC) -#define MCM_PLACR_REG(base) ((base)->PLACR) -#define MCM_ISCR_REG(base) ((base)->ISCR) -#define MCM_CPO_REG(base) ((base)->CPO) - -/*! - * @} - */ /* end of group MCM_Register_Accessor_Macros */ - +} MCM_Type; /* ---------------------------------------------------------------------------- -- MCM Register Masks @@ -6546,83 +4614,70 @@ typedef struct { * @{ */ -/* PLASC Bit Fields */ -#define MCM_PLASC_ASC_MASK 0xFFu -#define MCM_PLASC_ASC_SHIFT 0 -#define MCM_PLASC_ASC_WIDTH 8 -#define MCM_PLASC_ASC(x) (((uint16_t)(((uint16_t)(x))<BACKKEY3) -#define NV_BACKKEY2_REG(base) ((base)->BACKKEY2) -#define NV_BACKKEY1_REG(base) ((base)->BACKKEY1) -#define NV_BACKKEY0_REG(base) ((base)->BACKKEY0) -#define NV_BACKKEY7_REG(base) ((base)->BACKKEY7) -#define NV_BACKKEY6_REG(base) ((base)->BACKKEY6) -#define NV_BACKKEY5_REG(base) ((base)->BACKKEY5) -#define NV_BACKKEY4_REG(base) ((base)->BACKKEY4) -#define NV_FPROT3_REG(base) ((base)->FPROT3) -#define NV_FPROT2_REG(base) ((base)->FPROT2) -#define NV_FPROT1_REG(base) ((base)->FPROT1) -#define NV_FPROT0_REG(base) ((base)->FPROT0) -#define NV_FSEC_REG(base) ((base)->FSEC) -#define NV_FOPT_REG(base) ((base)->FOPT) - -/*! - * @} - */ /* end of group NV_Register_Accessor_Macros */ - +} NV_Type; /* ---------------------------------------------------------------------------- -- NV Register Masks @@ -6737,100 +4737,94 @@ typedef struct { * @{ */ -/* BACKKEY3 Bit Fields */ -#define NV_BACKKEY3_KEY_MASK 0xFFu -#define NV_BACKKEY3_KEY_SHIFT 0 -#define NV_BACKKEY3_KEY_WIDTH 8 -#define NV_BACKKEY3_KEY(x) (((uint8_t)(((uint8_t)(x))<CR) -#define OSC_DIV_REG(base) ((base)->DIV) - -/*! - * @} - */ /* end of group OSC_Register_Accessor_Macros */ - +} OSC_Type; /* ---------------------------------------------------------------------------- -- OSC Register Masks @@ -6929,36 +4871,31 @@ typedef struct { * @{ */ -/* CR Bit Fields */ -#define OSC_CR_SC16P_MASK 0x1u -#define OSC_CR_SC16P_SHIFT 0 -#define OSC_CR_SC16P_WIDTH 1 -#define OSC_CR_SC16P(x) (((uint8_t)(((uint8_t)(x))<SC) -#define PDB_MOD_REG(base) ((base)->MOD) -#define PDB_CNT_REG(base) ((base)->CNT) -#define PDB_IDLY_REG(base) ((base)->IDLY) -#define PDB_C1_REG(base,index) ((base)->CH[index].C1) -#define PDB_C1_COUNT 2 -#define PDB_S_REG(base,index) ((base)->CH[index].S) -#define PDB_S_COUNT 2 -#define PDB_DLY_REG(base,index,index2) ((base)->CH[index].DLY[index2]) -#define PDB_DLY_COUNT 2 -#define PDB_DLY_COUNT2 2 -#define PDB_INTC_REG(base,index) ((base)->DAC[index].INTC) -#define PDB_INTC_COUNT 1 -#define PDB_INT_REG(base,index) ((base)->DAC[index].INT) -#define PDB_INT_COUNT 1 -#define PDB_POEN_REG(base) ((base)->POEN) -#define PDB_PODLY_REG(base,index) ((base)->PODLY[index]) -#define PDB_PODLY_COUNT 2 - -/*! - * @} - */ /* end of group PDB_Register_Accessor_Macros */ - +} PDB_Type; /* ---------------------------------------------------------------------------- -- PDB Register Masks @@ -7076,125 +4957,130 @@ typedef struct { * @{ */ -/* SC Bit Fields */ -#define PDB_SC_LDOK_MASK 0x1u -#define PDB_SC_LDOK_SHIFT 0 -#define PDB_SC_LDOK_WIDTH 1 -#define PDB_SC_LDOK(x) (((uint32_t)(((uint32_t)(x))<MCR) -#define PIT_LDVAL_REG(base,index) ((base)->CHANNEL[index].LDVAL) -#define PIT_LDVAL_COUNT 4 -#define PIT_CVAL_REG(base,index) ((base)->CHANNEL[index].CVAL) -#define PIT_CVAL_COUNT 4 -#define PIT_TCTRL_REG(base,index) ((base)->CHANNEL[index].TCTRL) -#define PIT_TCTRL_COUNT 4 -#define PIT_TFLG_REG(base,index) ((base)->CHANNEL[index].TFLG) -#define PIT_TFLG_COUNT 4 - -/*! - * @} - */ /* end of group PIT_Register_Accessor_Macros */ - +} PIT_Type; /* ---------------------------------------------------------------------------- -- PIT Register Masks @@ -7318,43 +5134,52 @@ typedef struct { * @{ */ -/* MCR Bit Fields */ -#define PIT_MCR_FRZ_MASK 0x1u -#define PIT_MCR_FRZ_SHIFT 0 -#define PIT_MCR_FRZ_WIDTH 1 -#define PIT_MCR_FRZ(x) (((uint32_t)(((uint32_t)(x))<LVDSC1) -#define PMC_LVDSC2_REG(base) ((base)->LVDSC2) -#define PMC_REGSC_REG(base) ((base)->REGSC) - -/*! - * @} - */ /* end of group PMC_Register_Accessor_Macros */ - +} PMC_Type; /* ---------------------------------------------------------------------------- -- PMC Register Masks @@ -7465,61 +5228,51 @@ typedef struct { * @{ */ -/* LVDSC1 Bit Fields */ -#define PMC_LVDSC1_LVDV_MASK 0x3u -#define PMC_LVDSC1_LVDV_SHIFT 0 -#define PMC_LVDSC1_LVDV_WIDTH 2 -#define PMC_LVDSC1_LVDV(x) (((uint8_t)(((uint8_t)(x))<PCR[index]) -#define PORT_PCR_COUNT 32 -#define PORT_GPCLR_REG(base) ((base)->GPCLR) -#define PORT_GPCHR_REG(base) ((base)->GPCHR) -#define PORT_ISFR_REG(base) ((base)->ISFR) -#define PORT_DFER_REG(base) ((base)->DFER) -#define PORT_DFCR_REG(base) ((base)->DFCR) -#define PORT_DFWR_REG(base) ((base)->DFWR) - -/*! - * @} - */ /* end of group PORT_Register_Accessor_Macros */ - +} PORT_Type; /* ---------------------------------------------------------------------------- -- PORT Register Masks @@ -7621,85 +5327,77 @@ typedef struct { * @{ */ -/* PCR Bit Fields */ -#define PORT_PCR_PS_MASK 0x1u -#define PORT_PCR_PS_SHIFT 0 -#define PORT_PCR_PS_WIDTH 1 -#define PORT_PCR_PS(x) (((uint32_t)(((uint32_t)(x))<SRS0) -#define RCM_SRS1_REG(base) ((base)->SRS1) -#define RCM_RPFC_REG(base) ((base)->RPFC) -#define RCM_RPFW_REG(base) ((base)->RPFW) -#define RCM_MR_REG(base) ((base)->MR) -#define RCM_SSRS0_REG(base) ((base)->SSRS0) -#define RCM_SSRS1_REG(base) ((base)->SSRS1) - -/*! - * @} - */ /* end of group RCM_Register_Accessor_Macros */ - +} RCM_Type; /* ---------------------------------------------------------------------------- -- RCM Register Masks @@ -8006,125 +5468,104 @@ typedef struct { * @{ */ -/* SRS0 Bit Fields */ -#define RCM_SRS0_WAKEUP_MASK 0x1u -#define RCM_SRS0_WAKEUP_SHIFT 0 -#define RCM_SRS0_WAKEUP_WIDTH 1 -#define RCM_SRS0_WAKEUP(x) (((uint8_t)(((uint8_t)(x))<REG[index]) -#define RFSYS_REG_COUNT 8 - -/*! - * @} - */ /* end of group RFSYS_Register_Accessor_Macros */ - +} RFSYS_Type; /* ---------------------------------------------------------------------------- -- RFSYS Register Masks @@ -8214,23 +5610,23 @@ typedef struct { * @{ */ -/* REG Bit Fields */ -#define RFSYS_REG_LL_MASK 0xFFu -#define RFSYS_REG_LL_SHIFT 0 -#define RFSYS_REG_LL_WIDTH 8 -#define RFSYS_REG_LL(x) (((uint32_t)(((uint32_t)(x))<REG[index]) -#define RFVBAT_REG_COUNT 8 - -/*! - * @} - */ /* end of group RFVBAT_Register_Accessor_Macros */ - +} RFVBAT_Type; /* ---------------------------------------------------------------------------- -- RFVBAT Register Masks @@ -8324,23 +5671,23 @@ typedef struct { * @{ */ -/* REG Bit Fields */ -#define RFVBAT_REG_LL_MASK 0xFFu -#define RFVBAT_REG_LL_SHIFT 0 -#define RFVBAT_REG_LL_WIDTH 8 -#define RFVBAT_REG_LL(x) (((uint32_t)(((uint32_t)(x))<TSR) -#define RTC_TPR_REG(base) ((base)->TPR) -#define RTC_TAR_REG(base) ((base)->TAR) -#define RTC_TCR_REG(base) ((base)->TCR) -#define RTC_CR_REG(base) ((base)->CR) -#define RTC_SR_REG(base) ((base)->SR) -#define RTC_LR_REG(base) ((base)->LR) -#define RTC_IER_REG(base) ((base)->IER) -#define RTC_WAR_REG(base) ((base)->WAR) -#define RTC_RAR_REG(base) ((base)->RAR) - -/*! - * @} - */ /* end of group RTC_Register_Accessor_Macros */ - +} RTC_Type; /* ---------------------------------------------------------------------------- -- RTC Register Masks @@ -8452,204 +5742,167 @@ typedef struct { * @{ */ -/* TSR Bit Fields */ -#define RTC_TSR_TSR_MASK 0xFFFFFFFFu -#define RTC_TSR_TSR_SHIFT 0 -#define RTC_TSR_TSR_WIDTH 32 -#define RTC_TSR_TSR(x) (((uint32_t)(((uint32_t)(x))<SOPT1) -#define SIM_SOPT1CFG_REG(base) ((base)->SOPT1CFG) -#define SIM_SOPT2_REG(base) ((base)->SOPT2) -#define SIM_SOPT4_REG(base) ((base)->SOPT4) -#define SIM_SOPT5_REG(base) ((base)->SOPT5) -#define SIM_SOPT7_REG(base) ((base)->SOPT7) -#define SIM_SOPT8_REG(base) ((base)->SOPT8) -#define SIM_SDID_REG(base) ((base)->SDID) -#define SIM_SCGC4_REG(base) ((base)->SCGC4) -#define SIM_SCGC5_REG(base) ((base)->SCGC5) -#define SIM_SCGC6_REG(base) ((base)->SCGC6) -#define SIM_SCGC7_REG(base) ((base)->SCGC7) -#define SIM_CLKDIV1_REG(base) ((base)->CLKDIV1) -#define SIM_CLKDIV2_REG(base) ((base)->CLKDIV2) -#define SIM_FCFG1_REG(base) ((base)->FCFG1) -#define SIM_FCFG2_REG(base) ((base)->FCFG2) -#define SIM_UIDH_REG(base) ((base)->UIDH) -#define SIM_UIDMH_REG(base) ((base)->UIDMH) -#define SIM_UIDML_REG(base) ((base)->UIDML) -#define SIM_UIDL_REG(base) ((base)->UIDL) - -/*! - * @} - */ /* end of group SIM_Register_Accessor_Macros */ - +} SIM_Type; /* ---------------------------------------------------------------------------- -- SIM Register Masks @@ -8787,409 +5974,332 @@ typedef struct { * @{ */ -/* SOPT1 Bit Fields */ -#define SIM_SOPT1_RAMSIZE_MASK 0xF000u -#define SIM_SOPT1_RAMSIZE_SHIFT 12 -#define SIM_SOPT1_RAMSIZE_WIDTH 4 -#define SIM_SOPT1_RAMSIZE(x) (((uint32_t)(((uint32_t)(x))<PMPROT) -#define SMC_PMCTRL_REG(base) ((base)->PMCTRL) -#define SMC_STOPCTRL_REG(base) ((base)->STOPCTRL) -#define SMC_PMSTAT_REG(base) ((base)->PMSTAT) - -/*! - * @} - */ /* end of group SMC_Register_Accessor_Macros */ - +} SMC_Type; /* ---------------------------------------------------------------------------- -- SMC Register Masks @@ -9297,54 +6347,47 @@ typedef struct { * @{ */ -/* PMPROT Bit Fields */ -#define SMC_PMPROT_AVLLS_MASK 0x2u -#define SMC_PMPROT_AVLLS_SHIFT 1 -#define SMC_PMPROT_AVLLS_WIDTH 1 -#define SMC_PMPROT_AVLLS(x) (((uint8_t)(((uint8_t)(x))<MCR) -#define SPI_TCR_REG(base) ((base)->TCR) -#define SPI_CTAR_REG(base,index2) ((base)->CTAR[index2]) -#define SPI_CTAR_COUNT 2 -#define SPI_CTAR_SLAVE_REG(base,index2) ((base)->CTAR_SLAVE[index2]) -#define SPI_CTAR_SLAVE_COUNT 1 -#define SPI_SR_REG(base) ((base)->SR) -#define SPI_RSER_REG(base) ((base)->RSER) -#define SPI_PUSHR_REG(base) ((base)->PUSHR) -#define SPI_PUSHR_SLAVE_REG(base) ((base)->PUSHR_SLAVE) -#define SPI_POPR_REG(base) ((base)->POPR) -#define SPI_TXFR0_REG(base) ((base)->TXFR0) -#define SPI_TXFR1_REG(base) ((base)->TXFR1) -#define SPI_TXFR2_REG(base) ((base)->TXFR2) -#define SPI_TXFR3_REG(base) ((base)->TXFR3) -#define SPI_RXFR0_REG(base) ((base)->RXFR0) -#define SPI_RXFR1_REG(base) ((base)->RXFR1) -#define SPI_RXFR2_REG(base) ((base)->RXFR2) -#define SPI_RXFR3_REG(base) ((base)->RXFR3) - -/*! - * @} - */ /* end of group SPI_Register_Accessor_Macros */ - +} SPI_Type; /* ---------------------------------------------------------------------------- -- SPI Register Masks @@ -9471,311 +6455,262 @@ typedef struct { * @{ */ -/* MCR Bit Fields */ -#define SPI_MCR_HALT_MASK 0x1u -#define SPI_MCR_HALT_SHIFT 0 -#define SPI_MCR_HALT_WIDTH 1 -#define SPI_MCR_HALT(x) (((uint32_t)(((uint32_t)(x))<BDH) -#define UART_BDL_REG(base) ((base)->BDL) -#define UART_C1_REG(base) ((base)->C1) -#define UART_C2_REG(base) ((base)->C2) -#define UART_S1_REG(base) ((base)->S1) -#define UART_S2_REG(base) ((base)->S2) -#define UART_C3_REG(base) ((base)->C3) -#define UART_D_REG(base) ((base)->D) -#define UART_MA1_REG(base) ((base)->MA1) -#define UART_MA2_REG(base) ((base)->MA2) -#define UART_C4_REG(base) ((base)->C4) -#define UART_C5_REG(base) ((base)->C5) -#define UART_ED_REG(base) ((base)->ED) -#define UART_MODEM_REG(base) ((base)->MODEM) -#define UART_IR_REG(base) ((base)->IR) -#define UART_PFIFO_REG(base) ((base)->PFIFO) -#define UART_CFIFO_REG(base) ((base)->CFIFO) -#define UART_SFIFO_REG(base) ((base)->SFIFO) -#define UART_TWFIFO_REG(base) ((base)->TWFIFO) -#define UART_TCFIFO_REG(base) ((base)->TCFIFO) -#define UART_RWFIFO_REG(base) ((base)->RWFIFO) -#define UART_RCFIFO_REG(base) ((base)->RCFIFO) -#define UART_C7816_REG(base) ((base)->C7816) -#define UART_IE7816_REG(base) ((base)->IE7816) -#define UART_IS7816_REG(base) ((base)->IS7816) -#define UART_WP7816_REG(base) ((base)->WP7816) -#define UART_WN7816_REG(base) ((base)->WN7816) -#define UART_WF7816_REG(base) ((base)->WF7816) -#define UART_ET7816_REG(base) ((base)->ET7816) -#define UART_TL7816_REG(base) ((base)->TL7816) -#define UART_AP7816A_T0_REG(base) ((base)->AP7816A_T0) -#define UART_AP7816B_T0_REG(base) ((base)->AP7816B_T0) -#define UART_WP7816A_T0_REG(base) ((base)->TYPE0.WP7816A_T0) -#define UART_WP7816B_T0_REG(base) ((base)->TYPE0.WP7816B_T0) -#define UART_WP7816A_T1_REG(base) ((base)->TYPE1.WP7816A_T1) -#define UART_WP7816B_T1_REG(base) ((base)->TYPE1.WP7816B_T1) -#define UART_WGP7816_T1_REG(base) ((base)->WGP7816_T1) -#define UART_WP7816C_T1_REG(base) ((base)->WP7816C_T1) - -/*! - * @} - */ /* end of group UART_Register_Accessor_Macros */ - +} UART_Type; /* ---------------------------------------------------------------------------- -- UART Register Masks @@ -9990,504 +6807,427 @@ typedef struct { * @{ */ -/* BDH Bit Fields */ -#define UART_BDH_SBR_MASK 0x1Fu -#define UART_BDH_SBR_SHIFT 0 -#define UART_BDH_SBR_WIDTH 5 -#define UART_BDH_SBR(x) (((uint8_t)(((uint8_t)(x))<PERID) -#define USB_IDCOMP_REG(base) ((base)->IDCOMP) -#define USB_REV_REG(base) ((base)->REV) -#define USB_ADDINFO_REG(base) ((base)->ADDINFO) -#define USB_OTGISTAT_REG(base) ((base)->OTGISTAT) -#define USB_OTGICR_REG(base) ((base)->OTGICR) -#define USB_OTGSTAT_REG(base) ((base)->OTGSTAT) -#define USB_OTGCTL_REG(base) ((base)->OTGCTL) -#define USB_ISTAT_REG(base) ((base)->ISTAT) -#define USB_INTEN_REG(base) ((base)->INTEN) -#define USB_ERRSTAT_REG(base) ((base)->ERRSTAT) -#define USB_ERREN_REG(base) ((base)->ERREN) -#define USB_STAT_REG(base) ((base)->STAT) -#define USB_CTL_REG(base) ((base)->CTL) -#define USB_ADDR_REG(base) ((base)->ADDR) -#define USB_BDTPAGE1_REG(base) ((base)->BDTPAGE1) -#define USB_FRMNUML_REG(base) ((base)->FRMNUML) -#define USB_FRMNUMH_REG(base) ((base)->FRMNUMH) -#define USB_TOKEN_REG(base) ((base)->TOKEN) -#define USB_SOFTHLD_REG(base) ((base)->SOFTHLD) -#define USB_BDTPAGE2_REG(base) ((base)->BDTPAGE2) -#define USB_BDTPAGE3_REG(base) ((base)->BDTPAGE3) -#define USB_ENDPT_REG(base,index) ((base)->ENDPOINT[index].ENDPT) -#define USB_ENDPT_COUNT 16 -#define USB_USBCTRL_REG(base) ((base)->USBCTRL) -#define USB_OBSERVE_REG(base) ((base)->OBSERVE) -#define USB_CONTROL_REG(base) ((base)->CONTROL) -#define USB_USBTRC0_REG(base) ((base)->USBTRC0) -#define USB_USBFRMADJUST_REG(base) ((base)->USBFRMADJUST) -#define USB_CLK_RECOVER_CTRL_REG(base) ((base)->CLK_RECOVER_CTRL) -#define USB_CLK_RECOVER_IRC_EN_REG(base) ((base)->CLK_RECOVER_IRC_EN) -#define USB_CLK_RECOVER_INT_EN_REG(base) ((base)->CLK_RECOVER_INT_EN) -#define USB_CLK_RECOVER_INT_STATUS_REG(base) ((base)->CLK_RECOVER_INT_STATUS) - -/*! - * @} - */ /* end of group USB_Register_Accessor_Macros */ - +} USB_Type; /* ---------------------------------------------------------------------------- -- USB Register Masks @@ -10762,450 +7347,382 @@ typedef struct { * @{ */ -/* PERID Bit Fields */ -#define USB_PERID_ID_MASK 0x3Fu -#define USB_PERID_ID_SHIFT 0 -#define USB_PERID_ID_WIDTH 6 -#define USB_PERID_ID(x) (((uint8_t)(((uint8_t)(x))<TRM) -#define VREF_SC_REG(base) ((base)->SC) - -/*! - * @} - */ /* end of group VREF_Register_Accessor_Macros */ - +} VREF_Type; /* ---------------------------------------------------------------------------- -- VREF Register Masks @@ -11341,36 +7770,31 @@ typedef struct { * @{ */ -/* TRM Bit Fields */ -#define VREF_TRM_TRIM_MASK 0x3Fu -#define VREF_TRM_TRIM_SHIFT 0 -#define VREF_TRM_TRIM_WIDTH 6 -#define VREF_TRM_TRIM(x) (((uint8_t)(((uint8_t)(x))<STCTRLH) -#define WDOG_STCTRLL_REG(base) ((base)->STCTRLL) -#define WDOG_TOVALH_REG(base) ((base)->TOVALH) -#define WDOG_TOVALL_REG(base) ((base)->TOVALL) -#define WDOG_WINH_REG(base) ((base)->WINH) -#define WDOG_WINL_REG(base) ((base)->WINL) -#define WDOG_REFRESH_REG(base) ((base)->REFRESH) -#define WDOG_UNLOCK_REG(base) ((base)->UNLOCK) -#define WDOG_TMROUTH_REG(base) ((base)->TMROUTH) -#define WDOG_TMROUTL_REG(base) ((base)->TMROUTL) -#define WDOG_RSTCNT_REG(base) ((base)->RSTCNT) -#define WDOG_PRESC_REG(base) ((base)->PRESC) - -/*! - * @} - */ /* end of group WDOG_Register_Accessor_Macros */ - +} WDOG_Type; /* ---------------------------------------------------------------------------- -- WDOG Register Masks @@ -11476,110 +7850,99 @@ typedef struct { * @{ */ -/* STCTRLH Bit Fields */ -#define WDOG_STCTRLH_WDOGEN_MASK 0x1u -#define WDOG_STCTRLH_WDOGEN_SHIFT 0 -#define WDOG_STCTRLH_WDOGEN_WIDTH 1 -#define WDOG_STCTRLH_WDOGEN(x) (((uint16_t)(((uint16_t)(x))<= 6010050) + #pragma clang system_header + #endif +#elif defined(__IAR_SYSTEMS_ICC__) + #pragma system_include +#endif + +/** + * @brief Mask and left-shift a bit field value for use in a register bit range. + * @param field Name of the register bit field. + * @param value Value of the bit field. + * @return Masked and shifted value. + */ +#define NXP_VAL2FLD(field, value) (((value) << (field ## _SHIFT)) & (field ## _MASK)) +/** + * @brief Mask and right-shift a register value to extract a bit field value. + * @param field Name of the register bit field. + * @param value Value of the register. + * @return Masked and shifted bit field value. + */ +#define NXP_FLD2VAL(field, value) (((value) & (field ## _MASK)) >> (field ## _SHIFT)) + +/*! + * @} + */ /* end of group Bit_Field_Generic_Macros */ + + +/* ---------------------------------------------------------------------------- + -- SDK Compatibility + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup SDK_Compatibility_Symbols SDK Compatibility * @{ */ -#define ADC_BASES ADC_BASE_PTRS -#define CMP_BASES CMP_BASE_PTRS -#define CRC_BASES CRC_BASE_PTRS -#define DAC_BASES DAC_BASE_PTRS -#define DMA_BASES DMA_BASE_PTRS -#define DMAMUX_BASES DMAMUX_BASE_PTRS -#define EWM_BASES EWM_BASE_PTRS -#define FMC_BASES FMC_BASE_PTRS -#define FTFA_BASES FTFA_BASE_PTRS -#define FTM_BASES FTM_BASE_PTRS -#define GPIO_BASES GPIO_BASE_PTRS -#define I2C_BASES I2C_BASE_PTRS #define I2C0_S1 I2C0_S #define I2C1_S1 I2C1_S -#define I2S_BASES I2S_BASE_PTRS -#define LLWU_BASES LLWU_BASE_PTRS -#define LPTMR_BASES LPTMR_BASE_PTRS -#define LPUART_BASES LPUART_BASE_PTRS -#define MCG_BASES MCG_BASE_PTRS #define MCM_ISR_REG(base) MCM_ISCR_REG(base) #define MCM_ISR_FIOC_MASK MCM_ISCR_FIOC_MASK #define MCM_ISR_FIOC_SHIFT MCM_ISCR_FIOC_SHIFT @@ -11708,28 +8060,23 @@ typedef struct { #define MCM_ISR_FIXCE_SHIFT MCM_ISCR_FIXCE_SHIFT #define MCM_ISR_FIDCE_MASK MCM_ISCR_FIDCE_MASK #define MCM_ISR_FIDCE_SHIFT MCM_ISCR_FIDCE_SHIFT -#define MCM_BASES MCM_BASE_PTRS -#define NV_BASES NV_BASE_PTRS -#define OSC_BASES OSC_BASE_PTRS #define PDB0_DACINTC1 This_symbol_has_been_deprecated #define PDB0_DACINT1 This_symbol_has_been_deprecated -#define PDB_BASES PDB_BASE_PTRS -#define PIT_BASES PIT_BASE_PTRS -#define PMC_BASES PMC_BASE_PTRS -#define PORT_BASES PORT_BASE_PTRS -#define RCM_BASES RCM_BASE_PTRS -#define RFSYS_BASES RFSYS_BASE_PTRS -#define RFVBAT_BASES RFVBAT_BASE_PTRS -#define RTC_BASES RTC_BASE_PTRS -#define SIM_BASES SIM_BASE_PTRS +#define DSPI0 SPI0 +#define DSPI1 SPI1 +#define PTA_BASE GPIOA_BASE +#define PTA GPIOA +#define PTB_BASE GPIOB_BASE +#define PTB GPIOB +#define PTC_BASE GPIOC_BASE +#define PTC GPIOC +#define PTD_BASE GPIOD_BASE +#define PTD GPIOD +#define PTE_BASE GPIOE_BASE +#define PTE GPIOE +#define DMAMUX0 DMAMUX #define SMC_STOPCTRL_LPOPO_MASK This_symbol_has_been_deprecated #define SMC_STOPCTRL_LPOPO_SHIFT This_symbol_has_been_deprecated -#define SMC_BASES SMC_BASE_PTRS -#define SPI_BASES SPI_BASE_PTRS -#define UART_BASES UART_BASE_PTRS -#define USB_BASES USB_BASE_PTRS -#define VREF_BASES VREF_BASE_PTRS -#define WDOG_BASES WDOG_BASE_PTRS #define USB_ADDINFO_IRQNUM_MASK This_symbol_has_been_deprecated #define USB_ADDINFO_IRQNUM_SHIFT This_symbol_has_been_deprecated #define USB_ADDINFO_IRQNUM(x) This_symbol_has_been_deprecated @@ -11742,31 +8089,8 @@ typedef struct { #define LLW_IRQn LLWU_IRQn #define LLW_IRQHandler LLWU_IRQHandler -#define GPIOA_BASE PTA_BASE -#define GPIOB_BASE PTB_BASE -#define GPIOC_BASE PTC_BASE -#define GPIOD_BASE PTD_BASE -#define GPIOE_BASE PTE_BASE -#define GPIOF_BASE PTF_BASE -#define GPIOG_BASE PTG_BASE -#define GPIOA PTA -#define GPIOB PTB -#define GPIOC PTC -#define GPIOD PTD -#define GPIOE PTE -#define GPIOF PTF -#define GPIOG PTG -#define OSC0 OSC /*! * @} - */ /* end of group Backward_Compatibility_Symbols */ + */ /* end of group SDK_Compatibility_Symbols */ - -#else /* #if !defined(MK22F12810_H_) */ - /* There is already included the same memory map. Check if it is compatible (has the same major version) */ - #if (MCU_MEM_MAP_VERSION != 0x0100u) - #if (!defined(MCU_MEM_MAP_SUPPRESS_VERSION_WARNING)) - #warning There are included two not compatible versions of memory maps. Please check possible differences. - #endif /* (!defined(MCU_MEM_MAP_SUPPRESS_VERSION_WARNING)) */ - #endif /* (MCU_MEM_MAP_VERSION != 0x0100u) */ -#endif /* #if !defined(MK22F12810_H_) */ +#endif /* _MK22F12810_H_ */ diff --git a/cpu/k22f/include/vendor/MK22F25612.h b/cpu/k22f/include/vendor/MK22F25612.h index 4f34837667..c005c2789b 100644 --- a/cpu/k22f/include/vendor/MK22F25612.h +++ b/cpu/k22f/include/vendor/MK22F25612.h @@ -1,21 +1,27 @@ /* ** ################################################################### +** Processors: MK22FN128CAH12 +** MK22FN256CAH12 +** MK22FN256VDC12 +** MK22FN256VLH12 +** MK22FN256VLL12 +** MK22FN256VMP12 +** ** Compilers: Keil ARM C/C++ Compiler ** Freescale C/C++ for Embedded ARM ** GNU C Compiler -** GNU C Compiler - CodeSourcery Sourcery G++ ** IAR ANSI C/C++ Compiler for ARM +** MCUXpresso Compiler ** ** Reference manual: K22P121M120SF8RM, Rev. 1, March 24, 2014 ** Version: rev. 1.8, 2015-02-19 -** Build: b150225 +** Build: b170112 ** ** Abstract: ** CMSIS Peripheral Access Layer for MK22F25612 ** -** Copyright (c) 1997 - 2015 Freescale Semiconductor, Inc. -** All rights reserved. -** +** Copyright (c) 1997 - 2016 Freescale Semiconductor, Inc. +** Copyright 2016 - 2017 NXP ** Redistribution and use in source and binary forms, with or without modification, ** are permitted provided that the following conditions are met: ** @@ -26,7 +32,7 @@ ** list of conditions and the following disclaimer in the documentation and/or ** other materials provided with the distribution. ** -** o Neither the name of Freescale Semiconductor, Inc. nor the names of its +** o Neither the name of the copyright holder nor the names of its ** contributors may be used to endorse or promote products derived from this ** software without specific prior written permission. ** @@ -41,8 +47,8 @@ ** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ** -** http: www.freescale.com -** mail: support@freescale.com +** http: www.nxp.com +** mail: support@nxp.com ** ** Revisions: ** - rev. 1.0 (2013-09-17) @@ -79,29 +85,14 @@ * CMSIS Peripheral Access Layer for MK22F25612 */ - -/* ---------------------------------------------------------------------------- - -- MCU activation - ---------------------------------------------------------------------------- */ - -/* Prevention from multiple including the same memory map */ -#if !defined(MK22F25612_H_) /* Check if memory map has not been already included */ -#define MK22F25612_H_ -#define MCU_MK22F25612 - -/* Check if another memory map has not been also included */ -#if (defined(MCU_ACTIVE)) - #error MK22F25612 memory map: There is already included another memory map. Only one memory map can be included. -#endif /* (defined(MCU_ACTIVE)) */ -#define MCU_ACTIVE - -#include +#ifndef _MK22F25612_H_ +#define _MK22F25612_H_ /**< Symbol preventing repeated inclusion */ /** Memory map major version (memory maps with equal major version number are * compatible) */ -#define MCU_MEM_MAP_VERSION 0x0100u +#define MCU_MEM_MAP_VERSION 0x0100U /** Memory map minor version */ -#define MCU_MEM_MAP_VERSION_MINOR 0x0008u +#define MCU_MEM_MAP_VERSION_MINOR 0x0008U /** * @brief Macro to calculate address of an aliased word in the peripheral @@ -120,8 +111,8 @@ * @param Bit Bit number to access. * @return Value of the targeted bit in the bit band region. */ -#define BITBAND_REG32(Reg,Bit) (*((uint32_t volatile*)(BITBAND_REGADDR(Reg,Bit)))) -#define BITBAND_REG(Reg,Bit) (BITBAND_REG32(Reg,Bit)) +#define BITBAND_REG32(Reg,Bit) (*((uint32_t volatile*)(BITBAND_REGADDR((Reg),(Bit))))) +#define BITBAND_REG(Reg,Bit) (BITBAND_REG32((Reg),(Bit))) /** * @brief Macro to access a single bit of a peripheral register (bit band region * 0x40000000 to 0x400FFFFF) using the bit-band alias region access. Can @@ -130,7 +121,7 @@ * @param Bit Bit number to access. * @return Value of the targeted bit in the bit band region. */ -#define BITBAND_REG16(Reg,Bit) (*((uint16_t volatile*)(BITBAND_REGADDR(Reg,Bit)))) +#define BITBAND_REG16(Reg,Bit) (*((uint16_t volatile*)(BITBAND_REGADDR((Reg),(Bit))))) /** * @brief Macro to access a single bit of a peripheral register (bit band region * 0x40000000 to 0x400FFFFF) using the bit-band alias region access. Can @@ -139,7 +130,7 @@ * @param Bit Bit number to access. * @return Value of the targeted bit in the bit band region. */ -#define BITBAND_REG8(Reg,Bit) (*((uint8_t volatile*)(BITBAND_REGADDR(Reg,Bit)))) +#define BITBAND_REG8(Reg,Bit) (*((uint8_t volatile*)(BITBAND_REGADDR((Reg),(Bit))))) /* ---------------------------------------------------------------------------- -- Interrupt vector numbers @@ -283,6 +274,108 @@ typedef enum IRQn { */ /* end of group Cortex_Core_Configuration */ +/* ---------------------------------------------------------------------------- + -- Mapping Information + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup Mapping_Information Mapping Information + * @{ + */ + +/** Mapping Information */ +/*! + * @addtogroup edma_request + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! + * @brief Structure for the DMA hardware request + * + * Defines the structure for the DMA hardware request collections. The user can configure the + * hardware request into DMAMUX to trigger the DMA transfer accordingly. The index + * of the hardware request varies according to the to SoC. + */ +typedef enum _dma_request_source +{ + kDmaRequestMux0Disable = 0|0x100U, /**< DMAMUX TriggerDisabled. */ + kDmaRequestMux0Reserved1 = 1|0x100U, /**< Reserved1 */ + kDmaRequestMux0UART0Rx = 2|0x100U, /**< UART0 Receive. */ + kDmaRequestMux0UART0Tx = 3|0x100U, /**< UART0 Transmit. */ + kDmaRequestMux0UART1Rx = 4|0x100U, /**< UART1 Receive. */ + kDmaRequestMux0UART1Tx = 5|0x100U, /**< UART1 Transmit. */ + kDmaRequestMux0UART2Rx = 6|0x100U, /**< UART2 Receive. */ + kDmaRequestMux0UART2Tx = 7|0x100U, /**< UART2 Transmit. */ + kDmaRequestMux0Reserved8 = 8|0x100U, /**< Reserved8 */ + kDmaRequestMux0Reserved9 = 9|0x100U, /**< Reserved9 */ + kDmaRequestMux0Reserved10 = 10|0x100U, /**< Reserved10 */ + kDmaRequestMux0Reserved11 = 11|0x100U, /**< Reserved11 */ + kDmaRequestMux0I2S0Rx = 12|0x100U, /**< I2S0 Receive. */ + kDmaRequestMux0I2S0Tx = 13|0x100U, /**< I2S0 Transmit. */ + kDmaRequestMux0SPI0Rx = 14|0x100U, /**< SPI0 Receive. */ + kDmaRequestMux0SPI0Tx = 15|0x100U, /**< SPI0 Transmit. */ + kDmaRequestMux0SPI1 = 16|0x100U, /**< SPI1 Transmit or Receive. */ + kDmaRequestMux0Reserved17 = 17|0x100U, /**< Reserved17 */ + kDmaRequestMux0I2C0 = 18|0x100U, /**< I2C0. */ + kDmaRequestMux0I2C1 = 19|0x100U, /**< I2C1. */ + kDmaRequestMux0FTM0Channel0 = 20|0x100U, /**< FTM0 C0V. */ + kDmaRequestMux0FTM0Channel1 = 21|0x100U, /**< FTM0 C1V. */ + kDmaRequestMux0FTM0Channel2 = 22|0x100U, /**< FTM0 C2V. */ + kDmaRequestMux0FTM0Channel3 = 23|0x100U, /**< FTM0 C3V. */ + kDmaRequestMux0FTM0Channel4 = 24|0x100U, /**< FTM0 C4V. */ + kDmaRequestMux0FTM0Channel5 = 25|0x100U, /**< FTM0 C5V. */ + kDmaRequestMux0FTM0Channel6 = 26|0x100U, /**< FTM0 C6V. */ + kDmaRequestMux0FTM0Channel7 = 27|0x100U, /**< FTM0 C7V. */ + kDmaRequestMux0FTM1Channel0 = 28|0x100U, /**< FTM1 C0V. */ + kDmaRequestMux0FTM1Channel1 = 29|0x100U, /**< FTM1 C1V. */ + kDmaRequestMux0FTM2Channel0 = 30|0x100U, /**< FTM2 C0V. */ + kDmaRequestMux0FTM2Channel1 = 31|0x100U, /**< FTM2 C1V. */ + kDmaRequestMux0Reserved32 = 32|0x100U, /**< Reserved32 */ + kDmaRequestMux0Reserved33 = 33|0x100U, /**< Reserved33 */ + kDmaRequestMux0Reserved34 = 34|0x100U, /**< Reserved34 */ + kDmaRequestMux0Reserved35 = 35|0x100U, /**< Reserved35 */ + kDmaRequestMux0Reserved36 = 36|0x100U, /**< Reserved36 */ + kDmaRequestMux0Reserved37 = 37|0x100U, /**< Reserved37 */ + kDmaRequestMux0Reserved38 = 38|0x100U, /**< Reserved38 */ + kDmaRequestMux0Reserved39 = 39|0x100U, /**< Reserved39 */ + kDmaRequestMux0ADC0 = 40|0x100U, /**< ADC0. */ + kDmaRequestMux0ADC1 = 41|0x100U, /**< ADC1. */ + kDmaRequestMux0CMP0 = 42|0x100U, /**< CMP0. */ + kDmaRequestMux0CMP1 = 43|0x100U, /**< CMP1. */ + kDmaRequestMux0Reserved44 = 44|0x100U, /**< Reserved44 */ + kDmaRequestMux0DAC0 = 45|0x100U, /**< DAC0. */ + kDmaRequestMux0Reserved46 = 46|0x100U, /**< Reserved46 */ + kDmaRequestMux0Reserved47 = 47|0x100U, /**< Reserved47 */ + kDmaRequestMux0PDB = 48|0x100U, /**< PDB0. */ + kDmaRequestMux0PortA = 49|0x100U, /**< PTA. */ + kDmaRequestMux0PortB = 50|0x100U, /**< PTB. */ + kDmaRequestMux0PortC = 51|0x100U, /**< PTC. */ + kDmaRequestMux0PortD = 52|0x100U, /**< PTD. */ + kDmaRequestMux0PortE = 53|0x100U, /**< PTE. */ + kDmaRequestMux0Reserved54 = 54|0x100U, /**< Reserved54 */ + kDmaRequestMux0Reserved55 = 55|0x100U, /**< Reserved55 */ + kDmaRequestMux0Reserved56 = 56|0x100U, /**< Reserved56 */ + kDmaRequestMux0Reserved57 = 57|0x100U, /**< Reserved57 */ + kDmaRequestMux0LPUART0Rx = 58|0x100U, /**< LPUART0 Receive. */ + kDmaRequestMux0LPUART0Tx = 59|0x100U, /**< LPUART0 Transmit. */ + kDmaRequestMux0AlwaysOn60 = 60|0x100U, /**< DMAMUX Always Enabled slot. */ + kDmaRequestMux0AlwaysOn61 = 61|0x100U, /**< DMAMUX Always Enabled slot. */ + kDmaRequestMux0AlwaysOn62 = 62|0x100U, /**< DMAMUX Always Enabled slot. */ + kDmaRequestMux0AlwaysOn63 = 63|0x100U, /**< DMAMUX Always Enabled slot. */ +} dma_request_source_t; + +/* @} */ + + +/*! + * @} + */ /* end of group Mapping_Information */ + + /* ---------------------------------------------------------------------------- -- Device Peripheral Access Layer ---------------------------------------------------------------------------- */ @@ -348,51 +441,7 @@ typedef struct { __IO uint32_t CLM2; /**< ADC Minus-Side General Calibration Value Register, offset: 0x64 */ __IO uint32_t CLM1; /**< ADC Minus-Side General Calibration Value Register, offset: 0x68 */ __IO uint32_t CLM0; /**< ADC Minus-Side General Calibration Value Register, offset: 0x6C */ -} ADC_Type, *ADC_MemMapPtr; - -/* ---------------------------------------------------------------------------- - -- ADC - Register accessor macros - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup ADC_Register_Accessor_Macros ADC - Register accessor macros - * @{ - */ - - -/* ADC - Register accessors */ -#define ADC_SC1_REG(base,index) ((base)->SC1[index]) -#define ADC_SC1_COUNT 2 -#define ADC_CFG1_REG(base) ((base)->CFG1) -#define ADC_CFG2_REG(base) ((base)->CFG2) -#define ADC_R_REG(base,index) ((base)->R[index]) -#define ADC_R_COUNT 2 -#define ADC_CV1_REG(base) ((base)->CV1) -#define ADC_CV2_REG(base) ((base)->CV2) -#define ADC_SC2_REG(base) ((base)->SC2) -#define ADC_SC3_REG(base) ((base)->SC3) -#define ADC_OFS_REG(base) ((base)->OFS) -#define ADC_PG_REG(base) ((base)->PG) -#define ADC_MG_REG(base) ((base)->MG) -#define ADC_CLPD_REG(base) ((base)->CLPD) -#define ADC_CLPS_REG(base) ((base)->CLPS) -#define ADC_CLP4_REG(base) ((base)->CLP4) -#define ADC_CLP3_REG(base) ((base)->CLP3) -#define ADC_CLP2_REG(base) ((base)->CLP2) -#define ADC_CLP1_REG(base) ((base)->CLP1) -#define ADC_CLP0_REG(base) ((base)->CLP0) -#define ADC_CLMD_REG(base) ((base)->CLMD) -#define ADC_CLMS_REG(base) ((base)->CLMS) -#define ADC_CLM4_REG(base) ((base)->CLM4) -#define ADC_CLM3_REG(base) ((base)->CLM3) -#define ADC_CLM2_REG(base) ((base)->CLM2) -#define ADC_CLM1_REG(base) ((base)->CLM1) -#define ADC_CLM0_REG(base) ((base)->CLM0) - -/*! - * @} - */ /* end of group ADC_Register_Accessor_Macros */ - +} ADC_Type; /* ---------------------------------------------------------------------------- -- ADC Register Masks @@ -403,211 +452,197 @@ typedef struct { * @{ */ -/* SC1 Bit Fields */ -#define ADC_SC1_ADCH_MASK 0x1Fu -#define ADC_SC1_ADCH_SHIFT 0 -#define ADC_SC1_ADCH_WIDTH 5 -#define ADC_SC1_ADCH(x) (((uint32_t)(((uint32_t)(x))<CR0) -#define CMP_CR1_REG(base) ((base)->CR1) -#define CMP_FPR_REG(base) ((base)->FPR) -#define CMP_SCR_REG(base) ((base)->SCR) -#define CMP_DACCR_REG(base) ((base)->DACCR) -#define CMP_MUXCR_REG(base) ((base)->MUXCR) - -/*! - * @} - */ /* end of group CMP_Register_Accessor_Macros */ - +} CMP_Type; /* ---------------------------------------------------------------------------- -- CMP Register Masks @@ -767,100 +698,84 @@ typedef struct { * @{ */ -/* CR0 Bit Fields */ -#define CMP_CR0_HYSTCTR_MASK 0x3u -#define CMP_CR0_HYSTCTR_SHIFT 0 -#define CMP_CR0_HYSTCTR_WIDTH 2 -#define CMP_CR0_HYSTCTR(x) (((uint8_t)(((uint8_t)(x))<ACCESS16BIT.DATAL) -#define CRC_DATAH_REG(base) ((base)->ACCESS16BIT.DATAH) -#define CRC_DATA_REG(base) ((base)->DATA) -#define CRC_DATALL_REG(base) ((base)->ACCESS8BIT.DATALL) -#define CRC_DATALU_REG(base) ((base)->ACCESS8BIT.DATALU) -#define CRC_DATAHL_REG(base) ((base)->ACCESS8BIT.DATAHL) -#define CRC_DATAHU_REG(base) ((base)->ACCESS8BIT.DATAHU) -#define CRC_GPOLYL_REG(base) ((base)->GPOLY_ACCESS16BIT.GPOLYL) -#define CRC_GPOLYH_REG(base) ((base)->GPOLY_ACCESS16BIT.GPOLYH) -#define CRC_GPOLY_REG(base) ((base)->GPOLY) -#define CRC_GPOLYLL_REG(base) ((base)->GPOLY_ACCESS8BIT.GPOLYLL) -#define CRC_GPOLYLU_REG(base) ((base)->GPOLY_ACCESS8BIT.GPOLYLU) -#define CRC_GPOLYHL_REG(base) ((base)->GPOLY_ACCESS8BIT.GPOLYHL) -#define CRC_GPOLYHU_REG(base) ((base)->GPOLY_ACCESS8BIT.GPOLYHU) -#define CRC_CTRL_REG(base) ((base)->CTRL) -#define CRC_CTRLHU_REG(base) ((base)->CTRL_ACCESS8BIT.CTRLHU) - -/*! - * @} - */ /* end of group CRC_Register_Accessor_Macros */ - +} CRC_Type; /* ---------------------------------------------------------------------------- -- CRC Register Masks @@ -1009,134 +858,122 @@ typedef struct { * @{ */ -/* DATAL Bit Fields */ -#define CRC_DATAL_DATAL_MASK 0xFFFFu -#define CRC_DATAL_DATAL_SHIFT 0 -#define CRC_DATAL_DATAL_WIDTH 16 -#define CRC_DATAL_DATAL(x) (((uint16_t)(((uint16_t)(x))<DAT[index].DATL) -#define DAC_DATL_COUNT 16 -#define DAC_DATH_REG(base,index) ((base)->DAT[index].DATH) -#define DAC_DATH_COUNT 16 -#define DAC_SR_REG(base) ((base)->SR) -#define DAC_C0_REG(base) ((base)->C0) -#define DAC_C1_REG(base) ((base)->C1) -#define DAC_C2_REG(base) ((base)->C2) - -/*! - * @} - */ /* end of group DAC_Register_Accessor_Macros */ - +} DAC_Type; /* ---------------------------------------------------------------------------- -- DAC Register Masks @@ -1248,88 +1025,81 @@ typedef struct { * @{ */ -/* DATL Bit Fields */ -#define DAC_DATL_DATA0_MASK 0xFFu -#define DAC_DATL_DATA0_SHIFT 0 -#define DAC_DATL_DATA0_WIDTH 8 -#define DAC_DATL_DATA0(x) (((uint8_t)(((uint8_t)(x))<CR) -#define DMA_ES_REG(base) ((base)->ES) -#define DMA_ERQ_REG(base) ((base)->ERQ) -#define DMA_EEI_REG(base) ((base)->EEI) -#define DMA_CEEI_REG(base) ((base)->CEEI) -#define DMA_SEEI_REG(base) ((base)->SEEI) -#define DMA_CERQ_REG(base) ((base)->CERQ) -#define DMA_SERQ_REG(base) ((base)->SERQ) -#define DMA_CDNE_REG(base) ((base)->CDNE) -#define DMA_SSRT_REG(base) ((base)->SSRT) -#define DMA_CERR_REG(base) ((base)->CERR) -#define DMA_CINT_REG(base) ((base)->CINT) -#define DMA_INT_REG(base) ((base)->INT) -#define DMA_ERR_REG(base) ((base)->ERR) -#define DMA_HRS_REG(base) ((base)->HRS) -#define DMA_EARS_REG(base) ((base)->EARS) -#define DMA_DCHPRI3_REG(base) ((base)->DCHPRI3) -#define DMA_DCHPRI2_REG(base) ((base)->DCHPRI2) -#define DMA_DCHPRI1_REG(base) ((base)->DCHPRI1) -#define DMA_DCHPRI0_REG(base) ((base)->DCHPRI0) -#define DMA_DCHPRI7_REG(base) ((base)->DCHPRI7) -#define DMA_DCHPRI6_REG(base) ((base)->DCHPRI6) -#define DMA_DCHPRI5_REG(base) ((base)->DCHPRI5) -#define DMA_DCHPRI4_REG(base) ((base)->DCHPRI4) -#define DMA_DCHPRI11_REG(base) ((base)->DCHPRI11) -#define DMA_DCHPRI10_REG(base) ((base)->DCHPRI10) -#define DMA_DCHPRI9_REG(base) ((base)->DCHPRI9) -#define DMA_DCHPRI8_REG(base) ((base)->DCHPRI8) -#define DMA_DCHPRI15_REG(base) ((base)->DCHPRI15) -#define DMA_DCHPRI14_REG(base) ((base)->DCHPRI14) -#define DMA_DCHPRI13_REG(base) ((base)->DCHPRI13) -#define DMA_DCHPRI12_REG(base) ((base)->DCHPRI12) -#define DMA_SADDR_REG(base,index) ((base)->TCD[index].SADDR) -#define DMA_SADDR_COUNT 16 -#define DMA_SOFF_REG(base,index) ((base)->TCD[index].SOFF) -#define DMA_SOFF_COUNT 16 -#define DMA_ATTR_REG(base,index) ((base)->TCD[index].ATTR) -#define DMA_ATTR_COUNT 16 -#define DMA_NBYTES_MLNO_REG(base,index) ((base)->TCD[index].NBYTES_MLNO) -#define DMA_NBYTES_MLNO_COUNT 16 -#define DMA_NBYTES_MLOFFNO_REG(base,index) ((base)->TCD[index].NBYTES_MLOFFNO) -#define DMA_NBYTES_MLOFFNO_COUNT 16 -#define DMA_NBYTES_MLOFFYES_REG(base,index) ((base)->TCD[index].NBYTES_MLOFFYES) -#define DMA_NBYTES_MLOFFYES_COUNT 16 -#define DMA_SLAST_REG(base,index) ((base)->TCD[index].SLAST) -#define DMA_SLAST_COUNT 16 -#define DMA_DADDR_REG(base,index) ((base)->TCD[index].DADDR) -#define DMA_DADDR_COUNT 16 -#define DMA_DOFF_REG(base,index) ((base)->TCD[index].DOFF) -#define DMA_DOFF_COUNT 16 -#define DMA_CITER_ELINKNO_REG(base,index) ((base)->TCD[index].CITER_ELINKNO) -#define DMA_CITER_ELINKNO_COUNT 16 -#define DMA_CITER_ELINKYES_REG(base,index) ((base)->TCD[index].CITER_ELINKYES) -#define DMA_CITER_ELINKYES_COUNT 16 -#define DMA_DLAST_SGA_REG(base,index) ((base)->TCD[index].DLAST_SGA) -#define DMA_DLAST_SGA_COUNT 16 -#define DMA_CSR_REG(base,index) ((base)->TCD[index].CSR) -#define DMA_CSR_COUNT 16 -#define DMA_BITER_ELINKNO_REG(base,index) ((base)->TCD[index].BITER_ELINKNO) -#define DMA_BITER_ELINKNO_COUNT 16 -#define DMA_BITER_ELINKYES_REG(base,index) ((base)->TCD[index].BITER_ELINKYES) -#define DMA_BITER_ELINKYES_COUNT 16 - -/*! - * @} - */ /* end of group DMA_Register_Accessor_Macros */ - +} DMA_Type; /* ---------------------------------------------------------------------------- -- DMA Register Masks @@ -1576,957 +1208,823 @@ typedef struct { * @{ */ -/* CR Bit Fields */ -#define DMA_CR_EDBG_MASK 0x2u -#define DMA_CR_EDBG_SHIFT 1 -#define DMA_CR_EDBG_WIDTH 1 -#define DMA_CR_EDBG(x) (((uint32_t)(((uint32_t)(x))<CHCFG[index]) -#define DMAMUX_CHCFG_COUNT 16 - -/*! - * @} - */ /* end of group DMAMUX_Register_Accessor_Macros */ - +} DMAMUX_Type; /* ---------------------------------------------------------------------------- -- DMAMUX Register Masks @@ -2901,19 +2072,20 @@ typedef struct { * @{ */ -/* CHCFG Bit Fields */ -#define DMAMUX_CHCFG_SOURCE_MASK 0x3Fu -#define DMAMUX_CHCFG_SOURCE_SHIFT 0 -#define DMAMUX_CHCFG_SOURCE_WIDTH 6 -#define DMAMUX_CHCFG_SOURCE(x) (((uint8_t)(((uint8_t)(x))<CTRL) -#define EWM_SERV_REG(base) ((base)->SERV) -#define EWM_CMPL_REG(base) ((base)->CMPL) -#define EWM_CMPH_REG(base) ((base)->CMPH) -#define EWM_CLKPRESCALER_REG(base) ((base)->CLKPRESCALER) - -/*! - * @} - */ /* end of group EWM_Register_Accessor_Macros */ - +} EWM_Type; /* ---------------------------------------------------------------------------- -- EWM Register Masks @@ -3023,43 +2135,40 @@ typedef struct { * @{ */ -/* CTRL Bit Fields */ -#define EWM_CTRL_EWMEN_MASK 0x1u -#define EWM_CTRL_EWMEN_SHIFT 0 -#define EWM_CTRL_EWMEN_WIDTH 1 -#define EWM_CTRL_EWMEN(x) (((uint8_t)(((uint8_t)(x))<PFAPR) -#define FMC_PFB0CR_REG(base) ((base)->PFB0CR) -#define FMC_PFB1CR_REG(base) ((base)->PFB1CR) -#define FMC_TAGVDW0S_REG(base,index) ((base)->TAGVDW0S[index]) -#define FMC_TAGVDW0S_COUNT 8 -#define FMC_TAGVDW1S_REG(base,index) ((base)->TAGVDW1S[index]) -#define FMC_TAGVDW1S_COUNT 8 -#define FMC_TAGVDW2S_REG(base,index) ((base)->TAGVDW2S[index]) -#define FMC_TAGVDW2S_COUNT 8 -#define FMC_TAGVDW3S_REG(base,index) ((base)->TAGVDW3S[index]) -#define FMC_TAGVDW3S_COUNT 8 -#define FMC_DATA_U_REG(base,index,index2) ((base)->SET[index][index2].DATA_U) -#define FMC_DATA_U_COUNT 4 -#define FMC_DATA_U_COUNT2 8 -#define FMC_DATA_L_REG(base,index,index2) ((base)->SET[index][index2].DATA_L) -#define FMC_DATA_L_COUNT 4 -#define FMC_DATA_L_COUNT2 8 - -/*! - * @} - */ /* end of group FMC_Register_Accessor_Macros */ - +} FMC_Type; /* ---------------------------------------------------------------------------- -- FMC Register Masks @@ -3176,191 +2227,180 @@ typedef struct { * @{ */ -/* PFAPR Bit Fields */ -#define FMC_PFAPR_M0AP_MASK 0x3u -#define FMC_PFAPR_M0AP_SHIFT 0 -#define FMC_PFAPR_M0AP_WIDTH 2 -#define FMC_PFAPR_M0AP(x) (((uint32_t)(((uint32_t)(x))<FSTAT) -#define FTFA_FCNFG_REG(base) ((base)->FCNFG) -#define FTFA_FSEC_REG(base) ((base)->FSEC) -#define FTFA_FOPT_REG(base) ((base)->FOPT) -#define FTFA_FCCOB3_REG(base) ((base)->FCCOB3) -#define FTFA_FCCOB2_REG(base) ((base)->FCCOB2) -#define FTFA_FCCOB1_REG(base) ((base)->FCCOB1) -#define FTFA_FCCOB0_REG(base) ((base)->FCCOB0) -#define FTFA_FCCOB7_REG(base) ((base)->FCCOB7) -#define FTFA_FCCOB6_REG(base) ((base)->FCCOB6) -#define FTFA_FCCOB5_REG(base) ((base)->FCCOB5) -#define FTFA_FCCOB4_REG(base) ((base)->FCCOB4) -#define FTFA_FCCOBB_REG(base) ((base)->FCCOBB) -#define FTFA_FCCOBA_REG(base) ((base)->FCCOBA) -#define FTFA_FCCOB9_REG(base) ((base)->FCCOB9) -#define FTFA_FCCOB8_REG(base) ((base)->FCCOB8) -#define FTFA_FPROT3_REG(base) ((base)->FPROT3) -#define FTFA_FPROT2_REG(base) ((base)->FPROT2) -#define FTFA_FPROT1_REG(base) ((base)->FPROT1) -#define FTFA_FPROT0_REG(base) ((base)->FPROT0) -#define FTFA_XACCH3_REG(base) ((base)->XACCH3) -#define FTFA_XACCH2_REG(base) ((base)->XACCH2) -#define FTFA_XACCH1_REG(base) ((base)->XACCH1) -#define FTFA_XACCH0_REG(base) ((base)->XACCH0) -#define FTFA_XACCL3_REG(base) ((base)->XACCL3) -#define FTFA_XACCL2_REG(base) ((base)->XACCL2) -#define FTFA_XACCL1_REG(base) ((base)->XACCL1) -#define FTFA_XACCL0_REG(base) ((base)->XACCL0) -#define FTFA_SACCH3_REG(base) ((base)->SACCH3) -#define FTFA_SACCH2_REG(base) ((base)->SACCH2) -#define FTFA_SACCH1_REG(base) ((base)->SACCH1) -#define FTFA_SACCH0_REG(base) ((base)->SACCH0) -#define FTFA_SACCL3_REG(base) ((base)->SACCL3) -#define FTFA_SACCL2_REG(base) ((base)->SACCL2) -#define FTFA_SACCL1_REG(base) ((base)->SACCL1) -#define FTFA_SACCL0_REG(base) ((base)->SACCL0) -#define FTFA_FACSS_REG(base) ((base)->FACSS) -#define FTFA_FACSN_REG(base) ((base)->FACSN) - -/*! - * @} - */ /* end of group FTFA_Register_Accessor_Macros */ - +} FTFA_Type; /* ---------------------------------------------------------------------------- -- FTFA Register Masks @@ -3625,236 +2484,226 @@ typedef struct { * @{ */ -/* FSTAT Bit Fields */ -#define FTFA_FSTAT_MGSTAT0_MASK 0x1u -#define FTFA_FSTAT_MGSTAT0_SHIFT 0 -#define FTFA_FSTAT_MGSTAT0_WIDTH 1 -#define FTFA_FSTAT_MGSTAT0(x) (((uint8_t)(((uint8_t)(x))<SC) -#define FTM_CNT_REG(base) ((base)->CNT) -#define FTM_MOD_REG(base) ((base)->MOD) -#define FTM_CnSC_REG(base,index) ((base)->CONTROLS[index].CnSC) -#define FTM_CnSC_COUNT 8 -#define FTM_CnV_REG(base,index) ((base)->CONTROLS[index].CnV) -#define FTM_CnV_COUNT 8 -#define FTM_CNTIN_REG(base) ((base)->CNTIN) -#define FTM_STATUS_REG(base) ((base)->STATUS) -#define FTM_MODE_REG(base) ((base)->MODE) -#define FTM_SYNC_REG(base) ((base)->SYNC) -#define FTM_OUTINIT_REG(base) ((base)->OUTINIT) -#define FTM_OUTMASK_REG(base) ((base)->OUTMASK) -#define FTM_COMBINE_REG(base) ((base)->COMBINE) -#define FTM_DEADTIME_REG(base) ((base)->DEADTIME) -#define FTM_EXTTRIG_REG(base) ((base)->EXTTRIG) -#define FTM_POL_REG(base) ((base)->POL) -#define FTM_FMS_REG(base) ((base)->FMS) -#define FTM_FILTER_REG(base) ((base)->FILTER) -#define FTM_FLTCTRL_REG(base) ((base)->FLTCTRL) -#define FTM_QDCTRL_REG(base) ((base)->QDCTRL) -#define FTM_CONF_REG(base) ((base)->CONF) -#define FTM_FLTPOL_REG(base) ((base)->FLTPOL) -#define FTM_SYNCONF_REG(base) ((base)->SYNCONF) -#define FTM_INVCTRL_REG(base) ((base)->INVCTRL) -#define FTM_SWOCTRL_REG(base) ((base)->SWOCTRL) -#define FTM_PWMLOAD_REG(base) ((base)->PWMLOAD) - -/*! - * @} - */ /* end of group FTM_Register_Accessor_Macros */ - +} FTM_Type; /* ---------------------------------------------------------------------------- -- FTM Register Masks @@ -4029,759 +2777,608 @@ typedef struct { * @{ */ -/* SC Bit Fields */ -#define FTM_SC_PS_MASK 0x7u -#define FTM_SC_PS_SHIFT 0 -#define FTM_SC_PS_WIDTH 3 -#define FTM_SC_PS(x) (((uint32_t)(((uint32_t)(x))<PDOR) -#define GPIO_PSOR_REG(base) ((base)->PSOR) -#define GPIO_PCOR_REG(base) ((base)->PCOR) -#define GPIO_PTOR_REG(base) ((base)->PTOR) -#define GPIO_PDIR_REG(base) ((base)->PDIR) -#define GPIO_PDDR_REG(base) ((base)->PDDR) - -/*! - * @} - */ /* end of group GPIO_Register_Accessor_Macros */ - +} GPIO_Type; /* ---------------------------------------------------------------------------- -- GPIO Register Masks @@ -4988,36 +3438,36 @@ typedef struct { * @{ */ -/* PDOR Bit Fields */ -#define GPIO_PDOR_PDO_MASK 0xFFFFFFFFu -#define GPIO_PDOR_PDO_SHIFT 0 -#define GPIO_PDOR_PDO_WIDTH 32 -#define GPIO_PDOR_PDO(x) (((uint32_t)(((uint32_t)(x))<A1) -#define I2C_F_REG(base) ((base)->F) -#define I2C_C1_REG(base) ((base)->C1) -#define I2C_S_REG(base) ((base)->S) -#define I2C_D_REG(base) ((base)->D) -#define I2C_C2_REG(base) ((base)->C2) -#define I2C_FLT_REG(base) ((base)->FLT) -#define I2C_RA_REG(base) ((base)->RA) -#define I2C_SMB_REG(base) ((base)->SMB) -#define I2C_A2_REG(base) ((base)->A2) -#define I2C_SLTH_REG(base) ((base)->SLTH) -#define I2C_SLTL_REG(base) ((base)->SLTL) - -/*! - * @} - */ /* end of group I2C_Register_Accessor_Macros */ - +} I2C_Type; /* ---------------------------------------------------------------------------- -- I2C Register Masks @@ -5175,190 +3539,159 @@ typedef struct { * @{ */ -/* A1 Bit Fields */ -#define I2C_A1_AD_MASK 0xFEu -#define I2C_A1_AD_SHIFT 1 -#define I2C_A1_AD_WIDTH 7 -#define I2C_A1_AD(x) (((uint8_t)(((uint8_t)(x))<TCSR) -#define I2S_TCR1_REG(base) ((base)->TCR1) -#define I2S_TCR2_REG(base) ((base)->TCR2) -#define I2S_TCR3_REG(base) ((base)->TCR3) -#define I2S_TCR4_REG(base) ((base)->TCR4) -#define I2S_TCR5_REG(base) ((base)->TCR5) -#define I2S_TDR_REG(base,index) ((base)->TDR[index]) -#define I2S_TDR_COUNT 1 -#define I2S_TFR_REG(base,index) ((base)->TFR[index]) -#define I2S_TFR_COUNT 1 -#define I2S_TMR_REG(base) ((base)->TMR) -#define I2S_RCSR_REG(base) ((base)->RCSR) -#define I2S_RCR1_REG(base) ((base)->RCR1) -#define I2S_RCR2_REG(base) ((base)->RCR2) -#define I2S_RCR3_REG(base) ((base)->RCR3) -#define I2S_RCR4_REG(base) ((base)->RCR4) -#define I2S_RCR5_REG(base) ((base)->RCR5) -#define I2S_RDR_REG(base,index) ((base)->RDR[index]) -#define I2S_RDR_COUNT 1 -#define I2S_RFR_REG(base,index) ((base)->RFR[index]) -#define I2S_RFR_COUNT 1 -#define I2S_RMR_REG(base) ((base)->RMR) -#define I2S_MCR_REG(base) ((base)->MCR) -#define I2S_MDR_REG(base) ((base)->MDR) - -/*! - * @} - */ /* end of group I2S_Register_Accessor_Macros */ - +} I2S_Type; /* ---------------------------------------------------------------------------- -- I2S Register Masks @@ -5522,398 +3769,337 @@ typedef struct { * @{ */ -/* TCSR Bit Fields */ -#define I2S_TCSR_FRDE_MASK 0x1u -#define I2S_TCSR_FRDE_SHIFT 0 -#define I2S_TCSR_FRDE_WIDTH 1 -#define I2S_TCSR_FRDE(x) (((uint32_t)(((uint32_t)(x))<PE1) -#define LLWU_PE2_REG(base) ((base)->PE2) -#define LLWU_PE3_REG(base) ((base)->PE3) -#define LLWU_PE4_REG(base) ((base)->PE4) -#define LLWU_ME_REG(base) ((base)->ME) -#define LLWU_F1_REG(base) ((base)->F1) -#define LLWU_F2_REG(base) ((base)->F2) -#define LLWU_F3_REG(base) ((base)->F3) -#define LLWU_FILT1_REG(base) ((base)->FILT1) -#define LLWU_FILT2_REG(base) ((base)->FILT2) - -/*! - * @} - */ /* end of group LLWU_Register_Accessor_Macros */ - +} LLWU_Type; /* ---------------------------------------------------------------------------- -- LLWU Register Masks @@ -6042,232 +4156,188 @@ typedef struct { * @{ */ -/* PE1 Bit Fields */ -#define LLWU_PE1_WUPE0_MASK 0x3u -#define LLWU_PE1_WUPE0_SHIFT 0 -#define LLWU_PE1_WUPE0_WIDTH 2 -#define LLWU_PE1_WUPE0(x) (((uint8_t)(((uint8_t)(x))<CSR) -#define LPTMR_PSR_REG(base) ((base)->PSR) -#define LPTMR_CMR_REG(base) ((base)->CMR) -#define LPTMR_CNR_REG(base) ((base)->CNR) - -/*! - * @} - */ /* end of group LPTMR_Register_Accessor_Macros */ - +} LPTMR_Type; /* ---------------------------------------------------------------------------- -- LPTMR Register Masks @@ -6367,58 +4387,50 @@ typedef struct { * @{ */ -/* CSR Bit Fields */ -#define LPTMR_CSR_TEN_MASK 0x1u -#define LPTMR_CSR_TEN_SHIFT 0 -#define LPTMR_CSR_TEN_WIDTH 1 -#define LPTMR_CSR_TEN(x) (((uint32_t)(((uint32_t)(x))<BAUD) -#define LPUART_STAT_REG(base) ((base)->STAT) -#define LPUART_CTRL_REG(base) ((base)->CTRL) -#define LPUART_DATA_REG(base) ((base)->DATA) -#define LPUART_MATCH_REG(base) ((base)->MATCH) -#define LPUART_MODIR_REG(base) ((base)->MODIR) - -/*! - * @} - */ /* end of group LPUART_Register_Accessor_Macros */ - +} LPUART_Type; /* ---------------------------------------------------------------------------- -- LPUART Register Masks @@ -6516,344 +4482,267 @@ typedef struct { * @{ */ -/* BAUD Bit Fields */ -#define LPUART_BAUD_SBR_MASK 0x1FFFu -#define LPUART_BAUD_SBR_SHIFT 0 -#define LPUART_BAUD_SBR_WIDTH 13 -#define LPUART_BAUD_SBR(x) (((uint32_t)(((uint32_t)(x))<C1) -#define MCG_C2_REG(base) ((base)->C2) -#define MCG_C3_REG(base) ((base)->C3) -#define MCG_C4_REG(base) ((base)->C4) -#define MCG_C5_REG(base) ((base)->C5) -#define MCG_C6_REG(base) ((base)->C6) -#define MCG_S_REG(base) ((base)->S) -#define MCG_SC_REG(base) ((base)->SC) -#define MCG_ATCVH_REG(base) ((base)->ATCVH) -#define MCG_ATCVL_REG(base) ((base)->ATCVL) -#define MCG_C7_REG(base) ((base)->C7) -#define MCG_C8_REG(base) ((base)->C8) - -/*! - * @} - */ /* end of group MCG_Register_Accessor_Macros */ - +} MCG_Type; /* ---------------------------------------------------------------------------- -- MCG Register Masks @@ -6968,194 +4803,162 @@ typedef struct { * @{ */ -/* C1 Bit Fields */ -#define MCG_C1_IREFSTEN_MASK 0x1u -#define MCG_C1_IREFSTEN_SHIFT 0 -#define MCG_C1_IREFSTEN_WIDTH 1 -#define MCG_C1_IREFSTEN(x) (((uint8_t)(((uint8_t)(x))<PLASC) -#define MCM_PLAMC_REG(base) ((base)->PLAMC) -#define MCM_PLACR_REG(base) ((base)->PLACR) -#define MCM_ISCR_REG(base) ((base)->ISCR) -#define MCM_CPO_REG(base) ((base)->CPO) - -/*! - * @} - */ /* end of group MCM_Register_Accessor_Macros */ - +} MCM_Type; /* ---------------------------------------------------------------------------- -- MCM Register Masks @@ -7259,83 +5009,70 @@ typedef struct { * @{ */ -/* PLASC Bit Fields */ -#define MCM_PLASC_ASC_MASK 0xFFu -#define MCM_PLASC_ASC_SHIFT 0 -#define MCM_PLASC_ASC_WIDTH 8 -#define MCM_PLASC_ASC(x) (((uint16_t)(((uint16_t)(x))<BACKKEY3) -#define NV_BACKKEY2_REG(base) ((base)->BACKKEY2) -#define NV_BACKKEY1_REG(base) ((base)->BACKKEY1) -#define NV_BACKKEY0_REG(base) ((base)->BACKKEY0) -#define NV_BACKKEY7_REG(base) ((base)->BACKKEY7) -#define NV_BACKKEY6_REG(base) ((base)->BACKKEY6) -#define NV_BACKKEY5_REG(base) ((base)->BACKKEY5) -#define NV_BACKKEY4_REG(base) ((base)->BACKKEY4) -#define NV_FPROT3_REG(base) ((base)->FPROT3) -#define NV_FPROT2_REG(base) ((base)->FPROT2) -#define NV_FPROT1_REG(base) ((base)->FPROT1) -#define NV_FPROT0_REG(base) ((base)->FPROT0) -#define NV_FSEC_REG(base) ((base)->FSEC) -#define NV_FOPT_REG(base) ((base)->FOPT) - -/*! - * @} - */ /* end of group NV_Register_Accessor_Macros */ - +} NV_Type; /* ---------------------------------------------------------------------------- -- NV Register Masks @@ -7450,100 +5132,94 @@ typedef struct { * @{ */ -/* BACKKEY3 Bit Fields */ -#define NV_BACKKEY3_KEY_MASK 0xFFu -#define NV_BACKKEY3_KEY_SHIFT 0 -#define NV_BACKKEY3_KEY_WIDTH 8 -#define NV_BACKKEY3_KEY(x) (((uint8_t)(((uint8_t)(x))<CR) -#define OSC_DIV_REG(base) ((base)->DIV) - -/*! - * @} - */ /* end of group OSC_Register_Accessor_Macros */ - +} OSC_Type; /* ---------------------------------------------------------------------------- -- OSC Register Masks @@ -7642,36 +5266,31 @@ typedef struct { * @{ */ -/* CR Bit Fields */ -#define OSC_CR_SC16P_MASK 0x1u -#define OSC_CR_SC16P_SHIFT 0 -#define OSC_CR_SC16P_WIDTH 1 -#define OSC_CR_SC16P(x) (((uint8_t)(((uint8_t)(x))<SC) -#define PDB_MOD_REG(base) ((base)->MOD) -#define PDB_CNT_REG(base) ((base)->CNT) -#define PDB_IDLY_REG(base) ((base)->IDLY) -#define PDB_C1_REG(base,index) ((base)->CH[index].C1) -#define PDB_C1_COUNT 2 -#define PDB_S_REG(base,index) ((base)->CH[index].S) -#define PDB_S_COUNT 2 -#define PDB_DLY_REG(base,index,index2) ((base)->CH[index].DLY[index2]) -#define PDB_DLY_COUNT 2 -#define PDB_DLY_COUNT2 2 -#define PDB_INTC_REG(base,index) ((base)->DAC[index].INTC) -#define PDB_INTC_COUNT 1 -#define PDB_INT_REG(base,index) ((base)->DAC[index].INT) -#define PDB_INT_COUNT 1 -#define PDB_POEN_REG(base) ((base)->POEN) -#define PDB_PODLY_REG(base,index) ((base)->PODLY[index]) -#define PDB_PODLY_COUNT 2 - -/*! - * @} - */ /* end of group PDB_Register_Accessor_Macros */ - +} PDB_Type; /* ---------------------------------------------------------------------------- -- PDB Register Masks @@ -7789,125 +5352,130 @@ typedef struct { * @{ */ -/* SC Bit Fields */ -#define PDB_SC_LDOK_MASK 0x1u -#define PDB_SC_LDOK_SHIFT 0 -#define PDB_SC_LDOK_WIDTH 1 -#define PDB_SC_LDOK(x) (((uint32_t)(((uint32_t)(x))<MCR) -#define PIT_LDVAL_REG(base,index) ((base)->CHANNEL[index].LDVAL) -#define PIT_LDVAL_COUNT 4 -#define PIT_CVAL_REG(base,index) ((base)->CHANNEL[index].CVAL) -#define PIT_CVAL_COUNT 4 -#define PIT_TCTRL_REG(base,index) ((base)->CHANNEL[index].TCTRL) -#define PIT_TCTRL_COUNT 4 -#define PIT_TFLG_REG(base,index) ((base)->CHANNEL[index].TFLG) -#define PIT_TFLG_COUNT 4 - -/*! - * @} - */ /* end of group PIT_Register_Accessor_Macros */ - +} PIT_Type; /* ---------------------------------------------------------------------------- -- PIT Register Masks @@ -8031,43 +5529,52 @@ typedef struct { * @{ */ -/* MCR Bit Fields */ -#define PIT_MCR_FRZ_MASK 0x1u -#define PIT_MCR_FRZ_SHIFT 0 -#define PIT_MCR_FRZ_WIDTH 1 -#define PIT_MCR_FRZ(x) (((uint32_t)(((uint32_t)(x))<LVDSC1) -#define PMC_LVDSC2_REG(base) ((base)->LVDSC2) -#define PMC_REGSC_REG(base) ((base)->REGSC) - -/*! - * @} - */ /* end of group PMC_Register_Accessor_Macros */ - +} PMC_Type; /* ---------------------------------------------------------------------------- -- PMC Register Masks @@ -8178,61 +5623,51 @@ typedef struct { * @{ */ -/* LVDSC1 Bit Fields */ -#define PMC_LVDSC1_LVDV_MASK 0x3u -#define PMC_LVDSC1_LVDV_SHIFT 0 -#define PMC_LVDSC1_LVDV_WIDTH 2 -#define PMC_LVDSC1_LVDV(x) (((uint8_t)(((uint8_t)(x))<PCR[index]) -#define PORT_PCR_COUNT 32 -#define PORT_GPCLR_REG(base) ((base)->GPCLR) -#define PORT_GPCHR_REG(base) ((base)->GPCHR) -#define PORT_ISFR_REG(base) ((base)->ISFR) -#define PORT_DFER_REG(base) ((base)->DFER) -#define PORT_DFCR_REG(base) ((base)->DFCR) -#define PORT_DFWR_REG(base) ((base)->DFWR) - -/*! - * @} - */ /* end of group PORT_Register_Accessor_Macros */ - +} PORT_Type; /* ---------------------------------------------------------------------------- -- PORT Register Masks @@ -8334,85 +5722,77 @@ typedef struct { * @{ */ -/* PCR Bit Fields */ -#define PORT_PCR_PS_MASK 0x1u -#define PORT_PCR_PS_SHIFT 0 -#define PORT_PCR_PS_WIDTH 1 -#define PORT_PCR_PS(x) (((uint32_t)(((uint32_t)(x))<SRS0) -#define RCM_SRS1_REG(base) ((base)->SRS1) -#define RCM_RPFC_REG(base) ((base)->RPFC) -#define RCM_RPFW_REG(base) ((base)->RPFW) -#define RCM_MR_REG(base) ((base)->MR) -#define RCM_SSRS0_REG(base) ((base)->SSRS0) -#define RCM_SSRS1_REG(base) ((base)->SSRS1) - -/*! - * @} - */ /* end of group RCM_Register_Accessor_Macros */ - +} RCM_Type; /* ---------------------------------------------------------------------------- -- RCM Register Masks @@ -8719,133 +5863,110 @@ typedef struct { * @{ */ -/* SRS0 Bit Fields */ -#define RCM_SRS0_WAKEUP_MASK 0x1u -#define RCM_SRS0_WAKEUP_SHIFT 0 -#define RCM_SRS0_WAKEUP_WIDTH 1 -#define RCM_SRS0_WAKEUP(x) (((uint8_t)(((uint8_t)(x))<REG[index]) -#define RFSYS_REG_COUNT 8 - -/*! - * @} - */ /* end of group RFSYS_Register_Accessor_Macros */ - +} RFSYS_Type; /* ---------------------------------------------------------------------------- -- RFSYS Register Masks @@ -8935,23 +6011,23 @@ typedef struct { * @{ */ -/* REG Bit Fields */ -#define RFSYS_REG_LL_MASK 0xFFu -#define RFSYS_REG_LL_SHIFT 0 -#define RFSYS_REG_LL_WIDTH 8 -#define RFSYS_REG_LL(x) (((uint32_t)(((uint32_t)(x))<REG[index]) -#define RFVBAT_REG_COUNT 8 - -/*! - * @} - */ /* end of group RFVBAT_Register_Accessor_Macros */ - +} RFVBAT_Type; /* ---------------------------------------------------------------------------- -- RFVBAT Register Masks @@ -9045,23 +6072,23 @@ typedef struct { * @{ */ -/* REG Bit Fields */ -#define RFVBAT_REG_LL_MASK 0xFFu -#define RFVBAT_REG_LL_SHIFT 0 -#define RFVBAT_REG_LL_WIDTH 8 -#define RFVBAT_REG_LL(x) (((uint32_t)(((uint32_t)(x))<CR) -#define RNG_SR_REG(base) ((base)->SR) -#define RNG_ER_REG(base) ((base)->ER) -#define RNG_OR_REG(base) ((base)->OR) - -/*! - * @} - */ /* end of group RNG_Register_Accessor_Macros */ - +} RNG_Type; /* ---------------------------------------------------------------------------- -- RNG Register Masks @@ -9160,66 +6136,56 @@ typedef struct { * @{ */ -/* CR Bit Fields */ -#define RNG_CR_GO_MASK 0x1u -#define RNG_CR_GO_SHIFT 0 -#define RNG_CR_GO_WIDTH 1 -#define RNG_CR_GO(x) (((uint32_t)(((uint32_t)(x))<TSR) -#define RTC_TPR_REG(base) ((base)->TPR) -#define RTC_TAR_REG(base) ((base)->TAR) -#define RTC_TCR_REG(base) ((base)->TCR) -#define RTC_CR_REG(base) ((base)->CR) -#define RTC_SR_REG(base) ((base)->SR) -#define RTC_LR_REG(base) ((base)->LR) -#define RTC_IER_REG(base) ((base)->IER) -#define RTC_WAR_REG(base) ((base)->WAR) -#define RTC_RAR_REG(base) ((base)->RAR) - -/*! - * @} - */ /* end of group RTC_Register_Accessor_Macros */ - +} RTC_Type; /* ---------------------------------------------------------------------------- -- RTC Register Masks @@ -9326,204 +6242,167 @@ typedef struct { * @{ */ -/* TSR Bit Fields */ -#define RTC_TSR_TSR_MASK 0xFFFFFFFFu -#define RTC_TSR_TSR_SHIFT 0 -#define RTC_TSR_TSR_WIDTH 32 -#define RTC_TSR_TSR(x) (((uint32_t)(((uint32_t)(x))<SOPT1) -#define SIM_SOPT1CFG_REG(base) ((base)->SOPT1CFG) -#define SIM_SOPT2_REG(base) ((base)->SOPT2) -#define SIM_SOPT4_REG(base) ((base)->SOPT4) -#define SIM_SOPT5_REG(base) ((base)->SOPT5) -#define SIM_SOPT7_REG(base) ((base)->SOPT7) -#define SIM_SOPT8_REG(base) ((base)->SOPT8) -#define SIM_SDID_REG(base) ((base)->SDID) -#define SIM_SCGC4_REG(base) ((base)->SCGC4) -#define SIM_SCGC5_REG(base) ((base)->SCGC5) -#define SIM_SCGC6_REG(base) ((base)->SCGC6) -#define SIM_SCGC7_REG(base) ((base)->SCGC7) -#define SIM_CLKDIV1_REG(base) ((base)->CLKDIV1) -#define SIM_CLKDIV2_REG(base) ((base)->CLKDIV2) -#define SIM_FCFG1_REG(base) ((base)->FCFG1) -#define SIM_FCFG2_REG(base) ((base)->FCFG2) -#define SIM_UIDH_REG(base) ((base)->UIDH) -#define SIM_UIDMH_REG(base) ((base)->UIDMH) -#define SIM_UIDML_REG(base) ((base)->UIDML) -#define SIM_UIDL_REG(base) ((base)->UIDL) - -/*! - * @} - */ /* end of group SIM_Register_Accessor_Macros */ - +} SIM_Type; /* ---------------------------------------------------------------------------- -- SIM Register Masks @@ -9661,438 +6474,355 @@ typedef struct { * @{ */ -/* SOPT1 Bit Fields */ -#define SIM_SOPT1_RAMSIZE_MASK 0xF000u -#define SIM_SOPT1_RAMSIZE_SHIFT 12 -#define SIM_SOPT1_RAMSIZE_WIDTH 4 -#define SIM_SOPT1_RAMSIZE(x) (((uint32_t)(((uint32_t)(x))<PMPROT) -#define SMC_PMCTRL_REG(base) ((base)->PMCTRL) -#define SMC_STOPCTRL_REG(base) ((base)->STOPCTRL) -#define SMC_PMSTAT_REG(base) ((base)->PMSTAT) - -/*! - * @} - */ /* end of group SMC_Register_Accessor_Macros */ - +} SMC_Type; /* ---------------------------------------------------------------------------- -- SMC Register Masks @@ -10200,54 +6870,47 @@ typedef struct { * @{ */ -/* PMPROT Bit Fields */ -#define SMC_PMPROT_AVLLS_MASK 0x2u -#define SMC_PMPROT_AVLLS_SHIFT 1 -#define SMC_PMPROT_AVLLS_WIDTH 1 -#define SMC_PMPROT_AVLLS(x) (((uint8_t)(((uint8_t)(x))<MCR) -#define SPI_TCR_REG(base) ((base)->TCR) -#define SPI_CTAR_REG(base,index2) ((base)->CTAR[index2]) -#define SPI_CTAR_COUNT 2 -#define SPI_CTAR_SLAVE_REG(base,index2) ((base)->CTAR_SLAVE[index2]) -#define SPI_CTAR_SLAVE_COUNT 1 -#define SPI_SR_REG(base) ((base)->SR) -#define SPI_RSER_REG(base) ((base)->RSER) -#define SPI_PUSHR_REG(base) ((base)->PUSHR) -#define SPI_PUSHR_SLAVE_REG(base) ((base)->PUSHR_SLAVE) -#define SPI_POPR_REG(base) ((base)->POPR) -#define SPI_TXFR0_REG(base) ((base)->TXFR0) -#define SPI_TXFR1_REG(base) ((base)->TXFR1) -#define SPI_TXFR2_REG(base) ((base)->TXFR2) -#define SPI_TXFR3_REG(base) ((base)->TXFR3) -#define SPI_RXFR0_REG(base) ((base)->RXFR0) -#define SPI_RXFR1_REG(base) ((base)->RXFR1) -#define SPI_RXFR2_REG(base) ((base)->RXFR2) -#define SPI_RXFR3_REG(base) ((base)->RXFR3) - -/*! - * @} - */ /* end of group SPI_Register_Accessor_Macros */ - +} SPI_Type; /* ---------------------------------------------------------------------------- -- SPI Register Masks @@ -10374,311 +6978,262 @@ typedef struct { * @{ */ -/* MCR Bit Fields */ -#define SPI_MCR_HALT_MASK 0x1u -#define SPI_MCR_HALT_SHIFT 0 -#define SPI_MCR_HALT_WIDTH 1 -#define SPI_MCR_HALT(x) (((uint32_t)(((uint32_t)(x))<BDH) -#define UART_BDL_REG(base) ((base)->BDL) -#define UART_C1_REG(base) ((base)->C1) -#define UART_C2_REG(base) ((base)->C2) -#define UART_S1_REG(base) ((base)->S1) -#define UART_S2_REG(base) ((base)->S2) -#define UART_C3_REG(base) ((base)->C3) -#define UART_D_REG(base) ((base)->D) -#define UART_MA1_REG(base) ((base)->MA1) -#define UART_MA2_REG(base) ((base)->MA2) -#define UART_C4_REG(base) ((base)->C4) -#define UART_C5_REG(base) ((base)->C5) -#define UART_ED_REG(base) ((base)->ED) -#define UART_MODEM_REG(base) ((base)->MODEM) -#define UART_IR_REG(base) ((base)->IR) -#define UART_PFIFO_REG(base) ((base)->PFIFO) -#define UART_CFIFO_REG(base) ((base)->CFIFO) -#define UART_SFIFO_REG(base) ((base)->SFIFO) -#define UART_TWFIFO_REG(base) ((base)->TWFIFO) -#define UART_TCFIFO_REG(base) ((base)->TCFIFO) -#define UART_RWFIFO_REG(base) ((base)->RWFIFO) -#define UART_RCFIFO_REG(base) ((base)->RCFIFO) -#define UART_C7816_REG(base) ((base)->C7816) -#define UART_IE7816_REG(base) ((base)->IE7816) -#define UART_IS7816_REG(base) ((base)->IS7816) -#define UART_WP7816_REG(base) ((base)->WP7816) -#define UART_WN7816_REG(base) ((base)->WN7816) -#define UART_WF7816_REG(base) ((base)->WF7816) -#define UART_ET7816_REG(base) ((base)->ET7816) -#define UART_TL7816_REG(base) ((base)->TL7816) -#define UART_AP7816A_T0_REG(base) ((base)->AP7816A_T0) -#define UART_AP7816B_T0_REG(base) ((base)->AP7816B_T0) -#define UART_WP7816A_T0_REG(base) ((base)->TYPE0.WP7816A_T0) -#define UART_WP7816B_T0_REG(base) ((base)->TYPE0.WP7816B_T0) -#define UART_WP7816A_T1_REG(base) ((base)->TYPE1.WP7816A_T1) -#define UART_WP7816B_T1_REG(base) ((base)->TYPE1.WP7816B_T1) -#define UART_WGP7816_T1_REG(base) ((base)->WGP7816_T1) -#define UART_WP7816C_T1_REG(base) ((base)->WP7816C_T1) - -/*! - * @} - */ /* end of group UART_Register_Accessor_Macros */ - +} UART_Type; /* ---------------------------------------------------------------------------- -- UART Register Masks @@ -10893,504 +7330,427 @@ typedef struct { * @{ */ -/* BDH Bit Fields */ -#define UART_BDH_SBR_MASK 0x1Fu -#define UART_BDH_SBR_SHIFT 0 -#define UART_BDH_SBR_WIDTH 5 -#define UART_BDH_SBR(x) (((uint8_t)(((uint8_t)(x))<PERID) -#define USB_IDCOMP_REG(base) ((base)->IDCOMP) -#define USB_REV_REG(base) ((base)->REV) -#define USB_ADDINFO_REG(base) ((base)->ADDINFO) -#define USB_OTGISTAT_REG(base) ((base)->OTGISTAT) -#define USB_OTGICR_REG(base) ((base)->OTGICR) -#define USB_OTGSTAT_REG(base) ((base)->OTGSTAT) -#define USB_OTGCTL_REG(base) ((base)->OTGCTL) -#define USB_ISTAT_REG(base) ((base)->ISTAT) -#define USB_INTEN_REG(base) ((base)->INTEN) -#define USB_ERRSTAT_REG(base) ((base)->ERRSTAT) -#define USB_ERREN_REG(base) ((base)->ERREN) -#define USB_STAT_REG(base) ((base)->STAT) -#define USB_CTL_REG(base) ((base)->CTL) -#define USB_ADDR_REG(base) ((base)->ADDR) -#define USB_BDTPAGE1_REG(base) ((base)->BDTPAGE1) -#define USB_FRMNUML_REG(base) ((base)->FRMNUML) -#define USB_FRMNUMH_REG(base) ((base)->FRMNUMH) -#define USB_TOKEN_REG(base) ((base)->TOKEN) -#define USB_SOFTHLD_REG(base) ((base)->SOFTHLD) -#define USB_BDTPAGE2_REG(base) ((base)->BDTPAGE2) -#define USB_BDTPAGE3_REG(base) ((base)->BDTPAGE3) -#define USB_ENDPT_REG(base,index) ((base)->ENDPOINT[index].ENDPT) -#define USB_ENDPT_COUNT 16 -#define USB_USBCTRL_REG(base) ((base)->USBCTRL) -#define USB_OBSERVE_REG(base) ((base)->OBSERVE) -#define USB_CONTROL_REG(base) ((base)->CONTROL) -#define USB_USBTRC0_REG(base) ((base)->USBTRC0) -#define USB_USBFRMADJUST_REG(base) ((base)->USBFRMADJUST) -#define USB_CLK_RECOVER_CTRL_REG(base) ((base)->CLK_RECOVER_CTRL) -#define USB_CLK_RECOVER_IRC_EN_REG(base) ((base)->CLK_RECOVER_IRC_EN) -#define USB_CLK_RECOVER_INT_STATUS_REG(base) ((base)->CLK_RECOVER_INT_STATUS) - -/*! - * @} - */ /* end of group USB_Register_Accessor_Macros */ - +} USB_Type; /* ---------------------------------------------------------------------------- -- USB Register Masks @@ -11662,445 +7868,377 @@ typedef struct { * @{ */ -/* PERID Bit Fields */ -#define USB_PERID_ID_MASK 0x3Fu -#define USB_PERID_ID_SHIFT 0 -#define USB_PERID_ID_WIDTH 6 -#define USB_PERID_ID(x) (((uint8_t)(((uint8_t)(x))<TRM) -#define VREF_SC_REG(base) ((base)->SC) - -/*! - * @} - */ /* end of group VREF_Register_Accessor_Macros */ - +} VREF_Type; /* ---------------------------------------------------------------------------- -- VREF Register Masks @@ -12235,36 +8286,31 @@ typedef struct { * @{ */ -/* TRM Bit Fields */ -#define VREF_TRM_TRIM_MASK 0x3Fu -#define VREF_TRM_TRIM_SHIFT 0 -#define VREF_TRM_TRIM_WIDTH 6 -#define VREF_TRM_TRIM(x) (((uint8_t)(((uint8_t)(x))<STCTRLH) -#define WDOG_STCTRLL_REG(base) ((base)->STCTRLL) -#define WDOG_TOVALH_REG(base) ((base)->TOVALH) -#define WDOG_TOVALL_REG(base) ((base)->TOVALL) -#define WDOG_WINH_REG(base) ((base)->WINH) -#define WDOG_WINL_REG(base) ((base)->WINL) -#define WDOG_REFRESH_REG(base) ((base)->REFRESH) -#define WDOG_UNLOCK_REG(base) ((base)->UNLOCK) -#define WDOG_TMROUTH_REG(base) ((base)->TMROUTH) -#define WDOG_TMROUTL_REG(base) ((base)->TMROUTL) -#define WDOG_RSTCNT_REG(base) ((base)->RSTCNT) -#define WDOG_PRESC_REG(base) ((base)->PRESC) - -/*! - * @} - */ /* end of group WDOG_Register_Accessor_Macros */ - +} WDOG_Type; /* ---------------------------------------------------------------------------- -- WDOG Register Masks @@ -12370,110 +8366,99 @@ typedef struct { * @{ */ -/* STCTRLH Bit Fields */ -#define WDOG_STCTRLH_WDOGEN_MASK 0x1u -#define WDOG_STCTRLH_WDOGEN_SHIFT 0 -#define WDOG_STCTRLH_WDOGEN_WIDTH 1 -#define WDOG_STCTRLH_WDOGEN(x) (((uint16_t)(((uint16_t)(x))<= 6010050) + #pragma clang system_header + #endif +#elif defined(__IAR_SYSTEMS_ICC__) + #pragma system_include +#endif + +/** + * @brief Mask and left-shift a bit field value for use in a register bit range. + * @param field Name of the register bit field. + * @param value Value of the bit field. + * @return Masked and shifted value. + */ +#define NXP_VAL2FLD(field, value) (((value) << (field ## _SHIFT)) & (field ## _MASK)) +/** + * @brief Mask and right-shift a register value to extract a bit field value. + * @param field Name of the register bit field. + * @param value Value of the register. + * @return Masked and shifted bit field value. + */ +#define NXP_FLD2VAL(field, value) (((value) & (field ## _MASK)) >> (field ## _SHIFT)) + +/*! + * @} + */ /* end of group Bit_Field_Generic_Macros */ + + +/* ---------------------------------------------------------------------------- + -- SDK Compatibility + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup SDK_Compatibility_Symbols SDK Compatibility * @{ */ @@ -12565,77 +8556,31 @@ typedef struct { #define MCG_C2_RANGE0_MASK MCG_C2_RANGE_MASK #define MCG_C2_RANGE0_SHIFT MCG_C2_RANGE_SHIFT #define MCG_C2_RANGE0(x) MCG_C2_RANGE(x) -#define ADC_BASES ADC_BASE_PTRS -#define CMP_BASES CMP_BASE_PTRS -#define CRC_BASES CRC_BASE_PTRS -#define DAC_BASES DAC_BASE_PTRS -#define DMA_BASES DMA_BASE_PTRS -#define DMAMUX_BASES DMAMUX_BASE_PTRS -#define EWM_BASES EWM_BASE_PTRS -#define FMC_BASES FMC_BASE_PTRS -#define FTFA_BASES FTFA_BASE_PTRS -#define FTM_BASES FTM_BASE_PTRS -#define GPIO_BASES GPIO_BASE_PTRS -#define I2C_BASES I2C_BASE_PTRS -#define I2S_BASES I2S_BASE_PTRS -#define LLWU_BASES LLWU_BASE_PTRS -#define LPTMR_BASES LPTMR_BASE_PTRS -#define LPUART_BASES LPUART_BASE_PTRS -#define MCG_BASES MCG_BASE_PTRS -#define MCM_BASES MCM_BASE_PTRS -#define NV_BASES NV_BASE_PTRS -#define OSC_BASES OSC_BASE_PTRS -#define PDB_BASES PDB_BASE_PTRS -#define PIT_BASES PIT_BASE_PTRS -#define PMC_BASES PMC_BASE_PTRS -#define PORT_BASES PORT_BASE_PTRS -#define RCM_BASES RCM_BASE_PTRS -#define RFSYS_BASES RFSYS_BASE_PTRS -#define RFVBAT_BASES RFVBAT_BASE_PTRS -#define RNG_BASES RNG_BASE_PTRS -#define RTC_BASES RTC_BASE_PTRS -#define SIM_BASES SIM_BASE_PTRS -#define SMC_BASES SMC_BASE_PTRS -#define SPI_BASES SPI_BASE_PTRS -#define UART_BASES UART_BASE_PTRS -#define USB_BASES USB_BASE_PTRS -#define VREF_BASES VREF_BASE_PTRS -#define WDOG_BASES WDOG_BASE_PTRS -#define USB_ADDINFO_IRQNUM_MASK This_symbol_has_been_deprecated -#define USB_ADDINFO_IRQNUM_SHIFT This_symbol_has_been_deprecated -#define USB_ADDINFO_IRQNUM(x) This_symbol_has_been_deprecated -#define Watchdog_IRQn WDOG_EWM_IRQn -#define Watchdog_IRQHandler WDOG_EWM_IRQHandler -#define LPTimer_IRQn LPTMR0_IRQn -#define LPTimer_IRQHandler LPTMR0_IRQHandler -#define LLW_IRQn LLWU_IRQn -#define LLW_IRQHandler LLWU_IRQHandler +#define DSPI0 SPI0 +#define DSPI1 SPI1 +#define PTA_BASE GPIOA_BASE +#define PTA GPIOA +#define PTB_BASE GPIOB_BASE +#define PTB GPIOB +#define PTC_BASE GPIOC_BASE +#define PTC GPIOC +#define PTD_BASE GPIOD_BASE +#define PTD GPIOD +#define PTE_BASE GPIOE_BASE +#define PTE GPIOE +#define DMAMUX0 DMAMUX +#define USB_ADDINFO_IRQNUM_MASK This_symbol_has_been_deprecated +#define USB_ADDINFO_IRQNUM_SHIFT This_symbol_has_been_deprecated +#define USB_ADDINFO_IRQNUM(x) This_symbol_has_been_deprecated +#define Watchdog_IRQn WDOG_EWM_IRQn +#define Watchdog_IRQHandler WDOG_EWM_IRQHandler +#define LPTimer_IRQn LPTMR0_IRQn +#define LPTimer_IRQHandler LPTMR0_IRQHandler +#define LLW_IRQn LLWU_IRQn +#define LLW_IRQHandler LLWU_IRQHandler -#define GPIOA_BASE PTA_BASE -#define GPIOB_BASE PTB_BASE -#define GPIOC_BASE PTC_BASE -#define GPIOD_BASE PTD_BASE -#define GPIOE_BASE PTE_BASE -#define GPIOF_BASE PTF_BASE -#define GPIOG_BASE PTG_BASE -#define GPIOA PTA -#define GPIOB PTB -#define GPIOC PTC -#define GPIOD PTD -#define GPIOE PTE -#define GPIOF PTF -#define GPIOG PTG -#define OSC0 OSC /*! * @} - */ /* end of group Backward_Compatibility_Symbols */ + */ /* end of group SDK_Compatibility_Symbols */ - -#else /* #if !defined(MK22F25612_H_) */ - /* There is already included the same memory map. Check if it is compatible (has the same major version) */ - #if (MCU_MEM_MAP_VERSION != 0x0100u) - #if (!defined(MCU_MEM_MAP_SUPPRESS_VERSION_WARNING)) - #warning There are included two not compatible versions of memory maps. Please check possible differences. - #endif /* (!defined(MCU_MEM_MAP_SUPPRESS_VERSION_WARNING)) */ - #endif /* (MCU_MEM_MAP_VERSION != 0x0100u) */ -#endif /* #if !defined(MK22F25612_H_) */ +#endif /* _MK22F25612_H_ */ diff --git a/cpu/k22f/include/vendor/MK22FA12.h b/cpu/k22f/include/vendor/MK22FA12.h index 15ef9fe636..786b09b4be 100644 --- a/cpu/k22f/include/vendor/MK22FA12.h +++ b/cpu/k22f/include/vendor/MK22FA12.h @@ -1,38 +1,38 @@ /* ** ################################################################### ** Processors: MK22FN1M0AVLH12 -** MK22FX512AVLH12 ** MK22FN1M0AVLK12 -** MK22FX512AVLK12 ** MK22FN1M0AVLL12 -** MK22FX512AVLL12 ** MK22FN1M0AVLQ12 -** MK22FX512AVLQ12 ** MK22FN1M0AVMC12 -** MK22FX512AVMC12 ** MK22FN1M0AVMD12 +** MK22FX512AVLH12 +** MK22FX512AVLK12 +** MK22FX512AVLL12 +** MK22FX512AVLQ12 +** MK22FX512AVMC12 ** MK22FX512AVMD12 ** ** Compilers: Keil ARM C/C++ Compiler ** Freescale C/C++ for Embedded ARM ** GNU C Compiler -** GNU C Compiler - CodeSourcery Sourcery G++ ** IAR ANSI C/C++ Compiler for ARM +** MCUXpresso Compiler ** -** Reference manuals: K22P64M120SF5V2RM, Rev.5, March 2015 -** K22P80M120SF5V2RM, Rev.5, March 2015 -** K22P100M120SF5V2RM, Rev.5, March 2015 +** Reference manuals: K22P100M120SF5V2RM, Rev.5, March 2015 +** K22P121M120SF5V2RM, Rev.5, March 2015 ** K22P144M120SF5V2RM, Rev.5, March 2015 +** K22P64M120SF5V2RM, Rev.5, March 2015 +** K22P80M120SF5V2RM, Rev.5, March 2015 ** ** Version: rev. 1.0, 2015-04-07 -** Build: b150408 +** Build: b170112 ** ** Abstract: ** CMSIS Peripheral Access Layer for MK22FA12 ** -** Copyright (c) 1997 - 2015 Freescale Semiconductor, Inc. -** All rights reserved. -** +** Copyright (c) 1997 - 2016 Freescale Semiconductor, Inc. +** Copyright 2016 - 2017 NXP ** Redistribution and use in source and binary forms, with or without modification, ** are permitted provided that the following conditions are met: ** @@ -43,7 +43,7 @@ ** list of conditions and the following disclaimer in the documentation and/or ** other materials provided with the distribution. ** -** o Neither the name of Freescale Semiconductor, Inc. nor the names of its +** o Neither the name of the copyright holder nor the names of its ** contributors may be used to endorse or promote products derived from this ** software without specific prior written permission. ** @@ -58,8 +58,8 @@ ** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ** -** http: www.freescale.com -** mail: support@freescale.com +** http: www.nxp.com +** mail: support@nxp.com ** ** Revisions: ** - rev. 1.0 (2015-04-07) @@ -77,29 +77,14 @@ * CMSIS Peripheral Access Layer for MK22FA12 */ - -/* ---------------------------------------------------------------------------- - -- MCU activation - ---------------------------------------------------------------------------- */ - -/* Prevention from multiple including the same memory map */ -#if !defined(MK22FA12_H_) /* Check if memory map has not been already included */ -#define MK22FA12_H_ -#define MCU_MK22FA12 - -/* Check if another memory map has not been also included */ -#if (defined(MCU_ACTIVE)) - #error MK22FA12 memory map: There is already included another memory map. Only one memory map can be included. -#endif /* (defined(MCU_ACTIVE)) */ -#define MCU_ACTIVE - -#include +#ifndef _MK22FA12_H_ +#define _MK22FA12_H_ /**< Symbol preventing repeated inclusion */ /** Memory map major version (memory maps with equal major version number are * compatible) */ -#define MCU_MEM_MAP_VERSION 0x0100u +#define MCU_MEM_MAP_VERSION 0x0100U /** Memory map minor version */ -#define MCU_MEM_MAP_VERSION_MINOR 0x0000u +#define MCU_MEM_MAP_VERSION_MINOR 0x0000U /** * @brief Macro to calculate address of an aliased word in the peripheral @@ -118,8 +103,8 @@ * @param Bit Bit number to access. * @return Value of the targeted bit in the bit band region. */ -#define BITBAND_REG32(Reg,Bit) (*((uint32_t volatile*)(BITBAND_REGADDR(Reg,Bit)))) -#define BITBAND_REG(Reg,Bit) (BITBAND_REG32(Reg,Bit)) +#define BITBAND_REG32(Reg,Bit) (*((uint32_t volatile*)(BITBAND_REGADDR((Reg),(Bit))))) +#define BITBAND_REG(Reg,Bit) (BITBAND_REG32((Reg),(Bit))) /** * @brief Macro to access a single bit of a peripheral register (bit band region * 0x40000000 to 0x400FFFFF) using the bit-band alias region access. Can @@ -128,7 +113,7 @@ * @param Bit Bit number to access. * @return Value of the targeted bit in the bit band region. */ -#define BITBAND_REG16(Reg,Bit) (*((uint16_t volatile*)(BITBAND_REGADDR(Reg,Bit)))) +#define BITBAND_REG16(Reg,Bit) (*((uint16_t volatile*)(BITBAND_REGADDR((Reg),(Bit))))) /** * @brief Macro to access a single bit of a peripheral register (bit band region * 0x40000000 to 0x400FFFFF) using the bit-band alias region access. Can @@ -137,7 +122,7 @@ * @param Bit Bit number to access. * @return Value of the targeted bit in the bit band region. */ -#define BITBAND_REG8(Reg,Bit) (*((uint8_t volatile*)(BITBAND_REGADDR(Reg,Bit)))) +#define BITBAND_REG8(Reg,Bit) (*((uint8_t volatile*)(BITBAND_REGADDR((Reg),(Bit))))) /* ---------------------------------------------------------------------------- -- Interrupt vector numbers @@ -277,6 +262,110 @@ typedef enum IRQn { */ /* end of group Cortex_Core_Configuration */ +/* ---------------------------------------------------------------------------- + -- Mapping Information + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup Mapping_Information Mapping Information + * @{ + */ + +/** Mapping Information */ +/*! + * @addtogroup edma_request + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! + * @brief Structure for the DMA hardware request + * + * Defines the structure for the DMA hardware request collections. The user can configure the + * hardware request into DMAMUX to trigger the DMA transfer accordingly. The index + * of the hardware request varies according to the to SoC. + */ +typedef enum _dma_request_source +{ + kDmaRequestMux0Disable = 0|0x100U, /**< DMAMUX TriggerDisabled. */ + kDmaRequestMux0Reserved1 = 1|0x100U, /**< Reserved1 */ + kDmaRequestMux0UART0Rx = 2|0x100U, /**< UART0 Receive. */ + kDmaRequestMux0UART0Tx = 3|0x100U, /**< UART0 Transmit. */ + kDmaRequestMux0UART1Rx = 4|0x100U, /**< UART1 Receive. */ + kDmaRequestMux0UART1Tx = 5|0x100U, /**< UART1 Transmit. */ + kDmaRequestMux0UART2Rx = 6|0x100U, /**< UART2 Receive. */ + kDmaRequestMux0UART2Tx = 7|0x100U, /**< UART2 Transmit. */ + kDmaRequestMux0UART3Rx = 8|0x100U, /**< UART3 Receive. */ + kDmaRequestMux0UART3Tx = 9|0x100U, /**< UART3 Transmit. */ + kDmaRequestMux0UART4 = 10|0x100U, /**< UART4 Transmit or Receive. */ + kDmaRequestMux0UART5 = 11|0x100U, /**< UART5 Transmit or Receive. */ + kDmaRequestMux0I2S0Rx = 12|0x100U, /**< I2S0 Receive. */ + kDmaRequestMux0I2S0Tx = 13|0x100U, /**< I2S0 Transmit. */ + kDmaRequestMux0SPI0Rx = 14|0x100U, /**< SPI0 Receive. */ + kDmaRequestMux0SPI0Tx = 15|0x100U, /**< SPI0 Transmit. */ + kDmaRequestMux0SPI1 = 16|0x100U, /**< SPI1 Transmit or Receive. */ + kDmaRequestMux0SPI2 = 17|0x100U, /**< SPI2 Transmit or Receive. */ + kDmaRequestMux0I2C0 = 18|0x100U, /**< I2C0. */ + kDmaRequestMux0I2C1I2C2 = 19|0x100U, /**< I2C1 and I2C2. */ + kDmaRequestMux0I2C1 = 19|0x100U, /**< I2C1 and I2C2. */ + kDmaRequestMux0I2C2 = 19|0x100U, /**< I2C1 and I2C2. */ + kDmaRequestMux0FTM0Channel0 = 20|0x100U, /**< FTM0 C0V. */ + kDmaRequestMux0FTM0Channel1 = 21|0x100U, /**< FTM0 C1V. */ + kDmaRequestMux0FTM0Channel2 = 22|0x100U, /**< FTM0 C2V. */ + kDmaRequestMux0FTM0Channel3 = 23|0x100U, /**< FTM0 C3V. */ + kDmaRequestMux0FTM0Channel4 = 24|0x100U, /**< FTM0 C4V. */ + kDmaRequestMux0FTM0Channel5 = 25|0x100U, /**< FTM0 C5V. */ + kDmaRequestMux0FTM0Channel6 = 26|0x100U, /**< FTM0 C6V. */ + kDmaRequestMux0FTM0Channel7 = 27|0x100U, /**< FTM0 C7V. */ + kDmaRequestMux0FTM1Channel0 = 28|0x100U, /**< FTM1 C0V. */ + kDmaRequestMux0FTM1Channel1 = 29|0x100U, /**< FTM1 C1V. */ + kDmaRequestMux0FTM2Channel0 = 30|0x100U, /**< FTM2 C0V. */ + kDmaRequestMux0FTM2Channel1 = 31|0x100U, /**< FTM2 C1V. */ + kDmaRequestMux0FTM3Channel0 = 32|0x100U, /**< FTM3 C0V. */ + kDmaRequestMux0FTM3Channel1 = 33|0x100U, /**< FTM3 C1V. */ + kDmaRequestMux0FTM3Channel2 = 34|0x100U, /**< FTM3 C2V. */ + kDmaRequestMux0FTM3Channel3 = 35|0x100U, /**< FTM3 C3V. */ + kDmaRequestMux0FTM3Channel4 = 36|0x100U, /**< FTM3 C4V. */ + kDmaRequestMux0FTM3Channel5 = 37|0x100U, /**< FTM3 C5V. */ + kDmaRequestMux0FTM3Channel6 = 38|0x100U, /**< FTM3 C6V. */ + kDmaRequestMux0FTM3Channel7 = 39|0x100U, /**< FTM3 C7V. */ + kDmaRequestMux0ADC0 = 40|0x100U, /**< ADC0. */ + kDmaRequestMux0ADC1 = 41|0x100U, /**< ADC1. */ + kDmaRequestMux0CMP0 = 42|0x100U, /**< CMP0. */ + kDmaRequestMux0CMP1 = 43|0x100U, /**< CMP1. */ + kDmaRequestMux0CMP2 = 44|0x100U, /**< CMP2. */ + kDmaRequestMux0DAC0 = 45|0x100U, /**< DAC0. */ + kDmaRequestMux0DAC1 = 46|0x100U, /**< DAC1. */ + kDmaRequestMux0CMT = 47|0x100U, /**< CMT. */ + kDmaRequestMux0PDB = 48|0x100U, /**< PDB0. */ + kDmaRequestMux0PortA = 49|0x100U, /**< PTA. */ + kDmaRequestMux0PortB = 50|0x100U, /**< PTB. */ + kDmaRequestMux0PortC = 51|0x100U, /**< PTC. */ + kDmaRequestMux0PortD = 52|0x100U, /**< PTD. */ + kDmaRequestMux0PortE = 53|0x100U, /**< PTE. */ + kDmaRequestMux0AlwaysOn54 = 54|0x100U, /**< DMAMUX Always Enabled slot. */ + kDmaRequestMux0AlwaysOn55 = 55|0x100U, /**< DMAMUX Always Enabled slot. */ + kDmaRequestMux0AlwaysOn56 = 56|0x100U, /**< DMAMUX Always Enabled slot. */ + kDmaRequestMux0AlwaysOn57 = 57|0x100U, /**< DMAMUX Always Enabled slot. */ + kDmaRequestMux0AlwaysOn58 = 58|0x100U, /**< DMAMUX Always Enabled slot. */ + kDmaRequestMux0AlwaysOn59 = 59|0x100U, /**< DMAMUX Always Enabled slot. */ + kDmaRequestMux0AlwaysOn60 = 60|0x100U, /**< DMAMUX Always Enabled slot. */ + kDmaRequestMux0AlwaysOn61 = 61|0x100U, /**< DMAMUX Always Enabled slot. */ + kDmaRequestMux0AlwaysOn62 = 62|0x100U, /**< DMAMUX Always Enabled slot. */ + kDmaRequestMux0AlwaysOn63 = 63|0x100U, /**< DMAMUX Always Enabled slot. */ +} dma_request_source_t; + +/* @} */ + + +/*! + * @} + */ /* end of group Mapping_Information */ + + /* ---------------------------------------------------------------------------- -- Device Peripheral Access Layer ---------------------------------------------------------------------------- */ @@ -342,51 +431,7 @@ typedef struct { __IO uint32_t CLM2; /**< ADC Minus-Side General Calibration Value Register, offset: 0x64 */ __IO uint32_t CLM1; /**< ADC Minus-Side General Calibration Value Register, offset: 0x68 */ __IO uint32_t CLM0; /**< ADC Minus-Side General Calibration Value Register, offset: 0x6C */ -} ADC_Type, *ADC_MemMapPtr; - -/* ---------------------------------------------------------------------------- - -- ADC - Register accessor macros - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup ADC_Register_Accessor_Macros ADC - Register accessor macros - * @{ - */ - - -/* ADC - Register accessors */ -#define ADC_SC1_REG(base,index) ((base)->SC1[index]) -#define ADC_SC1_COUNT 2 -#define ADC_CFG1_REG(base) ((base)->CFG1) -#define ADC_CFG2_REG(base) ((base)->CFG2) -#define ADC_R_REG(base,index) ((base)->R[index]) -#define ADC_R_COUNT 2 -#define ADC_CV1_REG(base) ((base)->CV1) -#define ADC_CV2_REG(base) ((base)->CV2) -#define ADC_SC2_REG(base) ((base)->SC2) -#define ADC_SC3_REG(base) ((base)->SC3) -#define ADC_OFS_REG(base) ((base)->OFS) -#define ADC_PG_REG(base) ((base)->PG) -#define ADC_MG_REG(base) ((base)->MG) -#define ADC_CLPD_REG(base) ((base)->CLPD) -#define ADC_CLPS_REG(base) ((base)->CLPS) -#define ADC_CLP4_REG(base) ((base)->CLP4) -#define ADC_CLP3_REG(base) ((base)->CLP3) -#define ADC_CLP2_REG(base) ((base)->CLP2) -#define ADC_CLP1_REG(base) ((base)->CLP1) -#define ADC_CLP0_REG(base) ((base)->CLP0) -#define ADC_CLMD_REG(base) ((base)->CLMD) -#define ADC_CLMS_REG(base) ((base)->CLMS) -#define ADC_CLM4_REG(base) ((base)->CLM4) -#define ADC_CLM3_REG(base) ((base)->CLM3) -#define ADC_CLM2_REG(base) ((base)->CLM2) -#define ADC_CLM1_REG(base) ((base)->CLM1) -#define ADC_CLM0_REG(base) ((base)->CLM0) - -/*! - * @} - */ /* end of group ADC_Register_Accessor_Macros */ - +} ADC_Type; /* ---------------------------------------------------------------------------- -- ADC Register Masks @@ -397,211 +442,197 @@ typedef struct { * @{ */ -/* SC1 Bit Fields */ -#define ADC_SC1_ADCH_MASK 0x1Fu -#define ADC_SC1_ADCH_SHIFT 0 -#define ADC_SC1_ADCH_WIDTH 5 -#define ADC_SC1_ADCH(x) (((uint32_t)(((uint32_t)(x))<MPRA) -#define AIPS_PACRA_REG(base) ((base)->PACRA) -#define AIPS_PACRB_REG(base) ((base)->PACRB) -#define AIPS_PACRC_REG(base) ((base)->PACRC) -#define AIPS_PACRD_REG(base) ((base)->PACRD) -#define AIPS_PACRE_REG(base) ((base)->PACRE) -#define AIPS_PACRF_REG(base) ((base)->PACRF) -#define AIPS_PACRG_REG(base) ((base)->PACRG) -#define AIPS_PACRH_REG(base) ((base)->PACRH) -#define AIPS_PACRI_REG(base) ((base)->PACRI) -#define AIPS_PACRJ_REG(base) ((base)->PACRJ) -#define AIPS_PACRK_REG(base) ((base)->PACRK) -#define AIPS_PACRL_REG(base) ((base)->PACRL) -#define AIPS_PACRM_REG(base) ((base)->PACRM) -#define AIPS_PACRN_REG(base) ((base)->PACRN) -#define AIPS_PACRO_REG(base) ((base)->PACRO) -#define AIPS_PACRP_REG(base) ((base)->PACRP) - -/*! - * @} - */ /* end of group AIPS_Register_Accessor_Macros */ - +} AIPS_Type; /* ---------------------------------------------------------------------------- -- AIPS Register Masks @@ -785,1558 +701,1190 @@ typedef struct { * @{ */ -/* PACRA Bit Fields */ -#define AIPS_PACRA_TP7_MASK 0x1u -#define AIPS_PACRA_TP7_SHIFT 0 -#define AIPS_PACRA_TP7_WIDTH 1 -#define AIPS_PACRA_TP7(x) (((uint32_t)(((uint32_t)(x))<SLAVE[index].PRS) -#define AXBS_PRS_COUNT 5 -#define AXBS_CRS_REG(base,index) ((base)->SLAVE[index].CRS) -#define AXBS_CRS_COUNT 5 -#define AXBS_MGPCR0_REG(base) ((base)->MGPCR0) -#define AXBS_MGPCR1_REG(base) ((base)->MGPCR1) -#define AXBS_MGPCR2_REG(base) ((base)->MGPCR2) -#define AXBS_MGPCR4_REG(base) ((base)->MGPCR4) -#define AXBS_MGPCR5_REG(base) ((base)->MGPCR5) - -/*! - * @} - */ /* end of group AXBS_Register_Accessor_Macros */ - +} AXBS_Type; /* ---------------------------------------------------------------------------- -- AXBS Register Masks @@ -2481,73 +1948,71 @@ typedef struct { * @{ */ -/* PRS Bit Fields */ -#define AXBS_PRS_M0_MASK 0x7u -#define AXBS_PRS_M0_SHIFT 0 -#define AXBS_PRS_M0_WIDTH 3 -#define AXBS_PRS_M0(x) (((uint32_t)(((uint32_t)(x))<MCR) -#define CAN_CTRL1_REG(base) ((base)->CTRL1) -#define CAN_TIMER_REG(base) ((base)->TIMER) -#define CAN_RXMGMASK_REG(base) ((base)->RXMGMASK) -#define CAN_RX14MASK_REG(base) ((base)->RX14MASK) -#define CAN_RX15MASK_REG(base) ((base)->RX15MASK) -#define CAN_ECR_REG(base) ((base)->ECR) -#define CAN_ESR1_REG(base) ((base)->ESR1) -#define CAN_IMASK1_REG(base) ((base)->IMASK1) -#define CAN_IFLAG1_REG(base) ((base)->IFLAG1) -#define CAN_CTRL2_REG(base) ((base)->CTRL2) -#define CAN_ESR2_REG(base) ((base)->ESR2) -#define CAN_CRCR_REG(base) ((base)->CRCR) -#define CAN_RXFGMASK_REG(base) ((base)->RXFGMASK) -#define CAN_RXFIR_REG(base) ((base)->RXFIR) -#define CAN_CS_REG(base,index) ((base)->MB[index].CS) -#define CAN_CS_COUNT 16 -#define CAN_ID_REG(base,index) ((base)->MB[index].ID) -#define CAN_ID_COUNT 16 -#define CAN_WORD0_REG(base,index) ((base)->MB[index].WORD0) -#define CAN_WORD0_COUNT 16 -#define CAN_WORD1_REG(base,index) ((base)->MB[index].WORD1) -#define CAN_WORD1_COUNT 16 -#define CAN_RXIMR_REG(base,index) ((base)->RXIMR[index]) -#define CAN_RXIMR_COUNT 16 - -/*! - * @} - */ /* end of group CAN_Register_Accessor_Macros */ - +} CAN_Type; /* ---------------------------------------------------------------------------- -- CAN Register Masks @@ -2699,414 +2084,352 @@ typedef struct { * @{ */ -/* MCR Bit Fields */ -#define CAN_MCR_MAXMB_MASK 0x7Fu -#define CAN_MCR_MAXMB_SHIFT 0 -#define CAN_MCR_MAXMB_WIDTH 7 -#define CAN_MCR_MAXMB(x) (((uint32_t)(((uint32_t)(x))<CR0) -#define CMP_CR1_REG(base) ((base)->CR1) -#define CMP_FPR_REG(base) ((base)->FPR) -#define CMP_SCR_REG(base) ((base)->SCR) -#define CMP_DACCR_REG(base) ((base)->DACCR) -#define CMP_MUXCR_REG(base) ((base)->MUXCR) - -/*! - * @} - */ /* end of group CMP_Register_Accessor_Macros */ - +} CMP_Type; /* ---------------------------------------------------------------------------- -- CMP Register Masks @@ -3307,100 +2486,84 @@ typedef struct { * @{ */ -/* CR0 Bit Fields */ -#define CMP_CR0_HYSTCTR_MASK 0x3u -#define CMP_CR0_HYSTCTR_SHIFT 0 -#define CMP_CR0_HYSTCTR_WIDTH 2 -#define CMP_CR0_HYSTCTR(x) (((uint8_t)(((uint8_t)(x))<CGH1) -#define CMT_CGL1_REG(base) ((base)->CGL1) -#define CMT_CGH2_REG(base) ((base)->CGH2) -#define CMT_CGL2_REG(base) ((base)->CGL2) -#define CMT_OC_REG(base) ((base)->OC) -#define CMT_MSC_REG(base) ((base)->MSC) -#define CMT_CMD1_REG(base) ((base)->CMD1) -#define CMT_CMD2_REG(base) ((base)->CMD2) -#define CMT_CMD3_REG(base) ((base)->CMD3) -#define CMT_CMD4_REG(base) ((base)->CMD4) -#define CMT_PPS_REG(base) ((base)->PPS) -#define CMT_DMA_REG(base) ((base)->DMA) - -/*! - * @} - */ /* end of group CMT_Register_Accessor_Macros */ - +} CMT_Type; /* ---------------------------------------------------------------------------- -- CMT Register Masks @@ -3536,98 +2629,90 @@ typedef struct { * @{ */ -/* CGH1 Bit Fields */ -#define CMT_CGH1_PH_MASK 0xFFu -#define CMT_CGH1_PH_SHIFT 0 -#define CMT_CGH1_PH_WIDTH 8 -#define CMT_CGH1_PH(x) (((uint8_t)(((uint8_t)(x))<ACCESS16BIT.DATAL) -#define CRC_DATAH_REG(base) ((base)->ACCESS16BIT.DATAH) -#define CRC_DATA_REG(base) ((base)->DATA) -#define CRC_DATALL_REG(base) ((base)->ACCESS8BIT.DATALL) -#define CRC_DATALU_REG(base) ((base)->ACCESS8BIT.DATALU) -#define CRC_DATAHL_REG(base) ((base)->ACCESS8BIT.DATAHL) -#define CRC_DATAHU_REG(base) ((base)->ACCESS8BIT.DATAHU) -#define CRC_GPOLYL_REG(base) ((base)->GPOLY_ACCESS16BIT.GPOLYL) -#define CRC_GPOLYH_REG(base) ((base)->GPOLY_ACCESS16BIT.GPOLYH) -#define CRC_GPOLY_REG(base) ((base)->GPOLY) -#define CRC_GPOLYLL_REG(base) ((base)->GPOLY_ACCESS8BIT.GPOLYLL) -#define CRC_GPOLYLU_REG(base) ((base)->GPOLY_ACCESS8BIT.GPOLYLU) -#define CRC_GPOLYHL_REG(base) ((base)->GPOLY_ACCESS8BIT.GPOLYHL) -#define CRC_GPOLYHU_REG(base) ((base)->GPOLY_ACCESS8BIT.GPOLYHU) -#define CRC_CTRL_REG(base) ((base)->CTRL) -#define CRC_CTRLHU_REG(base) ((base)->CTRL_ACCESS8BIT.CTRLHU) - -/*! - * @} - */ /* end of group CRC_Register_Accessor_Macros */ - +} CRC_Type; /* ---------------------------------------------------------------------------- -- CRC Register Masks @@ -3770,134 +2791,122 @@ typedef struct { * @{ */ -/* DATAL Bit Fields */ -#define CRC_DATAL_DATAL_MASK 0xFFFFu -#define CRC_DATAL_DATAL_SHIFT 0 -#define CRC_DATAL_DATAL_WIDTH 16 -#define CRC_DATAL_DATAL(x) (((uint16_t)(((uint16_t)(x))<DAT[index].DATL) -#define DAC_DATL_COUNT 16 -#define DAC_DATH_REG(base,index) ((base)->DAT[index].DATH) -#define DAC_DATH_COUNT 16 -#define DAC_SR_REG(base) ((base)->SR) -#define DAC_C0_REG(base) ((base)->C0) -#define DAC_C1_REG(base) ((base)->C1) -#define DAC_C2_REG(base) ((base)->C2) - -/*! - * @} - */ /* end of group DAC_Register_Accessor_Macros */ - +} DAC_Type; /* ---------------------------------------------------------------------------- -- DAC Register Masks @@ -4009,88 +2958,81 @@ typedef struct { * @{ */ -/* DATL Bit Fields */ -#define DAC_DATL_DATA0_MASK 0xFFu -#define DAC_DATL_DATA0_SHIFT 0 -#define DAC_DATL_DATA0_WIDTH 8 -#define DAC_DATL_DATA0(x) (((uint8_t)(((uint8_t)(x))<CR) -#define DMA_ES_REG(base) ((base)->ES) -#define DMA_ERQ_REG(base) ((base)->ERQ) -#define DMA_EEI_REG(base) ((base)->EEI) -#define DMA_CEEI_REG(base) ((base)->CEEI) -#define DMA_SEEI_REG(base) ((base)->SEEI) -#define DMA_CERQ_REG(base) ((base)->CERQ) -#define DMA_SERQ_REG(base) ((base)->SERQ) -#define DMA_CDNE_REG(base) ((base)->CDNE) -#define DMA_SSRT_REG(base) ((base)->SSRT) -#define DMA_CERR_REG(base) ((base)->CERR) -#define DMA_CINT_REG(base) ((base)->CINT) -#define DMA_INT_REG(base) ((base)->INT) -#define DMA_ERR_REG(base) ((base)->ERR) -#define DMA_HRS_REG(base) ((base)->HRS) -#define DMA_DCHPRI3_REG(base) ((base)->DCHPRI3) -#define DMA_DCHPRI2_REG(base) ((base)->DCHPRI2) -#define DMA_DCHPRI1_REG(base) ((base)->DCHPRI1) -#define DMA_DCHPRI0_REG(base) ((base)->DCHPRI0) -#define DMA_DCHPRI7_REG(base) ((base)->DCHPRI7) -#define DMA_DCHPRI6_REG(base) ((base)->DCHPRI6) -#define DMA_DCHPRI5_REG(base) ((base)->DCHPRI5) -#define DMA_DCHPRI4_REG(base) ((base)->DCHPRI4) -#define DMA_DCHPRI11_REG(base) ((base)->DCHPRI11) -#define DMA_DCHPRI10_REG(base) ((base)->DCHPRI10) -#define DMA_DCHPRI9_REG(base) ((base)->DCHPRI9) -#define DMA_DCHPRI8_REG(base) ((base)->DCHPRI8) -#define DMA_DCHPRI15_REG(base) ((base)->DCHPRI15) -#define DMA_DCHPRI14_REG(base) ((base)->DCHPRI14) -#define DMA_DCHPRI13_REG(base) ((base)->DCHPRI13) -#define DMA_DCHPRI12_REG(base) ((base)->DCHPRI12) -#define DMA_SADDR_REG(base,index) ((base)->TCD[index].SADDR) -#define DMA_SADDR_COUNT 16 -#define DMA_SOFF_REG(base,index) ((base)->TCD[index].SOFF) -#define DMA_SOFF_COUNT 16 -#define DMA_ATTR_REG(base,index) ((base)->TCD[index].ATTR) -#define DMA_ATTR_COUNT 16 -#define DMA_NBYTES_MLNO_REG(base,index) ((base)->TCD[index].NBYTES_MLNO) -#define DMA_NBYTES_MLNO_COUNT 16 -#define DMA_NBYTES_MLOFFNO_REG(base,index) ((base)->TCD[index].NBYTES_MLOFFNO) -#define DMA_NBYTES_MLOFFNO_COUNT 16 -#define DMA_NBYTES_MLOFFYES_REG(base,index) ((base)->TCD[index].NBYTES_MLOFFYES) -#define DMA_NBYTES_MLOFFYES_COUNT 16 -#define DMA_SLAST_REG(base,index) ((base)->TCD[index].SLAST) -#define DMA_SLAST_COUNT 16 -#define DMA_DADDR_REG(base,index) ((base)->TCD[index].DADDR) -#define DMA_DADDR_COUNT 16 -#define DMA_DOFF_REG(base,index) ((base)->TCD[index].DOFF) -#define DMA_DOFF_COUNT 16 -#define DMA_CITER_ELINKNO_REG(base,index) ((base)->TCD[index].CITER_ELINKNO) -#define DMA_CITER_ELINKNO_COUNT 16 -#define DMA_CITER_ELINKYES_REG(base,index) ((base)->TCD[index].CITER_ELINKYES) -#define DMA_CITER_ELINKYES_COUNT 16 -#define DMA_DLAST_SGA_REG(base,index) ((base)->TCD[index].DLAST_SGA) -#define DMA_DLAST_SGA_COUNT 16 -#define DMA_CSR_REG(base,index) ((base)->TCD[index].CSR) -#define DMA_CSR_COUNT 16 -#define DMA_BITER_ELINKNO_REG(base,index) ((base)->TCD[index].BITER_ELINKNO) -#define DMA_BITER_ELINKNO_COUNT 16 -#define DMA_BITER_ELINKYES_REG(base,index) ((base)->TCD[index].BITER_ELINKYES) -#define DMA_BITER_ELINKYES_COUNT 16 - -/*! - * @} - */ /* end of group DMA_Register_Accessor_Macros */ - +} DMA_Type; /* ---------------------------------------------------------------------------- -- DMA Register Masks @@ -4378,892 +3143,773 @@ typedef struct { * @{ */ -/* CR Bit Fields */ -#define DMA_CR_EDBG_MASK 0x2u -#define DMA_CR_EDBG_SHIFT 1 -#define DMA_CR_EDBG_WIDTH 1 -#define DMA_CR_EDBG(x) (((uint32_t)(((uint32_t)(x))<CHCFG[index]) -#define DMAMUX_CHCFG_COUNT 16 - -/*! - * @} - */ /* end of group DMAMUX_Register_Accessor_Macros */ - +} DMAMUX_Type; /* ---------------------------------------------------------------------------- -- DMAMUX Register Masks @@ -5637,19 +3957,20 @@ typedef struct { * @{ */ -/* CHCFG Bit Fields */ -#define DMAMUX_CHCFG_SOURCE_MASK 0x3Fu -#define DMAMUX_CHCFG_SOURCE_SHIFT 0 -#define DMAMUX_CHCFG_SOURCE_WIDTH 6 -#define DMAMUX_CHCFG_SOURCE(x) (((uint8_t)(((uint8_t)(x))<CTRL) -#define EWM_SERV_REG(base) ((base)->SERV) -#define EWM_CMPL_REG(base) ((base)->CMPL) -#define EWM_CMPH_REG(base) ((base)->CMPH) - -/*! - * @} - */ /* end of group EWM_Register_Accessor_Macros */ - +} EWM_Type; /* ---------------------------------------------------------------------------- -- EWM Register Masks @@ -5756,38 +4018,35 @@ typedef struct { * @{ */ -/* CTRL Bit Fields */ -#define EWM_CTRL_EWMEN_MASK 0x1u -#define EWM_CTRL_EWMEN_SHIFT 0 -#define EWM_CTRL_EWMEN_WIDTH 1 -#define EWM_CTRL_EWMEN(x) (((uint8_t)(((uint8_t)(x))<CS[index].CSAR) -#define FB_CSAR_COUNT 6 -#define FB_CSMR_REG(base,index) ((base)->CS[index].CSMR) -#define FB_CSMR_COUNT 6 -#define FB_CSCR_REG(base,index) ((base)->CS[index].CSCR) -#define FB_CSCR_COUNT 6 -#define FB_CSPMCR_REG(base) ((base)->CSPMCR) - -/*! - * @} - */ /* end of group FB_Register_Accessor_Macros */ - +} FB_Type; /* ---------------------------------------------------------------------------- -- FB Register Masks @@ -5887,98 +4099,89 @@ typedef struct { * @{ */ -/* CSAR Bit Fields */ -#define FB_CSAR_BA_MASK 0xFFFF0000u -#define FB_CSAR_BA_SHIFT 16 -#define FB_CSAR_BA_WIDTH 16 -#define FB_CSAR_BA(x) (((uint32_t)(((uint32_t)(x))<PFAPR) -#define FMC_PFB0CR_REG(base) ((base)->PFB0CR) -#define FMC_PFB1CR_REG(base) ((base)->PFB1CR) -#define FMC_TAGVDW0S_REG(base,index) ((base)->TAGVDW0S[index]) -#define FMC_TAGVDW0S_COUNT 4 -#define FMC_TAGVDW1S_REG(base,index) ((base)->TAGVDW1S[index]) -#define FMC_TAGVDW1S_COUNT 4 -#define FMC_TAGVDW2S_REG(base,index) ((base)->TAGVDW2S[index]) -#define FMC_TAGVDW2S_COUNT 4 -#define FMC_TAGVDW3S_REG(base,index) ((base)->TAGVDW3S[index]) -#define FMC_TAGVDW3S_COUNT 4 -#define FMC_DATA_UM_REG(base,index,index2) ((base)->SET[index][index2].DATA_UM) -#define FMC_DATA_UM_COUNT 4 -#define FMC_DATA_UM_COUNT2 4 -#define FMC_DATA_MU_REG(base,index,index2) ((base)->SET[index][index2].DATA_MU) -#define FMC_DATA_MU_COUNT 4 -#define FMC_DATA_MU_COUNT2 4 -#define FMC_DATA_ML_REG(base,index,index2) ((base)->SET[index][index2].DATA_ML) -#define FMC_DATA_ML_COUNT 4 -#define FMC_DATA_ML_COUNT2 4 -#define FMC_DATA_LM_REG(base,index,index2) ((base)->SET[index][index2].DATA_LM) -#define FMC_DATA_LM_COUNT 4 -#define FMC_DATA_LM_COUNT2 4 - -/*! - * @} - */ /* end of group FMC_Register_Accessor_Macros */ - +} FMC_Type; /* ---------------------------------------------------------------------------- -- FMC Register Masks @@ -6120,201 +4240,202 @@ typedef struct { * @{ */ -/* PFAPR Bit Fields */ -#define FMC_PFAPR_M0AP_MASK 0x3u -#define FMC_PFAPR_M0AP_SHIFT 0 -#define FMC_PFAPR_M0AP_WIDTH 2 -#define FMC_PFAPR_M0AP(x) (((uint32_t)(((uint32_t)(x))<FSTAT) -#define FTFE_FCNFG_REG(base) ((base)->FCNFG) -#define FTFE_FSEC_REG(base) ((base)->FSEC) -#define FTFE_FOPT_REG(base) ((base)->FOPT) -#define FTFE_FCCOB3_REG(base) ((base)->FCCOB3) -#define FTFE_FCCOB2_REG(base) ((base)->FCCOB2) -#define FTFE_FCCOB1_REG(base) ((base)->FCCOB1) -#define FTFE_FCCOB0_REG(base) ((base)->FCCOB0) -#define FTFE_FCCOB7_REG(base) ((base)->FCCOB7) -#define FTFE_FCCOB6_REG(base) ((base)->FCCOB6) -#define FTFE_FCCOB5_REG(base) ((base)->FCCOB5) -#define FTFE_FCCOB4_REG(base) ((base)->FCCOB4) -#define FTFE_FCCOBB_REG(base) ((base)->FCCOBB) -#define FTFE_FCCOBA_REG(base) ((base)->FCCOBA) -#define FTFE_FCCOB9_REG(base) ((base)->FCCOB9) -#define FTFE_FCCOB8_REG(base) ((base)->FCCOB8) -#define FTFE_FPROT3_REG(base) ((base)->FPROT3) -#define FTFE_FPROT2_REG(base) ((base)->FPROT2) -#define FTFE_FPROT1_REG(base) ((base)->FPROT1) -#define FTFE_FPROT0_REG(base) ((base)->FPROT0) -#define FTFE_FEPROT_REG(base) ((base)->FEPROT) -#define FTFE_FDPROT_REG(base) ((base)->FDPROT) - -/*! - * @} - */ /* end of group FTFE_Register_Accessor_Macros */ - +} FTFE_Type; /* ---------------------------------------------------------------------------- -- FTFE Register Masks @@ -6532,172 +4502,158 @@ typedef struct { * @{ */ -/* FSTAT Bit Fields */ -#define FTFE_FSTAT_MGSTAT0_MASK 0x1u -#define FTFE_FSTAT_MGSTAT0_SHIFT 0 -#define FTFE_FSTAT_MGSTAT0_WIDTH 1 -#define FTFE_FSTAT_MGSTAT0(x) (((uint8_t)(((uint8_t)(x))<SC) -#define FTM_CNT_REG(base) ((base)->CNT) -#define FTM_MOD_REG(base) ((base)->MOD) -#define FTM_CnSC_REG(base,index) ((base)->CONTROLS[index].CnSC) -#define FTM_CnSC_COUNT 8 -#define FTM_CnV_REG(base,index) ((base)->CONTROLS[index].CnV) -#define FTM_CnV_COUNT 8 -#define FTM_CNTIN_REG(base) ((base)->CNTIN) -#define FTM_STATUS_REG(base) ((base)->STATUS) -#define FTM_MODE_REG(base) ((base)->MODE) -#define FTM_SYNC_REG(base) ((base)->SYNC) -#define FTM_OUTINIT_REG(base) ((base)->OUTINIT) -#define FTM_OUTMASK_REG(base) ((base)->OUTMASK) -#define FTM_COMBINE_REG(base) ((base)->COMBINE) -#define FTM_DEADTIME_REG(base) ((base)->DEADTIME) -#define FTM_EXTTRIG_REG(base) ((base)->EXTTRIG) -#define FTM_POL_REG(base) ((base)->POL) -#define FTM_FMS_REG(base) ((base)->FMS) -#define FTM_FILTER_REG(base) ((base)->FILTER) -#define FTM_FLTCTRL_REG(base) ((base)->FLTCTRL) -#define FTM_QDCTRL_REG(base) ((base)->QDCTRL) -#define FTM_CONF_REG(base) ((base)->CONF) -#define FTM_FLTPOL_REG(base) ((base)->FLTPOL) -#define FTM_SYNCONF_REG(base) ((base)->SYNCONF) -#define FTM_INVCTRL_REG(base) ((base)->INVCTRL) -#define FTM_SWOCTRL_REG(base) ((base)->SWOCTRL) -#define FTM_PWMLOAD_REG(base) ((base)->PWMLOAD) - -/*! - * @} - */ /* end of group FTM_Register_Accessor_Macros */ - +} FTM_Type; /* ---------------------------------------------------------------------------- -- FTM Register Masks @@ -6856,755 +4727,605 @@ typedef struct { * @{ */ -/* SC Bit Fields */ -#define FTM_SC_PS_MASK 0x7u -#define FTM_SC_PS_SHIFT 0 -#define FTM_SC_PS_WIDTH 3 -#define FTM_SC_PS(x) (((uint32_t)(((uint32_t)(x))<PDOR) -#define GPIO_PSOR_REG(base) ((base)->PSOR) -#define GPIO_PCOR_REG(base) ((base)->PCOR) -#define GPIO_PTOR_REG(base) ((base)->PTOR) -#define GPIO_PDIR_REG(base) ((base)->PDIR) -#define GPIO_PDDR_REG(base) ((base)->PDDR) - -/*! - * @} - */ /* end of group GPIO_Register_Accessor_Macros */ - +} GPIO_Type; /* ---------------------------------------------------------------------------- -- GPIO Register Masks @@ -7858,36 +5389,36 @@ typedef struct { * @{ */ -/* PDOR Bit Fields */ -#define GPIO_PDOR_PDO_MASK 0xFFFFFFFFu -#define GPIO_PDOR_PDO_SHIFT 0 -#define GPIO_PDOR_PDO_WIDTH 32 -#define GPIO_PDOR_PDO(x) (((uint32_t)(((uint32_t)(x))<A1) -#define I2C_F_REG(base) ((base)->F) -#define I2C_C1_REG(base) ((base)->C1) -#define I2C_S_REG(base) ((base)->S) -#define I2C_D_REG(base) ((base)->D) -#define I2C_C2_REG(base) ((base)->C2) -#define I2C_FLT_REG(base) ((base)->FLT) -#define I2C_RA_REG(base) ((base)->RA) -#define I2C_SMB_REG(base) ((base)->SMB) -#define I2C_A2_REG(base) ((base)->A2) -#define I2C_SLTH_REG(base) ((base)->SLTH) -#define I2C_SLTL_REG(base) ((base)->SLTL) - -/*! - * @} - */ /* end of group I2C_Register_Accessor_Macros */ - +} I2C_Type; /* ---------------------------------------------------------------------------- -- I2C Register Masks @@ -8045,190 +5490,159 @@ typedef struct { * @{ */ -/* A1 Bit Fields */ -#define I2C_A1_AD_MASK 0xFEu -#define I2C_A1_AD_SHIFT 1 -#define I2C_A1_AD_WIDTH 7 -#define I2C_A1_AD(x) (((uint8_t)(((uint8_t)(x))<TCSR) -#define I2S_TCR1_REG(base) ((base)->TCR1) -#define I2S_TCR2_REG(base) ((base)->TCR2) -#define I2S_TCR3_REG(base) ((base)->TCR3) -#define I2S_TCR4_REG(base) ((base)->TCR4) -#define I2S_TCR5_REG(base) ((base)->TCR5) -#define I2S_TDR_REG(base,index) ((base)->TDR[index]) -#define I2S_TDR_COUNT 2 -#define I2S_TFR_REG(base,index) ((base)->TFR[index]) -#define I2S_TFR_COUNT 2 -#define I2S_TMR_REG(base) ((base)->TMR) -#define I2S_RCSR_REG(base) ((base)->RCSR) -#define I2S_RCR1_REG(base) ((base)->RCR1) -#define I2S_RCR2_REG(base) ((base)->RCR2) -#define I2S_RCR3_REG(base) ((base)->RCR3) -#define I2S_RCR4_REG(base) ((base)->RCR4) -#define I2S_RCR5_REG(base) ((base)->RCR5) -#define I2S_RDR_REG(base,index) ((base)->RDR[index]) -#define I2S_RDR_COUNT 2 -#define I2S_RFR_REG(base,index) ((base)->RFR[index]) -#define I2S_RFR_COUNT 2 -#define I2S_RMR_REG(base) ((base)->RMR) -#define I2S_MCR_REG(base) ((base)->MCR) -#define I2S_MDR_REG(base) ((base)->MDR) - -/*! - * @} - */ /* end of group I2S_Register_Accessor_Macros */ - +} I2S_Type; /* ---------------------------------------------------------------------------- -- I2S Register Masks @@ -8410,374 +5724,319 @@ typedef struct { * @{ */ -/* TCSR Bit Fields */ -#define I2S_TCSR_FRDE_MASK 0x1u -#define I2S_TCSR_FRDE_SHIFT 0 -#define I2S_TCSR_FRDE_WIDTH 1 -#define I2S_TCSR_FRDE(x) (((uint32_t)(((uint32_t)(x))<PE1) -#define LLWU_PE2_REG(base) ((base)->PE2) -#define LLWU_PE3_REG(base) ((base)->PE3) -#define LLWU_PE4_REG(base) ((base)->PE4) -#define LLWU_ME_REG(base) ((base)->ME) -#define LLWU_F1_REG(base) ((base)->F1) -#define LLWU_F2_REG(base) ((base)->F2) -#define LLWU_F3_REG(base) ((base)->F3) -#define LLWU_FILT1_REG(base) ((base)->FILT1) -#define LLWU_FILT2_REG(base) ((base)->FILT2) -#define LLWU_RST_REG(base) ((base)->RST) - -/*! - * @} - */ /* end of group LLWU_Register_Accessor_Macros */ - +} LLWU_Type; /* ---------------------------------------------------------------------------- -- LLWU Register Masks @@ -8912,241 +6094,196 @@ typedef struct { * @{ */ -/* PE1 Bit Fields */ -#define LLWU_PE1_WUPE0_MASK 0x3u -#define LLWU_PE1_WUPE0_SHIFT 0 -#define LLWU_PE1_WUPE0_WIDTH 2 -#define LLWU_PE1_WUPE0(x) (((uint8_t)(((uint8_t)(x))<CSR) -#define LPTMR_PSR_REG(base) ((base)->PSR) -#define LPTMR_CMR_REG(base) ((base)->CMR) -#define LPTMR_CNR_REG(base) ((base)->CNR) - -/*! - * @} - */ /* end of group LPTMR_Register_Accessor_Macros */ - +} LPTMR_Type; /* ---------------------------------------------------------------------------- -- LPTMR Register Masks @@ -9247,58 +6333,50 @@ typedef struct { * @{ */ -/* CSR Bit Fields */ -#define LPTMR_CSR_TEN_MASK 0x1u -#define LPTMR_CSR_TEN_SHIFT 0 -#define LPTMR_CSR_TEN_WIDTH 1 -#define LPTMR_CSR_TEN(x) (((uint32_t)(((uint32_t)(x))<C1) -#define MCG_C2_REG(base) ((base)->C2) -#define MCG_C3_REG(base) ((base)->C3) -#define MCG_C4_REG(base) ((base)->C4) -#define MCG_C5_REG(base) ((base)->C5) -#define MCG_C6_REG(base) ((base)->C6) -#define MCG_S_REG(base) ((base)->S) -#define MCG_SC_REG(base) ((base)->SC) -#define MCG_ATCVH_REG(base) ((base)->ATCVH) -#define MCG_ATCVL_REG(base) ((base)->ATCVL) -#define MCG_C7_REG(base) ((base)->C7) -#define MCG_C8_REG(base) ((base)->C8) - -/*! - * @} - */ /* end of group MCG_Register_Accessor_Macros */ - +} MCG_Type; /* ---------------------------------------------------------------------------- -- MCG Register Masks @@ -9410,190 +6436,159 @@ typedef struct { * @{ */ -/* C1 Bit Fields */ -#define MCG_C1_IREFSTEN_MASK 0x1u -#define MCG_C1_IREFSTEN_SHIFT 0 -#define MCG_C1_IREFSTEN_WIDTH 1 -#define MCG_C1_IREFSTEN(x) (((uint8_t)(((uint8_t)(x))<PLASC) -#define MCM_PLAMC_REG(base) ((base)->PLAMC) -#define MCM_CR_REG(base) ((base)->CR) -#define MCM_ISCR_REG(base) ((base)->ISCR) -#define MCM_ETBCC_REG(base) ((base)->ETBCC) -#define MCM_ETBRL_REG(base) ((base)->ETBRL) -#define MCM_ETBCNT_REG(base) ((base)->ETBCNT) -#define MCM_PID_REG(base) ((base)->PID) - -/*! - * @} - */ /* end of group MCM_Register_Accessor_Macros */ - +} MCM_Type; /* ---------------------------------------------------------------------------- -- MCM Register Masks @@ -9703,130 +6642,109 @@ typedef struct { * @{ */ -/* PLASC Bit Fields */ -#define MCM_PLASC_ASC_MASK 0xFFu -#define MCM_PLASC_ASC_SHIFT 0 -#define MCM_PLASC_ASC_WIDTH 8 -#define MCM_PLASC_ASC(x) (((uint16_t)(((uint16_t)(x))<CESR) -#define MPU_EAR_REG(base,index) ((base)->SP[index].EAR) -#define MPU_EAR_COUNT 5 -#define MPU_EDR_REG(base,index) ((base)->SP[index].EDR) -#define MPU_EDR_COUNT 5 -#define MPU_WORD_REG(base,index,index2) ((base)->WORD[index][index2]) -#define MPU_WORD_COUNT 12 -#define MPU_WORD_COUNT2 4 -#define MPU_RGDAAC_REG(base,index) ((base)->RGDAAC[index]) -#define MPU_RGDAAC_COUNT 12 - -/*! - * @} - */ /* end of group MPU_Register_Accessor_Macros */ - - -/* ---------------------------------------------------------------------------- - -- MPU Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup MPU_Register_Masks MPU Register Masks - * @{ - */ - -/* CESR Bit Fields */ -#define MPU_CESR_VLD_MASK 0x1u -#define MPU_CESR_VLD_SHIFT 0 -#define MPU_CESR_VLD_WIDTH 1 -#define MPU_CESR_VLD(x) (((uint32_t)(((uint32_t)(x))<BACKKEY3) -#define NV_BACKKEY2_REG(base) ((base)->BACKKEY2) -#define NV_BACKKEY1_REG(base) ((base)->BACKKEY1) -#define NV_BACKKEY0_REG(base) ((base)->BACKKEY0) -#define NV_BACKKEY7_REG(base) ((base)->BACKKEY7) -#define NV_BACKKEY6_REG(base) ((base)->BACKKEY6) -#define NV_BACKKEY5_REG(base) ((base)->BACKKEY5) -#define NV_BACKKEY4_REG(base) ((base)->BACKKEY4) -#define NV_FPROT3_REG(base) ((base)->FPROT3) -#define NV_FPROT2_REG(base) ((base)->FPROT2) -#define NV_FPROT1_REG(base) ((base)->FPROT1) -#define NV_FPROT0_REG(base) ((base)->FPROT0) -#define NV_FSEC_REG(base) ((base)->FSEC) -#define NV_FOPT_REG(base) ((base)->FOPT) -#define NV_FEPROT_REG(base) ((base)->FEPROT) -#define NV_FDPROT_REG(base) ((base)->FDPROT) - -/*! - * @} - */ /* end of group NV_Register_Accessor_Macros */ - +} NV_Type; /* ---------------------------------------------------------------------------- -- NV Register Masks @@ -10353,106 +6806,101 @@ typedef struct { * @{ */ -/* BACKKEY3 Bit Fields */ -#define NV_BACKKEY3_KEY_MASK 0xFFu -#define NV_BACKKEY3_KEY_SHIFT 0 -#define NV_BACKKEY3_KEY_WIDTH 8 -#define NV_BACKKEY3_KEY(x) (((uint8_t)(((uint8_t)(x))<CR) - -/*! - * @} - */ /* end of group OSC_Register_Accessor_Macros */ - +} OSC_Type; /* ---------------------------------------------------------------------------- -- OSC Register Masks @@ -10550,31 +6945,26 @@ typedef struct { * @{ */ -/* CR Bit Fields */ -#define OSC_CR_SC16P_MASK 0x1u -#define OSC_CR_SC16P_SHIFT 0 -#define OSC_CR_SC16P_WIDTH 1 -#define OSC_CR_SC16P(x) (((uint8_t)(((uint8_t)(x))<SC) -#define PDB_MOD_REG(base) ((base)->MOD) -#define PDB_CNT_REG(base) ((base)->CNT) -#define PDB_IDLY_REG(base) ((base)->IDLY) -#define PDB_C1_REG(base,index) ((base)->CH[index].C1) -#define PDB_C1_COUNT 2 -#define PDB_S_REG(base,index) ((base)->CH[index].S) -#define PDB_S_COUNT 2 -#define PDB_DLY_REG(base,index,index2) ((base)->CH[index].DLY[index2]) -#define PDB_DLY_COUNT 2 -#define PDB_DLY_COUNT2 2 -#define PDB_INTC_REG(base,index) ((base)->DAC[index].INTC) -#define PDB_INTC_COUNT 2 -#define PDB_INT_REG(base,index) ((base)->DAC[index].INT) -#define PDB_INT_COUNT 2 -#define PDB_POEN_REG(base) ((base)->POEN) -#define PDB_PODLY_REG(base,index) ((base)->PODLY[index]) -#define PDB_PODLY_COUNT 3 - -/*! - * @} - */ /* end of group PDB_Register_Accessor_Macros */ - +} PDB_Type; /* ---------------------------------------------------------------------------- -- PDB Register Masks @@ -10691,125 +7026,130 @@ typedef struct { * @{ */ -/* SC Bit Fields */ -#define PDB_SC_LDOK_MASK 0x1u -#define PDB_SC_LDOK_SHIFT 0 -#define PDB_SC_LDOK_WIDTH 1 -#define PDB_SC_LDOK(x) (((uint32_t)(((uint32_t)(x))<MCR) -#define PIT_LDVAL_REG(base,index) ((base)->CHANNEL[index].LDVAL) -#define PIT_LDVAL_COUNT 4 -#define PIT_CVAL_REG(base,index) ((base)->CHANNEL[index].CVAL) -#define PIT_CVAL_COUNT 4 -#define PIT_TCTRL_REG(base,index) ((base)->CHANNEL[index].TCTRL) -#define PIT_TCTRL_COUNT 4 -#define PIT_TFLG_REG(base,index) ((base)->CHANNEL[index].TFLG) -#define PIT_TFLG_COUNT 4 - -/*! - * @} - */ /* end of group PIT_Register_Accessor_Macros */ - +} PIT_Type; /* ---------------------------------------------------------------------------- -- PIT Register Masks @@ -10936,43 +7203,52 @@ typedef struct { * @{ */ -/* MCR Bit Fields */ -#define PIT_MCR_FRZ_MASK 0x1u -#define PIT_MCR_FRZ_SHIFT 0 -#define PIT_MCR_FRZ_WIDTH 1 -#define PIT_MCR_FRZ(x) (((uint32_t)(((uint32_t)(x))<LVDSC1) -#define PMC_LVDSC2_REG(base) ((base)->LVDSC2) -#define PMC_REGSC_REG(base) ((base)->REGSC) - -/*! - * @} - */ /* end of group PMC_Register_Accessor_Macros */ - +} PMC_Type; /* ---------------------------------------------------------------------------- -- PMC Register Masks @@ -11083,61 +7297,51 @@ typedef struct { * @{ */ -/* LVDSC1 Bit Fields */ -#define PMC_LVDSC1_LVDV_MASK 0x3u -#define PMC_LVDSC1_LVDV_SHIFT 0 -#define PMC_LVDSC1_LVDV_WIDTH 2 -#define PMC_LVDSC1_LVDV(x) (((uint8_t)(((uint8_t)(x))<PCR[index]) -#define PORT_PCR_COUNT 32 -#define PORT_GPCLR_REG(base) ((base)->GPCLR) -#define PORT_GPCHR_REG(base) ((base)->GPCHR) -#define PORT_ISFR_REG(base) ((base)->ISFR) -#define PORT_DFER_REG(base) ((base)->DFER) -#define PORT_DFCR_REG(base) ((base)->DFCR) -#define PORT_DFWR_REG(base) ((base)->DFWR) - -/*! - * @} - */ /* end of group PORT_Register_Accessor_Macros */ - +} PORT_Type; /* ---------------------------------------------------------------------------- -- PORT Register Masks @@ -11239,85 +7396,77 @@ typedef struct { * @{ */ -/* PCR Bit Fields */ -#define PORT_PCR_PS_MASK 0x1u -#define PORT_PCR_PS_SHIFT 0 -#define PORT_PCR_PS_WIDTH 1 -#define PORT_PCR_PS(x) (((uint32_t)(((uint32_t)(x))<SRS0) -#define RCM_SRS1_REG(base) ((base)->SRS1) -#define RCM_RPFC_REG(base) ((base)->RPFC) -#define RCM_RPFW_REG(base) ((base)->RPFW) -#define RCM_MR_REG(base) ((base)->MR) - -/*! - * @} - */ /* end of group RCM_Register_Accessor_Macros */ - +} RCM_Type; /* ---------------------------------------------------------------------------- -- RCM Register Masks @@ -11620,79 +7535,67 @@ typedef struct { * @{ */ -/* SRS0 Bit Fields */ -#define RCM_SRS0_WAKEUP_MASK 0x1u -#define RCM_SRS0_WAKEUP_SHIFT 0 -#define RCM_SRS0_WAKEUP_WIDTH 1 -#define RCM_SRS0_WAKEUP(x) (((uint8_t)(((uint8_t)(x))<REG[index]) -#define RFSYS_REG_COUNT 8 - -/*! - * @} - */ /* end of group RFSYS_Register_Accessor_Macros */ - +} RFSYS_Type; /* ---------------------------------------------------------------------------- -- RFSYS Register Masks @@ -11780,23 +7640,23 @@ typedef struct { * @{ */ -/* REG Bit Fields */ -#define RFSYS_REG_LL_MASK 0xFFu -#define RFSYS_REG_LL_SHIFT 0 -#define RFSYS_REG_LL_WIDTH 8 -#define RFSYS_REG_LL(x) (((uint32_t)(((uint32_t)(x))<REG[index]) -#define RFVBAT_REG_COUNT 8 - -/*! - * @} - */ /* end of group RFVBAT_Register_Accessor_Macros */ - +} RFVBAT_Type; /* ---------------------------------------------------------------------------- -- RFVBAT Register Masks @@ -11890,23 +7701,23 @@ typedef struct { * @{ */ -/* REG Bit Fields */ -#define RFVBAT_REG_LL_MASK 0xFFu -#define RFVBAT_REG_LL_SHIFT 0 -#define RFVBAT_REG_LL_WIDTH 8 -#define RFVBAT_REG_LL(x) (((uint32_t)(((uint32_t)(x))<TSR) -#define RTC_TPR_REG(base) ((base)->TPR) -#define RTC_TAR_REG(base) ((base)->TAR) -#define RTC_TCR_REG(base) ((base)->TCR) -#define RTC_CR_REG(base) ((base)->CR) -#define RTC_SR_REG(base) ((base)->SR) -#define RTC_LR_REG(base) ((base)->LR) -#define RTC_IER_REG(base) ((base)->IER) -#define RTC_TTSR_REG(base) ((base)->TTSR) -#define RTC_MER_REG(base) ((base)->MER) -#define RTC_MCLR_REG(base) ((base)->MCLR) -#define RTC_MCHR_REG(base) ((base)->MCHR) -#define RTC_WAR_REG(base) ((base)->WAR) -#define RTC_RAR_REG(base) ((base)->RAR) - -/*! - * @} - */ /* end of group RTC_Register_Accessor_Macros */ - +} RTC_Type; /* ---------------------------------------------------------------------------- -- RTC Register Masks @@ -12026,280 +7776,229 @@ typedef struct { * @{ */ -/* TSR Bit Fields */ -#define RTC_TSR_TSR_MASK 0xFFFFFFFFu -#define RTC_TSR_TSR_SHIFT 0 -#define RTC_TSR_TSR_WIDTH 32 -#define RTC_TSR_TSR(x) (((uint32_t)(((uint32_t)(x))<DSADDR) -#define SDHC_BLKATTR_REG(base) ((base)->BLKATTR) -#define SDHC_CMDARG_REG(base) ((base)->CMDARG) -#define SDHC_XFERTYP_REG(base) ((base)->XFERTYP) -#define SDHC_CMDRSP_REG(base,index) ((base)->CMDRSP[index]) -#define SDHC_CMDRSP_COUNT 4 -#define SDHC_DATPORT_REG(base) ((base)->DATPORT) -#define SDHC_PRSSTAT_REG(base) ((base)->PRSSTAT) -#define SDHC_PROCTL_REG(base) ((base)->PROCTL) -#define SDHC_SYSCTL_REG(base) ((base)->SYSCTL) -#define SDHC_IRQSTAT_REG(base) ((base)->IRQSTAT) -#define SDHC_IRQSTATEN_REG(base) ((base)->IRQSTATEN) -#define SDHC_IRQSIGEN_REG(base) ((base)->IRQSIGEN) -#define SDHC_AC12ERR_REG(base) ((base)->AC12ERR) -#define SDHC_HTCAPBLT_REG(base) ((base)->HTCAPBLT) -#define SDHC_WML_REG(base) ((base)->WML) -#define SDHC_FEVT_REG(base) ((base)->FEVT) -#define SDHC_ADMAES_REG(base) ((base)->ADMAES) -#define SDHC_ADSADDR_REG(base) ((base)->ADSADDR) -#define SDHC_VENDOR_REG(base) ((base)->VENDOR) -#define SDHC_MMCBOOT_REG(base) ((base)->MMCBOOT) -#define SDHC_HOSTVER_REG(base) ((base)->HOSTVER) - -/*! - * @} - */ /* end of group SDHC_Register_Accessor_Macros */ - +} SDHC_Type; /* ---------------------------------------------------------------------------- -- SDHC Register Masks @@ -12442,663 +8069,528 @@ typedef struct { * @{ */ -/* DSADDR Bit Fields */ -#define SDHC_DSADDR_DSADDR_MASK 0xFFFFFFFCu -#define SDHC_DSADDR_DSADDR_SHIFT 2 -#define SDHC_DSADDR_DSADDR_WIDTH 30 -#define SDHC_DSADDR_DSADDR(x) (((uint32_t)(((uint32_t)(x))<SOPT1) -#define SIM_SOPT1CFG_REG(base) ((base)->SOPT1CFG) -#define SIM_SOPT2_REG(base) ((base)->SOPT2) -#define SIM_SOPT4_REG(base) ((base)->SOPT4) -#define SIM_SOPT5_REG(base) ((base)->SOPT5) -#define SIM_SOPT7_REG(base) ((base)->SOPT7) -#define SIM_SDID_REG(base) ((base)->SDID) -#define SIM_SCGC1_REG(base) ((base)->SCGC1) -#define SIM_SCGC2_REG(base) ((base)->SCGC2) -#define SIM_SCGC3_REG(base) ((base)->SCGC3) -#define SIM_SCGC4_REG(base) ((base)->SCGC4) -#define SIM_SCGC5_REG(base) ((base)->SCGC5) -#define SIM_SCGC6_REG(base) ((base)->SCGC6) -#define SIM_SCGC7_REG(base) ((base)->SCGC7) -#define SIM_CLKDIV1_REG(base) ((base)->CLKDIV1) -#define SIM_CLKDIV2_REG(base) ((base)->CLKDIV2) -#define SIM_FCFG1_REG(base) ((base)->FCFG1) -#define SIM_FCFG2_REG(base) ((base)->FCFG2) -#define SIM_UIDH_REG(base) ((base)->UIDH) -#define SIM_UIDMH_REG(base) ((base)->UIDMH) -#define SIM_UIDML_REG(base) ((base)->UIDML) -#define SIM_UIDL_REG(base) ((base)->UIDL) - -/*! - * @} - */ /* end of group SIM_Register_Accessor_Macros */ - +} SIM_Type; /* ---------------------------------------------------------------------------- -- SIM Register Masks @@ -13255,476 +8662,386 @@ typedef struct { * @{ */ -/* SOPT1 Bit Fields */ -#define SIM_SOPT1_RAMSIZE_MASK 0xF000u -#define SIM_SOPT1_RAMSIZE_SHIFT 12 -#define SIM_SOPT1_RAMSIZE_WIDTH 4 -#define SIM_SOPT1_RAMSIZE(x) (((uint32_t)(((uint32_t)(x))<PMPROT) -#define SMC_PMCTRL_REG(base) ((base)->PMCTRL) -#define SMC_VLLSCTRL_REG(base) ((base)->VLLSCTRL) -#define SMC_PMSTAT_REG(base) ((base)->PMSTAT) - -/*! - * @} - */ /* end of group SMC_Register_Accessor_Macros */ - +} SMC_Type; /* ---------------------------------------------------------------------------- -- SMC Register Masks @@ -13834,54 +9089,47 @@ typedef struct { * @{ */ -/* PMPROT Bit Fields */ -#define SMC_PMPROT_AVLLS_MASK 0x2u -#define SMC_PMPROT_AVLLS_SHIFT 1 -#define SMC_PMPROT_AVLLS_WIDTH 1 -#define SMC_PMPROT_AVLLS(x) (((uint8_t)(((uint8_t)(x))<MCR) -#define SPI_TCR_REG(base) ((base)->TCR) -#define SPI_CTAR_REG(base,index2) ((base)->CTAR[index2]) -#define SPI_CTAR_COUNT 2 -#define SPI_CTAR_SLAVE_REG(base,index2) ((base)->CTAR_SLAVE[index2]) -#define SPI_CTAR_SLAVE_COUNT 1 -#define SPI_SR_REG(base) ((base)->SR) -#define SPI_RSER_REG(base) ((base)->RSER) -#define SPI_PUSHR_REG(base) ((base)->PUSHR) -#define SPI_PUSHR_SLAVE_REG(base) ((base)->PUSHR_SLAVE) -#define SPI_POPR_REG(base) ((base)->POPR) -#define SPI_TXFR0_REG(base) ((base)->TXFR0) -#define SPI_TXFR1_REG(base) ((base)->TXFR1) -#define SPI_TXFR2_REG(base) ((base)->TXFR2) -#define SPI_TXFR3_REG(base) ((base)->TXFR3) -#define SPI_RXFR0_REG(base) ((base)->RXFR0) -#define SPI_RXFR1_REG(base) ((base)->RXFR1) -#define SPI_RXFR2_REG(base) ((base)->RXFR2) -#define SPI_RXFR3_REG(base) ((base)->RXFR3) - -/*! - * @} - */ /* end of group SPI_Register_Accessor_Macros */ - +} SPI_Type; /* ---------------------------------------------------------------------------- -- SPI Register Masks @@ -14008,311 +9197,262 @@ typedef struct { * @{ */ -/* MCR Bit Fields */ -#define SPI_MCR_HALT_MASK 0x1u -#define SPI_MCR_HALT_SHIFT 0 -#define SPI_MCR_HALT_WIDTH 1 -#define SPI_MCR_HALT(x) (((uint32_t)(((uint32_t)(x))<BDH) -#define UART_BDL_REG(base) ((base)->BDL) -#define UART_C1_REG(base) ((base)->C1) -#define UART_C2_REG(base) ((base)->C2) -#define UART_S1_REG(base) ((base)->S1) -#define UART_S2_REG(base) ((base)->S2) -#define UART_C3_REG(base) ((base)->C3) -#define UART_D_REG(base) ((base)->D) -#define UART_MA1_REG(base) ((base)->MA1) -#define UART_MA2_REG(base) ((base)->MA2) -#define UART_C4_REG(base) ((base)->C4) -#define UART_C5_REG(base) ((base)->C5) -#define UART_ED_REG(base) ((base)->ED) -#define UART_MODEM_REG(base) ((base)->MODEM) -#define UART_IR_REG(base) ((base)->IR) -#define UART_PFIFO_REG(base) ((base)->PFIFO) -#define UART_CFIFO_REG(base) ((base)->CFIFO) -#define UART_SFIFO_REG(base) ((base)->SFIFO) -#define UART_TWFIFO_REG(base) ((base)->TWFIFO) -#define UART_TCFIFO_REG(base) ((base)->TCFIFO) -#define UART_RWFIFO_REG(base) ((base)->RWFIFO) -#define UART_RCFIFO_REG(base) ((base)->RCFIFO) -#define UART_C7816_REG(base) ((base)->C7816) -#define UART_IE7816_REG(base) ((base)->IE7816) -#define UART_IS7816_REG(base) ((base)->IS7816) -#define UART_WP7816_REG(base) ((base)->WP7816) -#define UART_WN7816_REG(base) ((base)->WN7816) -#define UART_WF7816_REG(base) ((base)->WF7816) -#define UART_ET7816_REG(base) ((base)->ET7816) -#define UART_TL7816_REG(base) ((base)->TL7816) -#define UART_AP7816A_T0_REG(base) ((base)->AP7816A_T0) -#define UART_AP7816B_T0_REG(base) ((base)->AP7816B_T0) -#define UART_WP7816A_T0_REG(base) ((base)->TYPE0.WP7816A_T0) -#define UART_WP7816B_T0_REG(base) ((base)->TYPE0.WP7816B_T0) -#define UART_WP7816A_T1_REG(base) ((base)->TYPE1.WP7816A_T1) -#define UART_WP7816B_T1_REG(base) ((base)->TYPE1.WP7816B_T1) -#define UART_WGP7816_T1_REG(base) ((base)->WGP7816_T1) -#define UART_WP7816C_T1_REG(base) ((base)->WP7816C_T1) - -/*! - * @} - */ /* end of group UART_Register_Accessor_Macros */ - +} UART_Type; /* ---------------------------------------------------------------------------- -- UART Register Masks @@ -14553,504 +9799,427 @@ typedef struct { * @{ */ -/* BDH Bit Fields */ -#define UART_BDH_SBR_MASK 0x1Fu -#define UART_BDH_SBR_SHIFT 0 -#define UART_BDH_SBR_WIDTH 5 -#define UART_BDH_SBR(x) (((uint8_t)(((uint8_t)(x))<PERID) -#define USB_IDCOMP_REG(base) ((base)->IDCOMP) -#define USB_REV_REG(base) ((base)->REV) -#define USB_ADDINFO_REG(base) ((base)->ADDINFO) -#define USB_OTGISTAT_REG(base) ((base)->OTGISTAT) -#define USB_OTGICR_REG(base) ((base)->OTGICR) -#define USB_OTGSTAT_REG(base) ((base)->OTGSTAT) -#define USB_OTGCTL_REG(base) ((base)->OTGCTL) -#define USB_ISTAT_REG(base) ((base)->ISTAT) -#define USB_INTEN_REG(base) ((base)->INTEN) -#define USB_ERRSTAT_REG(base) ((base)->ERRSTAT) -#define USB_ERREN_REG(base) ((base)->ERREN) -#define USB_STAT_REG(base) ((base)->STAT) -#define USB_CTL_REG(base) ((base)->CTL) -#define USB_ADDR_REG(base) ((base)->ADDR) -#define USB_BDTPAGE1_REG(base) ((base)->BDTPAGE1) -#define USB_FRMNUML_REG(base) ((base)->FRMNUML) -#define USB_FRMNUMH_REG(base) ((base)->FRMNUMH) -#define USB_TOKEN_REG(base) ((base)->TOKEN) -#define USB_SOFTHLD_REG(base) ((base)->SOFTHLD) -#define USB_BDTPAGE2_REG(base) ((base)->BDTPAGE2) -#define USB_BDTPAGE3_REG(base) ((base)->BDTPAGE3) -#define USB_ENDPT_REG(base,index) ((base)->ENDPOINT[index].ENDPT) -#define USB_ENDPT_COUNT 16 -#define USB_USBCTRL_REG(base) ((base)->USBCTRL) -#define USB_OBSERVE_REG(base) ((base)->OBSERVE) -#define USB_CONTROL_REG(base) ((base)->CONTROL) -#define USB_USBTRC0_REG(base) ((base)->USBTRC0) -#define USB_USBFRMADJUST_REG(base) ((base)->USBFRMADJUST) - -/*! - * @} - */ /* end of group USB_Register_Accessor_Macros */ - +} USB_Type; /* ---------------------------------------------------------------------------- -- USB Register Masks @@ -15397,414 +10343,350 @@ typedef struct { * @{ */ -/* PERID Bit Fields */ -#define USB_PERID_ID_MASK 0x3Fu -#define USB_PERID_ID_SHIFT 0 -#define USB_PERID_ID_WIDTH 6 -#define USB_PERID_ID(x) (((uint8_t)(((uint8_t)(x))<CONTROL) -#define USBDCD_CLOCK_REG(base) ((base)->CLOCK) -#define USBDCD_STATUS_REG(base) ((base)->STATUS) -#define USBDCD_TIMER0_REG(base) ((base)->TIMER0) -#define USBDCD_TIMER1_REG(base) ((base)->TIMER1) -#define USBDCD_TIMER2_BC11_REG(base) ((base)->TIMER2_BC11) -#define USBDCD_TIMER2_BC12_REG(base) ((base)->TIMER2_BC12) - -/*! - * @} - */ /* end of group USBDCD_Register_Accessor_Macros */ - +} USBDCD_Type; /* ---------------------------------------------------------------------------- -- USBDCD Register Masks @@ -15949,97 +10742,83 @@ typedef struct { * @{ */ -/* CONTROL Bit Fields */ -#define USBDCD_CONTROL_IACK_MASK 0x1u -#define USBDCD_CONTROL_IACK_SHIFT 0 -#define USBDCD_CONTROL_IACK_WIDTH 1 -#define USBDCD_CONTROL_IACK(x) (((uint32_t)(((uint32_t)(x))<TRM) -#define VREF_SC_REG(base) ((base)->SC) - -/*! - * @} - */ /* end of group VREF_Register_Accessor_Macros */ - +} VREF_Type; /* ---------------------------------------------------------------------------- -- VREF Register Masks @@ -16132,36 +10866,31 @@ typedef struct { * @{ */ -/* TRM Bit Fields */ -#define VREF_TRM_TRIM_MASK 0x3Fu -#define VREF_TRM_TRIM_SHIFT 0 -#define VREF_TRM_TRIM_WIDTH 6 -#define VREF_TRM_TRIM(x) (((uint8_t)(((uint8_t)(x))<STCTRLH) -#define WDOG_STCTRLL_REG(base) ((base)->STCTRLL) -#define WDOG_TOVALH_REG(base) ((base)->TOVALH) -#define WDOG_TOVALL_REG(base) ((base)->TOVALL) -#define WDOG_WINH_REG(base) ((base)->WINH) -#define WDOG_WINL_REG(base) ((base)->WINL) -#define WDOG_REFRESH_REG(base) ((base)->REFRESH) -#define WDOG_UNLOCK_REG(base) ((base)->UNLOCK) -#define WDOG_TMROUTH_REG(base) ((base)->TMROUTH) -#define WDOG_TMROUTL_REG(base) ((base)->TMROUTL) -#define WDOG_RSTCNT_REG(base) ((base)->RSTCNT) -#define WDOG_PRESC_REG(base) ((base)->PRESC) - -/*! - * @} - */ /* end of group WDOG_Register_Accessor_Macros */ - +} WDOG_Type; /* ---------------------------------------------------------------------------- -- WDOG Register Masks @@ -16267,110 +10946,99 @@ typedef struct { * @{ */ -/* STCTRLH Bit Fields */ -#define WDOG_STCTRLH_WDOGEN_MASK 0x1u -#define WDOG_STCTRLH_WDOGEN_SHIFT 0 -#define WDOG_STCTRLH_WDOGEN_WIDTH 1 -#define WDOG_STCTRLH_WDOGEN(x) (((uint16_t)(((uint16_t)(x))<= 6010050) + #pragma clang system_header + #endif +#elif defined(__IAR_SYSTEMS_ICC__) + #pragma system_include +#endif + +/** + * @brief Mask and left-shift a bit field value for use in a register bit range. + * @param field Name of the register bit field. + * @param value Value of the bit field. + * @return Masked and shifted value. + */ +#define NXP_VAL2FLD(field, value) (((value) << (field ## _SHIFT)) & (field ## _MASK)) +/** + * @brief Mask and right-shift a register value to extract a bit field value. + * @param field Name of the register bit field. + * @param value Value of the register. + * @return Masked and shifted bit field value. + */ +#define NXP_FLD2VAL(field, value) (((value) & (field ## _MASK)) >> (field ## _SHIFT)) + +/*! + * @} + */ /* end of group Bit_Field_Generic_Macros */ + + +/* ---------------------------------------------------------------------------- + -- SDK Compatibility + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup SDK_Compatibility_Symbols SDK Compatibility + * @{ + */ + +#define DSPI0 SPI0 +#define DSPI1 SPI1 +#define DSPI2 SPI2 +#define FLEXCAN0 CAN0 #define PTA_BASE GPIOA_BASE #define PTA GPIOA -#define PTB_BASE_PTR GPIOB_BASE_PTR #define PTB_BASE GPIOB_BASE #define PTB GPIOB -#define PTC_BASE_PTR GPIOC_BASE_PTR #define PTC_BASE GPIOC_BASE #define PTC GPIOC -#define PTD_BASE_PTR GPIOD_BASE_PTR #define PTD_BASE GPIOD_BASE #define PTD GPIOD -#define PTE_BASE_PTR GPIOE_BASE_PTR #define PTE_BASE GPIOE_BASE #define PTE GPIOE +#define DMAMUX0 DMAMUX #define SIM_SCGC6_FTFL_MASK SIM_SCGC6_FTF_MASK #define SIM_SCGC6_FTFL_SHIFT SIM_SCGC6_FTF_SHIFT #define MCG_S_LOLS_MASK MCG_S_LOLS0_MASK @@ -16481,24 +11155,15 @@ typedef struct { #define MCG_C2_RANGE0_MASK MCG_C2_RANGE_MASK #define MCG_C2_RANGE0_SHIFT MCG_C2_RANGE_SHIFT #define MCG_C2_RANGE0(x) MCG_C2_RANGE(x) -#define Watchdog_IRQn WDOG_EWM_IRQn -#define Watchdog_IRQHandler WDOG_EWM_IRQHandler -#define LPTimer_IRQn LPTMR0_IRQn -#define LPTimer_IRQHandler LPTMR0_IRQHandler -#define LLW_IRQn LLWU_IRQn -#define LLW_IRQHandler LLWU_IRQHandler +#define Watchdog_IRQn WDOG_EWM_IRQn +#define Watchdog_IRQHandler WDOG_EWM_IRQHandler +#define LPTimer_IRQn LPTMR0_IRQn +#define LPTimer_IRQHandler LPTMR0_IRQHandler +#define LLW_IRQn LLWU_IRQn +#define LLW_IRQHandler LLWU_IRQHandler -#define OSC0 OSC /*! * @} - */ /* end of group Backward_Compatibility_Symbols */ + */ /* end of group SDK_Compatibility_Symbols */ - -#else /* #if !defined(MK22FA12_H_) */ - /* There is already included the same memory map. Check if it is compatible (has the same major version) */ - #if (MCU_MEM_MAP_VERSION != 0x0100u) - #if (!defined(MCU_MEM_MAP_SUPPRESS_VERSION_WARNING)) - #warning There are included two not compatible versions of memory maps. Please check possible differences. - #endif /* (!defined(MCU_MEM_MAP_SUPPRESS_VERSION_WARNING)) */ - #endif /* (MCU_MEM_MAP_VERSION != 0x0100u) */ -#endif /* #if !defined(MK22FA12_H_) */ +#endif /* _MK22FA12_H_ */