diff --git a/boards/common/stm32/include/cfg_timer_tim2.h b/boards/common/stm32/include/cfg_timer_tim2.h index 35a440371e..dee761f2fd 100644 --- a/boards/common/stm32/include/cfg_timer_tim2.h +++ b/boards/common/stm32/include/cfg_timer_tim2.h @@ -40,6 +40,8 @@ static const timer_conf_t timer_config[] = { #if defined(CPU_FAM_STM32L4) || defined(CPU_FAM_STM32WB) || \ defined(CPU_FAM_STM32G4) .rcc_mask = RCC_APB1ENR1_TIM2EN, +#elif CPU_FAM_STM32MP1 + .rcc_mask = RCC_MC_APB1ENSETR_TIM2EN, #else .rcc_mask = RCC_APB1ENR_TIM2EN, #endif diff --git a/cpu/stm32/include/clk/clk_conf.h b/cpu/stm32/include/clk/clk_conf.h index 797f00284f..2714dee16a 100644 --- a/cpu/stm32/include/clk/clk_conf.h +++ b/cpu/stm32/include/clk/clk_conf.h @@ -38,6 +38,8 @@ #elif defined(CPU_FAM_STM32L4) || defined(CPU_FAM_STM32L5) || \ defined(CPU_FAM_STM32WB) #include "l4l5wb/cfg_clock_default.h" +#elif defined(CPU_FAM_STM32MP1) +#include "mp1/cfg_clock_default.h" #else #error "No clock configuration available" #endif diff --git a/cpu/stm32/include/clk/mp1/cfg_clock_common.h b/cpu/stm32/include/clk/mp1/cfg_clock_common.h new file mode 100644 index 0000000000..68ed904e7d --- /dev/null +++ b/cpu/stm32/include/clk/mp1/cfg_clock_common.h @@ -0,0 +1,77 @@ +/* + * Copyright (C) 2020 Savoir-faire Linux + * + * This file is subject to the terms and conditions of the GNU Lesser General + * Public License v2.1. See the file LICENSE in the top level directory for more + * details. + */ + +/** + * @ingroup boards_common_stm32 + * @{ + * + * @file + * @brief Base STM32MP1 clock configuration + * + * @author Gilles DOFFE + */ + +#ifndef CLK_MP1_CFG_CLOCK_COMMON_H +#define CLK_MP1_CFG_CLOCK_COMMON_H + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @name Clock common configuration + * @{ + */ +/* Select the desired system clock source between PLL, HSE or HSI */ +#ifndef CONFIG_USE_CLOCK_PLL +#if IS_ACTIVE(CONFIG_USE_CLOCK_HSE) || IS_ACTIVE(CONFIG_USE_CLOCK_HSI) +#define CONFIG_USE_CLOCK_PLL 0 +#else +#define CONFIG_USE_CLOCK_PLL 1 /* Use PLL by default */ +#endif +#endif /* CONFIG_USE_CLOCK_PLL */ + +#ifndef CONFIG_USE_CLOCK_HSE +#define CONFIG_USE_CLOCK_HSE 0 +#endif /* CONFIG_USE_CLOCK_HSE */ + +#ifndef CONFIG_USE_CLOCK_HSI +#define CONFIG_USE_CLOCK_HSI 0 +#endif /* CONFIG_USE_CLOCK_HSI */ + +#if IS_ACTIVE(CONFIG_USE_CLOCK_PLL) && \ + (IS_ACTIVE(CONFIG_USE_CLOCK_HSE) || IS_ACTIVE(CONFIG_USE_CLOCK_HSI)) +#error "Cannot use PLL as clock source with other clock configurations" +#endif + +#if IS_ACTIVE(CONFIG_USE_CLOCK_HSE) && \ + (IS_ACTIVE(CONFIG_USE_CLOCK_PLL) || IS_ACTIVE(CONFIG_USE_CLOCK_HSI)) +#error "Cannot use HSE as clock source with other clock configurations" +#endif + +#if IS_ACTIVE(CONFIG_USE_CLOCK_HSI) && \ + (IS_ACTIVE(CONFIG_USE_CLOCK_PLL) || IS_ACTIVE(CONFIG_USE_CLOCK_HSE)) +#error "Cannot use HSI as clock source with other clock configurations" +#endif + +#ifndef CONFIG_BOARD_HAS_HSE +#define CONFIG_BOARD_HAS_HSE 0 +#endif + +#ifndef CLOCK_HSE +#define CLOCK_HSE MHZ(24) +#endif + +#define CLOCK_HSI MHZ(64) + +#ifdef __cplusplus +} +#endif + +#endif /* CLK_MP1_CFG_CLOCK_COMMON_H */ +/** @} */ diff --git a/cpu/stm32/include/clk/mp1/cfg_clock_default.h b/cpu/stm32/include/clk/mp1/cfg_clock_default.h new file mode 100644 index 0000000000..aa77185731 --- /dev/null +++ b/cpu/stm32/include/clk/mp1/cfg_clock_default.h @@ -0,0 +1,38 @@ +/* + * Copyright (C) 2020 Savoir-faire Linux + * + * This file is subject to the terms and conditions of the GNU Lesser General + * Public License v2.1. See the file LICENSE in the top level directory for more + * details. + */ + + +/** + * @ingroup cpu_stm32 + * @{ + * + * @file + * @brief Main header for STM32MP1 clock configuration + * + * @author Gilles DOFFE +*/ + +#ifndef CLK_MP1_CFG_CLOCK_DEFAULT_H +#define CLK_MP1_CFG_CLOCK_DEFAULT_H + +#if defined(CPU_LINE_STM32MP157Cxx) +#include "mp1/cfg_clock_default_208.h" +#else +#error "No clock configuration available for this family" +#endif + +#ifdef __cplusplus +extern "C" { +#endif + +#ifdef __cplusplus +} +#endif + +#endif /* CLK_MP1_CFG_CLOCK_DEFAULT_H */ +/** @} */ diff --git a/cpu/stm32/include/clk/mp1/cfg_clock_default_208.h b/cpu/stm32/include/clk/mp1/cfg_clock_default_208.h new file mode 100644 index 0000000000..4e52f5ff5f --- /dev/null +++ b/cpu/stm32/include/clk/mp1/cfg_clock_default_208.h @@ -0,0 +1,85 @@ +/* + * Copyright (C) 2020 Savoir-faire Linux + * + * This file is subject to the terms and conditions of the GNU Lesser General + * Public License v2.1. See the file LICENSE in the top level directory for more + * details. + */ + +/** + * @ingroup boards_common_stm32 + * @{ + * + * @file + * @brief Default STM32MP1 clock configuration for 208MHz boards + * + * @author Gilles DOFFE + */ + +#ifndef CLK_MP1_CFG_CLOCK_DEFAULT_208_H +#define CLK_MP1_CFG_CLOCK_DEFAULT_208_H + +#include "mp1/cfg_clock_common.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @name Clock PLL settings (208MHz) + * @{ + */ +/* The following parameters configure a 208MHz system clock with HSE (24MHz) + * or HSI (16MHz) as PLL input clock */ +#ifndef CONFIG_CLOCK_PLL_M +#define CONFIG_CLOCK_PLL_M (2) +#endif +#if IS_ACTIVE(CONFIG_BOARD_HAS_HSE) && (CLOCK_HSE == MHZ(24)) +#ifndef CONFIG_CLOCK_PLL_N +#define CONFIG_CLOCK_PLL_N (52) +#endif +#else /* HSI */ +#ifndef CONFIG_CLOCK_PLL_N +#define CONFIG_CLOCK_PLL_N (78) +#endif +#endif +#ifndef CONFIG_CLOCK_PLL_P +#define CONFIG_CLOCK_PLL_P (3) +#endif +#ifndef CONFIG_CLOCK_PLL_Q +#define CONFIG_CLOCK_PLL_Q (13) +#endif +#ifndef CONFIG_CLOCK_PLL_R +#define CONFIG_CLOCK_PLL_R (3) +#endif +/** @} */ + +/** + * @name Clock bus settings (MCU, APB1, APB2 and APB3) + */ +#ifndef CONFIG_CLOCK_MCU_DIV +#define CONFIG_CLOCK_MCU_DIV (1) /* max 208MHz */ +#endif +#ifndef CONFIG_CLOCK_APB1_DIV +#define CONFIG_CLOCK_APB1_DIV (2) /* max 104MHz */ +#endif +#ifndef CONFIG_CLOCK_APB2_DIV +#define CONFIG_CLOCK_APB2_DIV (2) /* max 104MHz */ +#endif +#ifndef CONFIG_CLOCK_APB3_DIV +#define CONFIG_CLOCK_APB3_DIV (2) /* max 104MHz */ +#endif +/** @} */ + +#ifdef __cplusplus +} +#endif + +#include "mp1/cfg_clock_values.h" + +#if CLOCK_CORECLOCK > MHZ(208) +#error "SYSCLK cannot exceed 208MHz" +#endif + +#endif /* CLK_MP1_CFG_CLOCK_DEFAULT_208_H */ +/** @} */ diff --git a/cpu/stm32/include/clk/mp1/cfg_clock_values.h b/cpu/stm32/include/clk/mp1/cfg_clock_values.h new file mode 100644 index 0000000000..d58d7cc7f4 --- /dev/null +++ b/cpu/stm32/include/clk/mp1/cfg_clock_values.h @@ -0,0 +1,65 @@ +/* + * Copyright (C) 2020 Savoir-faire Linux + * + * This file is subject to the terms and conditions of the GNU Lesser General + * Public License v2.1. See the file LICENSE in the top level directory for more + * details. + */ + +/** + * @ingroup boards_common_stm32 + * @{ + * + * @file + * @brief STM32MP1 clock values definitions + * + * @author Gilles DOFFE + */ + +#ifndef CLK_MP1_CFG_CLOCK_VALUES_H +#define CLK_MP1_CFG_CLOCK_VALUES_H + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @name Clock values + * @{ + */ +#if IS_ACTIVE(CONFIG_BOARD_HAS_HSE) +#define CLOCK_PLL_SRC (CLOCK_HSE) +#else /* CLOCK_HSI */ +#define CLOCK_PLL_SRC (CLOCK_HSI) +#endif + +#if IS_ACTIVE(CONFIG_USE_CLOCK_HSI) +#define CLOCK_CORECLOCK (CLOCK_HSI) + +#elif IS_ACTIVE(CONFIG_USE_CLOCK_HSE) +#if !IS_ACTIVE(CONFIG_BOARD_HAS_HSE) +#error "The board doesn't provide an HSE oscillator" +#endif +#define CLOCK_CORECLOCK (CLOCK_HSE) + +#elif IS_ACTIVE(CONFIG_USE_CLOCK_PLL) +#define CLOCK_CORECLOCK (((CLOCK_PLL_SRC / CONFIG_CLOCK_PLL_M) \ + * CONFIG_CLOCK_PLL_N) / CONFIG_CLOCK_PLL_P) +#endif /* CONFIG_USE_CLOCK_PLL */ + +#define CLOCK_PLLQ (((CLOCK_PLL_SRC / CONFIG_CLOCK_PLL_M) \ + * CONFIG_CLOCK_PLL_N) / CONFIG_CLOCK_PLL_Q) + +#define CLOCK_APB1 (CLOCK_CORECLOCK \ + / CONFIG_CLOCK_APB1_DIV) +#define CLOCK_APB2 (CLOCK_CORECLOCK \ + / CONFIG_CLOCK_APB2_DIV) +/** @} */ + + +#ifdef __cplusplus +} +#endif + +#endif /* CLK_MP1_CFG_CLOCK_VALUES_H */ +/** @} */