From 2c04d6cefe2d0c6566f474a0b08f3ceacab13a63 Mon Sep 17 00:00:00 2001 From: Benjamin Valentin Date: Thu, 9 Jun 2022 18:27:30 +0200 Subject: [PATCH] cpu/samd21: handle silicon errata - The `periph_flashpage` driver expects the manual write bit to be set This should be set by default, but the SAM D20/SAM D21 errata sheets correct that this is indeed *not* set by default, which may cause spurious writes. - SAM D20 may not wake up from any sleep mode if sleep power reduction is enabled for the NVM block. --- cpu/samd21/cpu.c | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/cpu/samd21/cpu.c b/cpu/samd21/cpu.c index 71aac9ddce..010fb8a674 100644 --- a/cpu/samd21/cpu.c +++ b/cpu/samd21/cpu.c @@ -117,7 +117,14 @@ static void clk_init(void) /* adjust NVM wait states */ PM->APBBMASK.reg |= PM_APBBMASK_NVMCTRL; - NVMCTRL->CTRLB.reg |= NVMCTRL_CTRLB_RWS(WAITSTATES); + NVMCTRL->CTRLB.reg = NVMCTRL_CTRLB_RWS(WAITSTATES) +#ifdef CPU_SAMD20 + /* errata: In Standby, Idle1 and Idle2 Sleep modes, + the device might not wake up from sleep. */ + | NVMCTRL_CTRLB_SLEEPPRM_DISABLED +#endif + /* errata: Default value of MANW in NVM.CTRLB is 0. */ + | NVMCTRL_CTRLB_MANW; PM->APBBMASK.reg &= ~PM_APBBMASK_NVMCTRL; #if CLOCK_8MHZ