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cpu/efm32/wdt: add series 2 support
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@ -30,6 +30,10 @@ config CPU_EFM32_SERIES1
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bool
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bool
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select HAS_PERIPH_WDT_CB
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select HAS_PERIPH_WDT_CB
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config CPU_EFM32_SERIES2
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bool
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select HAS_PERIPH_WDT_CB
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## Definition of specific features
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## Definition of specific features
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config HAS_ARCH_EFM32
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config HAS_ARCH_EFM32
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bool
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bool
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@ -32,7 +32,7 @@ ifeq (1,$(EFM32_TRNG))
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FEATURES_PROVIDED += periph_hwrng
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FEATURES_PROVIDED += periph_hwrng
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endif
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endif
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ifeq (1,$(EFM32_SERIES))
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ifneq (,$(filter $(EFM32_SERIES),1 2))
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FEATURES_PROVIDED += periph_wdt_cb
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FEATURES_PROVIDED += periph_wdt_cb
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endif
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endif
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@ -507,7 +507,7 @@ typedef struct {
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#define NWDT_TIME_LOWER_LIMIT ((1U << (3U + wdogPeriod_9)) + 1U)
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#define NWDT_TIME_LOWER_LIMIT ((1U << (3U + wdogPeriod_9)) + 1U)
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#define NWDT_TIME_UPPER_LIMIT ((1U << (3U + wdogPeriod_256k)) + 1U)
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#define NWDT_TIME_UPPER_LIMIT ((1U << (3U + wdogPeriod_256k)) + 1U)
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#ifdef _SILICON_LABS_32B_SERIES_1
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#if defined(_SILICON_LABS_32B_SERIES_1) || defined(_SILICON_LABS_32B_SERIES_2)
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#define WDT_TIME_LOWER_LIMIT NWDT_TIME_LOWER_LIMIT
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#define WDT_TIME_LOWER_LIMIT NWDT_TIME_LOWER_LIMIT
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#define WDT_TIME_UPPER_LIMIT NWDT_TIME_UPPER_LIMIT
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#define WDT_TIME_UPPER_LIMIT NWDT_TIME_UPPER_LIMIT
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#endif
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#endif
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@ -49,8 +49,8 @@ endif
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ifneq (,$(filter periph_wdt,$(USEMODULE)))
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ifneq (,$(filter periph_wdt,$(USEMODULE)))
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ifeq (0,$(EFM32_SERIES))
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ifeq (0,$(EFM32_SERIES))
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SRC += wdt_series0.c
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SRC += wdt_series0.c
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else ifeq (1,$(EFM32_SERIES))
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else ifneq (,$(filter $(EFM32_SERIES),1 2))
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SRC += wdt_series1.c
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SRC += wdt_series12.c
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endif
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endif
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endif
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endif
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@ -16,6 +16,7 @@
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* EFM32 Series 1 MCUs
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* EFM32 Series 1 MCUs
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*
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*
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* @author Bas Stottelaar <basstottelaar@gmail.com>
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* @author Bas Stottelaar <basstottelaar@gmail.com>
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* @author Juergen Fitschen <me@jue.yt>
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* @}
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* @}
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*/
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*/
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@ -41,14 +42,23 @@ static wdt_cb_t wdt_cb;
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static void *wdt_arg;
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static void *wdt_arg;
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#endif
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#endif
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static inline uint32_t _get_clock(void)
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{
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#if defined(_SILICON_LABS_32B_SERIES_0) || defined(_SILICON_LABS_32B_SERIES_1)
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return WDT_CLOCK_HZ;
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#else
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return CMU_ClockFreqGet(cmuClock_WDOG0);
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#endif
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}
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static uint32_t _get_calculated_time(WDOG_PeriodSel_TypeDef period)
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static uint32_t _get_calculated_time(WDOG_PeriodSel_TypeDef period)
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{
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{
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return ((1 << (3 + (int)period)) + 1) / WDT_CLOCK_HZ * MS_PER_SEC;
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return ((1 << (3 + (int)period)) + 1) / _get_clock() * MS_PER_SEC;
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}
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}
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static WDOG_PeriodSel_TypeDef _get_period(uint32_t max_time)
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static WDOG_PeriodSel_TypeDef _get_period(uint32_t max_time)
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{
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{
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const uint32_t cycles = (max_time * WDT_CLOCK_HZ) / MS_PER_SEC;
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const uint32_t cycles = (max_time * _get_clock()) / MS_PER_SEC;
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DEBUG("[wdt_series1] _get_period: cycles=%" PRIu32 "\n", cycles);
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DEBUG("[wdt_series1] _get_period: cycles=%" PRIu32 "\n", cycles);
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@ -92,14 +102,25 @@ static void _init(uint32_t min_time, uint32_t max_time, bool warn)
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}
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}
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/* initialize clock */
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/* initialize clock */
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#if defined(_SILICON_LABS_32B_SERIES_0) || defined(_SILICON_LABS_32B_SERIES_1)
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CMU_ClockEnable(cmuClock_HFLE, true);
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CMU_ClockEnable(cmuClock_HFLE, true);
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#else
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CMU_ClockSelectSet(cmuClock_WDOG0CLK, cmuSelect_ULFRCO);
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CMU_ClockEnable(cmuClock_WDOG0, true);
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#endif
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/* initialize watchdog */
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/* initialize watchdog */
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WDOG_Init_TypeDef init = WDOG_INIT_DEFAULT;
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WDOG_Init_TypeDef init = WDOG_INIT_DEFAULT;
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init.enable = false;
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init.enable = false;
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#if defined(_WDOG_CFG_EM1RUN_MASK)
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init.em1Run = true;
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#endif
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init.em2Run = true;
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init.em2Run = true;
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init.em3Run = true;
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#if defined(_SILICON_LABS_32B_SERIES_0) || defined(_SILICON_LABS_32B_SERIES_1)
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init.clkSel = wdogClkSelULFRCO;
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init.clkSel = wdogClkSelULFRCO;
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#endif
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init.perSel = _get_period(max_time);
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init.perSel = _get_period(max_time);
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uint32_t calculated_time = _get_calculated_time(init.perSel);
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uint32_t calculated_time = _get_calculated_time(init.perSel);
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