kaspar/RIOT
1
0
Fork 0
mirror of https://github.com/RIOT-OS/RIOT.git synced 2025-12-25 14:33:52 +01:00
Code Releases Activity

cpu/samd21: cleanup XOSC32K initialization

Browse Source
This commit is contained in:
Francisco Molina 2020-02-07 15:45:57 +01:00
parent 9ab22b6926
commit 2e542a2488
No known key found for this signature in database
GPG Key ID: 3E94EAC3DBDEEDA8
1 changed files with 21 additions and 16 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

37
cpu/samd21/cpu.c
View File

@ -35,6 +35,16 @@
#define GEN3_ULP32K 1
#endif
#ifndef XOSC32_STARTUP_TIME
/**
* @brief XOSC32 start up time
*
* @note Override this value in your boards periph_conf.h file
* if a different start up time is to be used.
*/
#define XOSC32_STARTUP_TIME 6
#endif
#ifndef VDD
/**
* @brief Set system voltage level in mV (determines flash wait states)
@ -98,6 +108,17 @@ static void clk_init(void)
while (!(SYSCTRL->PCLKSR.reg & SYSCTRL_PCLKSR_OSC8MRDY)) {}
#endif
#if CLOCK_USE_XOSC32_DFLL || !GEN2_ULP32K || !GEN4_ULP32K
/* Use External 32.768KHz Oscillator */
SYSCTRL->XOSC32K.reg = SYSCTRL_XOSC32K_ONDEMAND |
SYSCTRL_XOSC32K_EN32K |
SYSCTRL_XOSC32K_XTALEN |
SYSCTRL_XOSC32K_STARTUP(XOSC32_STARTUP_TIME) |
SYSCTRL_XOSC32K_RUNSTDBY;
/* Enable XOSC32 with Separate Call */
SYSCTRL->XOSC32K.bit.ENABLE = 1;
#endif
/* Setup GCLK2 with divider 1 (32.768kHz) */
GCLK->GENDIV.reg = (GCLK_GENDIV_ID(SAM0_GCLK_32KHZ) | GCLK_GENDIV_DIV(0));
GCLK->GENCTRL.reg = (GCLK_GENCTRL_ID(SAM0_GCLK_32KHZ) | GCLK_GENCTRL_GENEN
@ -106,12 +127,6 @@ static void clk_init(void)
| GCLK_GENCTRL_SRC_OSCULP32K);
#else
| GCLK_GENCTRL_SRC_XOSC32K);
SYSCTRL->XOSC32K.reg = SYSCTRL_XOSC32K_ONDEMAND
| SYSCTRL_XOSC32K_EN32K
| SYSCTRL_XOSC32K_XTALEN
| SYSCTRL_XOSC32K_STARTUP(6)
| SYSCTRL_XOSC32K_ENABLE;
#endif
#if CLOCK_USE_PLL
@ -144,16 +159,6 @@ static void clk_init(void)
GCLK_GENCTRL_SRC_FDPLL |
GCLK_GENCTRL_ID(SAM0_GCLK_MAIN));
#elif CLOCK_USE_XOSC32_DFLL
/* Use External 32.768KHz Oscillator */
SYSCTRL->XOSC32K.reg = SYSCTRL_XOSC32K_ONDEMAND |
SYSCTRL_XOSC32K_EN32K |
SYSCTRL_XOSC32K_XTALEN |
SYSCTRL_XOSC32K_STARTUP(6) |
SYSCTRL_XOSC32K_RUNSTDBY;
/* Enable with Separate Call */
SYSCTRL->XOSC32K.bit.ENABLE = 1;
/* reset the GCLK module so it is in a known state */
GCLK->CTRL.reg = GCLK_CTRL_SWRST;
while (GCLK->STATUS.reg & GCLK_STATUS_SYNCBUSY) {}