diff --git a/cpu/efm32/families/efm32gg/include/vendor/efm32gg990f1024.h b/cpu/efm32/families/efm32gg/include/vendor/efm32gg990f1024.h
index 95e29f2e11..f7ee1c65e7 100644
--- a/cpu/efm32/families/efm32gg/include/vendor/efm32gg990f1024.h
+++ b/cpu/efm32/families/efm32gg/include/vendor/efm32gg990f1024.h
@@ -2,10 +2,9 @@
* @file
* @brief CMSIS Cortex-M Peripheral Access Layer Header File
* for EFM32GG990F1024
- * @version 5.8.3
*******************************************************************************
* # License
- * Copyright 2019 Silicon Laboratories Inc. www.silabs.com
+ * Copyright 2020 Silicon Laboratories Inc. www.silabs.com
*******************************************************************************
*
* SPDX-License-Identifier: Zlib
@@ -144,6 +143,30 @@ typedef enum IRQn{
#define PART_NUMBER "EFM32GG990F1024" /**< Part Number */
/** Memory Base addresses and limits */
+#define RAM_MEM_BASE (0x20000000UL) /**< RAM base address */
+#define RAM_MEM_SIZE (0x40000UL) /**< RAM available address space */
+#define RAM_MEM_END (0x2003FFFFUL) /**< RAM end address */
+#define RAM_MEM_BITS (0x18UL) /**< RAM used bits */
+#define EBI_CODE_MEM_BASE (0x12000000UL) /**< EBI_CODE base address */
+#define EBI_CODE_MEM_SIZE (0xE000000UL) /**< EBI_CODE available address space */
+#define EBI_CODE_MEM_END (0x1FFFFFFFUL) /**< EBI_CODE end address */
+#define EBI_CODE_MEM_BITS (0x28UL) /**< EBI_CODE used bits */
+#define USBC_MEM_BASE (0x40100000UL) /**< USBC base address */
+#define USBC_MEM_SIZE (0x40000UL) /**< USBC available address space */
+#define USBC_MEM_END (0x4013FFFFUL) /**< USBC end address */
+#define USBC_MEM_BITS (0x18UL) /**< USBC used bits */
+#define RAM_CODE_MEM_BASE (0x10000000UL) /**< RAM_CODE base address */
+#define RAM_CODE_MEM_SIZE (0x20000UL) /**< RAM_CODE available address space */
+#define RAM_CODE_MEM_END (0x1001FFFFUL) /**< RAM_CODE end address */
+#define RAM_CODE_MEM_BITS (0x17UL) /**< RAM_CODE used bits */
+#define PER_MEM_BASE (0x40000000UL) /**< PER base address */
+#define PER_MEM_SIZE (0xE0000UL) /**< PER available address space */
+#define PER_MEM_END (0x400DFFFFUL) /**< PER end address */
+#define PER_MEM_BITS (0x20UL) /**< PER used bits */
+#define EBI_MEM_BASE (0x80000000UL) /**< EBI base address */
+#define EBI_MEM_SIZE (0x40000000UL) /**< EBI available address space */
+#define EBI_MEM_END (0xBFFFFFFFUL) /**< EBI end address */
+#define EBI_MEM_BITS (0x30UL) /**< EBI used bits */
#define FLASH_MEM_BASE (0x0UL) /**< FLASH base address */
#define FLASH_MEM_SIZE (0x10000000UL) /**< FLASH available address space */
#define FLASH_MEM_END (0xFFFFFFFUL) /**< FLASH end address */
@@ -152,30 +175,6 @@ typedef enum IRQn{
#define AES_MEM_SIZE (0x400UL) /**< AES available address space */
#define AES_MEM_END (0x400E03FFUL) /**< AES end address */
#define AES_MEM_BITS (0x10UL) /**< AES used bits */
-#define USBC_MEM_BASE (0x40100000UL) /**< USBC base address */
-#define USBC_MEM_SIZE (0x40000UL) /**< USBC available address space */
-#define USBC_MEM_END (0x4013FFFFUL) /**< USBC end address */
-#define USBC_MEM_BITS (0x18UL) /**< USBC used bits */
-#define EBI_CODE_MEM_BASE (0x12000000UL) /**< EBI_CODE base address */
-#define EBI_CODE_MEM_SIZE (0xE000000UL) /**< EBI_CODE available address space */
-#define EBI_CODE_MEM_END (0x1FFFFFFFUL) /**< EBI_CODE end address */
-#define EBI_CODE_MEM_BITS (0x28UL) /**< EBI_CODE used bits */
-#define PER_MEM_BASE (0x40000000UL) /**< PER base address */
-#define PER_MEM_SIZE (0xE0000UL) /**< PER available address space */
-#define PER_MEM_END (0x400DFFFFUL) /**< PER end address */
-#define PER_MEM_BITS (0x20UL) /**< PER used bits */
-#define RAM_MEM_BASE (0x20000000UL) /**< RAM base address */
-#define RAM_MEM_SIZE (0x40000UL) /**< RAM available address space */
-#define RAM_MEM_END (0x2003FFFFUL) /**< RAM end address */
-#define RAM_MEM_BITS (0x18UL) /**< RAM used bits */
-#define RAM_CODE_MEM_BASE (0x10000000UL) /**< RAM_CODE base address */
-#define RAM_CODE_MEM_SIZE (0x20000UL) /**< RAM_CODE available address space */
-#define RAM_CODE_MEM_END (0x1001FFFFUL) /**< RAM_CODE end address */
-#define RAM_CODE_MEM_BITS (0x17UL) /**< RAM_CODE used bits */
-#define EBI_MEM_BASE (0x80000000UL) /**< EBI base address */
-#define EBI_MEM_SIZE (0x40000000UL) /**< EBI available address space */
-#define EBI_MEM_END (0xBFFFFFFFUL) /**< EBI end address */
-#define EBI_MEM_BITS (0x30UL) /**< EBI used bits */
/** Bit banding area */
#define BITBAND_PER_BASE (0x42000000UL) /**< Peripheral Address Space bit-band area */
diff --git a/cpu/efm32/families/efm32gg/include/vendor/efm32gg_acmp.h b/cpu/efm32/families/efm32gg/include/vendor/efm32gg_acmp.h
index f2cf7ad0c5..c514936e13 100644
--- a/cpu/efm32/families/efm32gg/include/vendor/efm32gg_acmp.h
+++ b/cpu/efm32/families/efm32gg/include/vendor/efm32gg_acmp.h
@@ -1,10 +1,9 @@
/***************************************************************************//**
* @file
* @brief EFM32GG_ACMP register and bit field definitions
- * @version 5.8.3
*******************************************************************************
* # License
- * Copyright 2019 Silicon Laboratories Inc. www.silabs.com
+ * Copyright 2020 Silicon Laboratories Inc. www.silabs.com
*******************************************************************************
*
* SPDX-License-Identifier: Zlib
diff --git a/cpu/efm32/families/efm32gg/include/vendor/efm32gg_adc.h b/cpu/efm32/families/efm32gg/include/vendor/efm32gg_adc.h
index aa442c2199..ecfac21281 100644
--- a/cpu/efm32/families/efm32gg/include/vendor/efm32gg_adc.h
+++ b/cpu/efm32/families/efm32gg/include/vendor/efm32gg_adc.h
@@ -1,10 +1,9 @@
/***************************************************************************//**
* @file
* @brief EFM32GG_ADC register and bit field definitions
- * @version 5.8.3
*******************************************************************************
* # License
- * Copyright 2019 Silicon Laboratories Inc. www.silabs.com
+ * Copyright 2020 Silicon Laboratories Inc. www.silabs.com
*******************************************************************************
*
* SPDX-License-Identifier: Zlib
@@ -263,16 +262,16 @@ typedef struct {
#define _ADC_SINGLECTRL_INPUTSEL_SHIFT 8 /**< Shift value for ADC_INPUTSEL */
#define _ADC_SINGLECTRL_INPUTSEL_MASK 0xF00UL /**< Bit mask for ADC_INPUTSEL */
#define _ADC_SINGLECTRL_INPUTSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SINGLECTRL */
-#define _ADC_SINGLECTRL_INPUTSEL_CH0 0x00000000UL /**< Mode CH0 for ADC_SINGLECTRL */
#define _ADC_SINGLECTRL_INPUTSEL_CH0CH1 0x00000000UL /**< Mode CH0CH1 for ADC_SINGLECTRL */
-#define _ADC_SINGLECTRL_INPUTSEL_CH1 0x00000001UL /**< Mode CH1 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_INPUTSEL_CH0 0x00000000UL /**< Mode CH0 for ADC_SINGLECTRL */
#define _ADC_SINGLECTRL_INPUTSEL_CH2CH3 0x00000001UL /**< Mode CH2CH3 for ADC_SINGLECTRL */
-#define _ADC_SINGLECTRL_INPUTSEL_CH2 0x00000002UL /**< Mode CH2 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_INPUTSEL_CH1 0x00000001UL /**< Mode CH1 for ADC_SINGLECTRL */
#define _ADC_SINGLECTRL_INPUTSEL_CH4CH5 0x00000002UL /**< Mode CH4CH5 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_INPUTSEL_CH2 0x00000002UL /**< Mode CH2 for ADC_SINGLECTRL */
#define _ADC_SINGLECTRL_INPUTSEL_CH6CH7 0x00000003UL /**< Mode CH6CH7 for ADC_SINGLECTRL */
#define _ADC_SINGLECTRL_INPUTSEL_CH3 0x00000003UL /**< Mode CH3 for ADC_SINGLECTRL */
-#define _ADC_SINGLECTRL_INPUTSEL_CH4 0x00000004UL /**< Mode CH4 for ADC_SINGLECTRL */
#define _ADC_SINGLECTRL_INPUTSEL_DIFF0 0x00000004UL /**< Mode DIFF0 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_INPUTSEL_CH4 0x00000004UL /**< Mode CH4 for ADC_SINGLECTRL */
#define _ADC_SINGLECTRL_INPUTSEL_CH5 0x00000005UL /**< Mode CH5 for ADC_SINGLECTRL */
#define _ADC_SINGLECTRL_INPUTSEL_CH6 0x00000006UL /**< Mode CH6 for ADC_SINGLECTRL */
#define _ADC_SINGLECTRL_INPUTSEL_CH7 0x00000007UL /**< Mode CH7 for ADC_SINGLECTRL */
@@ -284,16 +283,16 @@ typedef struct {
#define _ADC_SINGLECTRL_INPUTSEL_DAC0OUT0 0x0000000DUL /**< Mode DAC0OUT0 for ADC_SINGLECTRL */
#define _ADC_SINGLECTRL_INPUTSEL_DAC0OUT1 0x0000000EUL /**< Mode DAC0OUT1 for ADC_SINGLECTRL */
#define ADC_SINGLECTRL_INPUTSEL_DEFAULT (_ADC_SINGLECTRL_INPUTSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for ADC_SINGLECTRL */
-#define ADC_SINGLECTRL_INPUTSEL_CH0 (_ADC_SINGLECTRL_INPUTSEL_CH0 << 8) /**< Shifted mode CH0 for ADC_SINGLECTRL */
#define ADC_SINGLECTRL_INPUTSEL_CH0CH1 (_ADC_SINGLECTRL_INPUTSEL_CH0CH1 << 8) /**< Shifted mode CH0CH1 for ADC_SINGLECTRL */
-#define ADC_SINGLECTRL_INPUTSEL_CH1 (_ADC_SINGLECTRL_INPUTSEL_CH1 << 8) /**< Shifted mode CH1 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_INPUTSEL_CH0 (_ADC_SINGLECTRL_INPUTSEL_CH0 << 8) /**< Shifted mode CH0 for ADC_SINGLECTRL */
#define ADC_SINGLECTRL_INPUTSEL_CH2CH3 (_ADC_SINGLECTRL_INPUTSEL_CH2CH3 << 8) /**< Shifted mode CH2CH3 for ADC_SINGLECTRL */
-#define ADC_SINGLECTRL_INPUTSEL_CH2 (_ADC_SINGLECTRL_INPUTSEL_CH2 << 8) /**< Shifted mode CH2 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_INPUTSEL_CH1 (_ADC_SINGLECTRL_INPUTSEL_CH1 << 8) /**< Shifted mode CH1 for ADC_SINGLECTRL */
#define ADC_SINGLECTRL_INPUTSEL_CH4CH5 (_ADC_SINGLECTRL_INPUTSEL_CH4CH5 << 8) /**< Shifted mode CH4CH5 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_INPUTSEL_CH2 (_ADC_SINGLECTRL_INPUTSEL_CH2 << 8) /**< Shifted mode CH2 for ADC_SINGLECTRL */
#define ADC_SINGLECTRL_INPUTSEL_CH6CH7 (_ADC_SINGLECTRL_INPUTSEL_CH6CH7 << 8) /**< Shifted mode CH6CH7 for ADC_SINGLECTRL */
#define ADC_SINGLECTRL_INPUTSEL_CH3 (_ADC_SINGLECTRL_INPUTSEL_CH3 << 8) /**< Shifted mode CH3 for ADC_SINGLECTRL */
-#define ADC_SINGLECTRL_INPUTSEL_CH4 (_ADC_SINGLECTRL_INPUTSEL_CH4 << 8) /**< Shifted mode CH4 for ADC_SINGLECTRL */
#define ADC_SINGLECTRL_INPUTSEL_DIFF0 (_ADC_SINGLECTRL_INPUTSEL_DIFF0 << 8) /**< Shifted mode DIFF0 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_INPUTSEL_CH4 (_ADC_SINGLECTRL_INPUTSEL_CH4 << 8) /**< Shifted mode CH4 for ADC_SINGLECTRL */
#define ADC_SINGLECTRL_INPUTSEL_CH5 (_ADC_SINGLECTRL_INPUTSEL_CH5 << 8) /**< Shifted mode CH5 for ADC_SINGLECTRL */
#define ADC_SINGLECTRL_INPUTSEL_CH6 (_ADC_SINGLECTRL_INPUTSEL_CH6 << 8) /**< Shifted mode CH6 for ADC_SINGLECTRL */
#define ADC_SINGLECTRL_INPUTSEL_CH7 (_ADC_SINGLECTRL_INPUTSEL_CH7 << 8) /**< Shifted mode CH7 for ADC_SINGLECTRL */
@@ -415,12 +414,12 @@ typedef struct {
#define _ADC_SCANCTRL_INPUTMASK_SHIFT 8 /**< Shift value for ADC_INPUTMASK */
#define _ADC_SCANCTRL_INPUTMASK_MASK 0xFF00UL /**< Bit mask for ADC_INPUTMASK */
#define _ADC_SCANCTRL_INPUTMASK_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SCANCTRL */
-#define _ADC_SCANCTRL_INPUTMASK_CH0 0x00000001UL /**< Mode CH0 for ADC_SCANCTRL */
#define _ADC_SCANCTRL_INPUTMASK_CH0CH1 0x00000001UL /**< Mode CH0CH1 for ADC_SCANCTRL */
-#define _ADC_SCANCTRL_INPUTMASK_CH1 0x00000002UL /**< Mode CH1 for ADC_SCANCTRL */
+#define _ADC_SCANCTRL_INPUTMASK_CH0 0x00000001UL /**< Mode CH0 for ADC_SCANCTRL */
#define _ADC_SCANCTRL_INPUTMASK_CH2CH3 0x00000002UL /**< Mode CH2CH3 for ADC_SCANCTRL */
-#define _ADC_SCANCTRL_INPUTMASK_CH2 0x00000004UL /**< Mode CH2 for ADC_SCANCTRL */
+#define _ADC_SCANCTRL_INPUTMASK_CH1 0x00000002UL /**< Mode CH1 for ADC_SCANCTRL */
#define _ADC_SCANCTRL_INPUTMASK_CH4CH5 0x00000004UL /**< Mode CH4CH5 for ADC_SCANCTRL */
+#define _ADC_SCANCTRL_INPUTMASK_CH2 0x00000004UL /**< Mode CH2 for ADC_SCANCTRL */
#define _ADC_SCANCTRL_INPUTMASK_CH6CH7 0x00000008UL /**< Mode CH6CH7 for ADC_SCANCTRL */
#define _ADC_SCANCTRL_INPUTMASK_CH3 0x00000008UL /**< Mode CH3 for ADC_SCANCTRL */
#define _ADC_SCANCTRL_INPUTMASK_CH4 0x00000010UL /**< Mode CH4 for ADC_SCANCTRL */
@@ -428,12 +427,12 @@ typedef struct {
#define _ADC_SCANCTRL_INPUTMASK_CH6 0x00000040UL /**< Mode CH6 for ADC_SCANCTRL */
#define _ADC_SCANCTRL_INPUTMASK_CH7 0x00000080UL /**< Mode CH7 for ADC_SCANCTRL */
#define ADC_SCANCTRL_INPUTMASK_DEFAULT (_ADC_SCANCTRL_INPUTMASK_DEFAULT << 8) /**< Shifted mode DEFAULT for ADC_SCANCTRL */
-#define ADC_SCANCTRL_INPUTMASK_CH0 (_ADC_SCANCTRL_INPUTMASK_CH0 << 8) /**< Shifted mode CH0 for ADC_SCANCTRL */
#define ADC_SCANCTRL_INPUTMASK_CH0CH1 (_ADC_SCANCTRL_INPUTMASK_CH0CH1 << 8) /**< Shifted mode CH0CH1 for ADC_SCANCTRL */
-#define ADC_SCANCTRL_INPUTMASK_CH1 (_ADC_SCANCTRL_INPUTMASK_CH1 << 8) /**< Shifted mode CH1 for ADC_SCANCTRL */
+#define ADC_SCANCTRL_INPUTMASK_CH0 (_ADC_SCANCTRL_INPUTMASK_CH0 << 8) /**< Shifted mode CH0 for ADC_SCANCTRL */
#define ADC_SCANCTRL_INPUTMASK_CH2CH3 (_ADC_SCANCTRL_INPUTMASK_CH2CH3 << 8) /**< Shifted mode CH2CH3 for ADC_SCANCTRL */
-#define ADC_SCANCTRL_INPUTMASK_CH2 (_ADC_SCANCTRL_INPUTMASK_CH2 << 8) /**< Shifted mode CH2 for ADC_SCANCTRL */
+#define ADC_SCANCTRL_INPUTMASK_CH1 (_ADC_SCANCTRL_INPUTMASK_CH1 << 8) /**< Shifted mode CH1 for ADC_SCANCTRL */
#define ADC_SCANCTRL_INPUTMASK_CH4CH5 (_ADC_SCANCTRL_INPUTMASK_CH4CH5 << 8) /**< Shifted mode CH4CH5 for ADC_SCANCTRL */
+#define ADC_SCANCTRL_INPUTMASK_CH2 (_ADC_SCANCTRL_INPUTMASK_CH2 << 8) /**< Shifted mode CH2 for ADC_SCANCTRL */
#define ADC_SCANCTRL_INPUTMASK_CH6CH7 (_ADC_SCANCTRL_INPUTMASK_CH6CH7 << 8) /**< Shifted mode CH6CH7 for ADC_SCANCTRL */
#define ADC_SCANCTRL_INPUTMASK_CH3 (_ADC_SCANCTRL_INPUTMASK_CH3 << 8) /**< Shifted mode CH3 for ADC_SCANCTRL */
#define ADC_SCANCTRL_INPUTMASK_CH4 (_ADC_SCANCTRL_INPUTMASK_CH4 << 8) /**< Shifted mode CH4 for ADC_SCANCTRL */
diff --git a/cpu/efm32/families/efm32gg/include/vendor/efm32gg_aes.h b/cpu/efm32/families/efm32gg/include/vendor/efm32gg_aes.h
index 0ca7e8b557..88b7cb03b6 100644
--- a/cpu/efm32/families/efm32gg/include/vendor/efm32gg_aes.h
+++ b/cpu/efm32/families/efm32gg/include/vendor/efm32gg_aes.h
@@ -1,10 +1,9 @@
/***************************************************************************//**
* @file
* @brief EFM32GG_AES register and bit field definitions
- * @version 5.8.3
*******************************************************************************
* # License
- * Copyright 2019 Silicon Laboratories Inc. www.silabs.com
+ * Copyright 2020 Silicon Laboratories Inc. www.silabs.com
*******************************************************************************
*
* SPDX-License-Identifier: Zlib
diff --git a/cpu/efm32/families/efm32gg/include/vendor/efm32gg_af_pins.h b/cpu/efm32/families/efm32gg/include/vendor/efm32gg_af_pins.h
index caaa5ed13e..4d20dc3331 100644
--- a/cpu/efm32/families/efm32gg/include/vendor/efm32gg_af_pins.h
+++ b/cpu/efm32/families/efm32gg/include/vendor/efm32gg_af_pins.h
@@ -1,10 +1,9 @@
/***************************************************************************//**
* @file
* @brief EFM32GG_AF_PINS register and bit field definitions
- * @version 5.8.3
*******************************************************************************
* # License
- * Copyright 2019 Silicon Laboratories Inc. www.silabs.com
+ * Copyright 2020 Silicon Laboratories Inc. www.silabs.com
*******************************************************************************
*
* SPDX-License-Identifier: Zlib
diff --git a/cpu/efm32/families/efm32gg/include/vendor/efm32gg_af_ports.h b/cpu/efm32/families/efm32gg/include/vendor/efm32gg_af_ports.h
index 9357f03cf8..7b94a55147 100644
--- a/cpu/efm32/families/efm32gg/include/vendor/efm32gg_af_ports.h
+++ b/cpu/efm32/families/efm32gg/include/vendor/efm32gg_af_ports.h
@@ -1,10 +1,9 @@
/***************************************************************************//**
* @file
* @brief EFM32GG_AF_PORTS register and bit field definitions
- * @version 5.8.3
*******************************************************************************
* # License
- * Copyright 2019 Silicon Laboratories Inc. www.silabs.com
+ * Copyright 2020 Silicon Laboratories Inc. www.silabs.com
*******************************************************************************
*
* SPDX-License-Identifier: Zlib
diff --git a/cpu/efm32/families/efm32gg/include/vendor/efm32gg_burtc.h b/cpu/efm32/families/efm32gg/include/vendor/efm32gg_burtc.h
index 00babb40d3..7cda2d3f9b 100644
--- a/cpu/efm32/families/efm32gg/include/vendor/efm32gg_burtc.h
+++ b/cpu/efm32/families/efm32gg/include/vendor/efm32gg_burtc.h
@@ -1,10 +1,9 @@
/***************************************************************************//**
* @file
* @brief EFM32GG_BURTC register and bit field definitions
- * @version 5.8.3
*******************************************************************************
* # License
- * Copyright 2019 Silicon Laboratories Inc. www.silabs.com
+ * Copyright 2020 Silicon Laboratories Inc. www.silabs.com
*******************************************************************************
*
* SPDX-License-Identifier: Zlib
@@ -264,13 +263,13 @@ typedef struct {
#define _BURTC_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for BURTC_LOCKKEY */
#define _BURTC_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for BURTC_LOCKKEY */
#define _BURTC_LOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_LOCK */
-#define _BURTC_LOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for BURTC_LOCK */
#define _BURTC_LOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for BURTC_LOCK */
+#define _BURTC_LOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for BURTC_LOCK */
#define _BURTC_LOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for BURTC_LOCK */
#define _BURTC_LOCK_LOCKKEY_UNLOCK 0x0000AEE8UL /**< Mode UNLOCK for BURTC_LOCK */
#define BURTC_LOCK_LOCKKEY_DEFAULT (_BURTC_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for BURTC_LOCK */
-#define BURTC_LOCK_LOCKKEY_LOCK (_BURTC_LOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for BURTC_LOCK */
#define BURTC_LOCK_LOCKKEY_UNLOCKED (_BURTC_LOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for BURTC_LOCK */
+#define BURTC_LOCK_LOCKKEY_LOCK (_BURTC_LOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for BURTC_LOCK */
#define BURTC_LOCK_LOCKKEY_LOCKED (_BURTC_LOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for BURTC_LOCK */
#define BURTC_LOCK_LOCKKEY_UNLOCK (_BURTC_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for BURTC_LOCK */
diff --git a/cpu/efm32/families/efm32gg/include/vendor/efm32gg_burtc_ret.h b/cpu/efm32/families/efm32gg/include/vendor/efm32gg_burtc_ret.h
index e8ee898b6f..b952d5c864 100644
--- a/cpu/efm32/families/efm32gg/include/vendor/efm32gg_burtc_ret.h
+++ b/cpu/efm32/families/efm32gg/include/vendor/efm32gg_burtc_ret.h
@@ -1,10 +1,9 @@
/***************************************************************************//**
* @file
* @brief EFM32GG_BURTC_RET register and bit field definitions
- * @version 5.8.3
*******************************************************************************
* # License
- * Copyright 2019 Silicon Laboratories Inc. www.silabs.com
+ * Copyright 2020 Silicon Laboratories Inc. www.silabs.com
*******************************************************************************
*
* SPDX-License-Identifier: Zlib
diff --git a/cpu/efm32/families/efm32gg/include/vendor/efm32gg_calibrate.h b/cpu/efm32/families/efm32gg/include/vendor/efm32gg_calibrate.h
index 760c93bf47..ee1654e5ed 100644
--- a/cpu/efm32/families/efm32gg/include/vendor/efm32gg_calibrate.h
+++ b/cpu/efm32/families/efm32gg/include/vendor/efm32gg_calibrate.h
@@ -1,10 +1,9 @@
/***************************************************************************//**
* @file
* @brief EFM32GG_CALIBRATE register and bit field definitions
- * @version 5.8.3
*******************************************************************************
* # License
- * Copyright 2019 Silicon Laboratories Inc. www.silabs.com
+ * Copyright 2020 Silicon Laboratories Inc. www.silabs.com
*******************************************************************************
*
* SPDX-License-Identifier: Zlib
diff --git a/cpu/efm32/families/efm32gg/include/vendor/efm32gg_cmu.h b/cpu/efm32/families/efm32gg/include/vendor/efm32gg_cmu.h
index a4644151af..d0a5d05f8b 100644
--- a/cpu/efm32/families/efm32gg/include/vendor/efm32gg_cmu.h
+++ b/cpu/efm32/families/efm32gg/include/vendor/efm32gg_cmu.h
@@ -1,10 +1,9 @@
/***************************************************************************//**
* @file
* @brief EFM32GG_CMU register and bit field definitions
- * @version 5.8.3
*******************************************************************************
* # License
- * Copyright 2019 Silicon Laboratories Inc. www.silabs.com
+ * Copyright 2020 Silicon Laboratories Inc. www.silabs.com
*******************************************************************************
*
* SPDX-License-Identifier: Zlib
@@ -1247,13 +1246,13 @@ typedef struct {
#define _CMU_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for CMU_LOCKKEY */
#define _CMU_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for CMU_LOCKKEY */
#define _CMU_LOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LOCK */
-#define _CMU_LOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for CMU_LOCK */
#define _CMU_LOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for CMU_LOCK */
+#define _CMU_LOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for CMU_LOCK */
#define _CMU_LOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for CMU_LOCK */
#define _CMU_LOCK_LOCKKEY_UNLOCK 0x0000580EUL /**< Mode UNLOCK for CMU_LOCK */
#define CMU_LOCK_LOCKKEY_DEFAULT (_CMU_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LOCK */
-#define CMU_LOCK_LOCKKEY_LOCK (_CMU_LOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for CMU_LOCK */
#define CMU_LOCK_LOCKKEY_UNLOCKED (_CMU_LOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for CMU_LOCK */
+#define CMU_LOCK_LOCKKEY_LOCK (_CMU_LOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for CMU_LOCK */
#define CMU_LOCK_LOCKKEY_LOCKED (_CMU_LOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for CMU_LOCK */
#define CMU_LOCK_LOCKKEY_UNLOCK (_CMU_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for CMU_LOCK */
diff --git a/cpu/efm32/families/efm32gg/include/vendor/efm32gg_dac.h b/cpu/efm32/families/efm32gg/include/vendor/efm32gg_dac.h
index 4230b74094..42474c9dfb 100644
--- a/cpu/efm32/families/efm32gg/include/vendor/efm32gg_dac.h
+++ b/cpu/efm32/families/efm32gg/include/vendor/efm32gg_dac.h
@@ -1,10 +1,9 @@
/***************************************************************************//**
* @file
* @brief EFM32GG_DAC register and bit field definitions
- * @version 5.8.3
*******************************************************************************
* # License
- * Copyright 2019 Silicon Laboratories Inc. www.silabs.com
+ * Copyright 2020 Silicon Laboratories Inc. www.silabs.com
*******************************************************************************
*
* SPDX-License-Identifier: Zlib
diff --git a/cpu/efm32/families/efm32gg/include/vendor/efm32gg_devinfo.h b/cpu/efm32/families/efm32gg/include/vendor/efm32gg_devinfo.h
index 9e0b713d9a..8150195f58 100644
--- a/cpu/efm32/families/efm32gg/include/vendor/efm32gg_devinfo.h
+++ b/cpu/efm32/families/efm32gg/include/vendor/efm32gg_devinfo.h
@@ -1,10 +1,9 @@
/***************************************************************************//**
* @file
* @brief EFM32GG_DEVINFO register and bit field definitions
- * @version 5.8.3
*******************************************************************************
* # License
- * Copyright 2019 Silicon Laboratories Inc. www.silabs.com
+ * Copyright 2020 Silicon Laboratories Inc. www.silabs.com
*******************************************************************************
*
* SPDX-License-Identifier: Zlib
diff --git a/cpu/efm32/families/efm32gg/include/vendor/efm32gg_dma.h b/cpu/efm32/families/efm32gg/include/vendor/efm32gg_dma.h
index baee81ed09..f8ab3e02c0 100644
--- a/cpu/efm32/families/efm32gg/include/vendor/efm32gg_dma.h
+++ b/cpu/efm32/families/efm32gg/include/vendor/efm32gg_dma.h
@@ -1,10 +1,9 @@
/***************************************************************************//**
* @file
* @brief EFM32GG_DMA register and bit field definitions
- * @version 5.8.3
*******************************************************************************
* # License
- * Copyright 2019 Silicon Laboratories Inc. www.silabs.com
+ * Copyright 2020 Silicon Laboratories Inc. www.silabs.com
*******************************************************************************
*
* SPDX-License-Identifier: Zlib
diff --git a/cpu/efm32/families/efm32gg/include/vendor/efm32gg_dma_ch.h b/cpu/efm32/families/efm32gg/include/vendor/efm32gg_dma_ch.h
index 02ed0916a3..2d81c5a3a5 100644
--- a/cpu/efm32/families/efm32gg/include/vendor/efm32gg_dma_ch.h
+++ b/cpu/efm32/families/efm32gg/include/vendor/efm32gg_dma_ch.h
@@ -1,10 +1,9 @@
/***************************************************************************//**
* @file
* @brief EFM32GG_DMA_CH register and bit field definitions
- * @version 5.8.3
*******************************************************************************
* # License
- * Copyright 2019 Silicon Laboratories Inc. www.silabs.com
+ * Copyright 2020 Silicon Laboratories Inc. www.silabs.com
*******************************************************************************
*
* SPDX-License-Identifier: Zlib
diff --git a/cpu/efm32/families/efm32gg/include/vendor/efm32gg_dma_descriptor.h b/cpu/efm32/families/efm32gg/include/vendor/efm32gg_dma_descriptor.h
index e8a74b8f19..2bf9ba8a99 100644
--- a/cpu/efm32/families/efm32gg/include/vendor/efm32gg_dma_descriptor.h
+++ b/cpu/efm32/families/efm32gg/include/vendor/efm32gg_dma_descriptor.h
@@ -1,10 +1,9 @@
/***************************************************************************//**
* @file
* @brief EFM32GG_DMA_DESCRIPTOR register and bit field definitions
- * @version 5.8.3
*******************************************************************************
* # License
- * Copyright 2019 Silicon Laboratories Inc. www.silabs.com
+ * Copyright 2020 Silicon Laboratories Inc. www.silabs.com
*******************************************************************************
*
* SPDX-License-Identifier: Zlib
diff --git a/cpu/efm32/families/efm32gg/include/vendor/efm32gg_dmactrl.h b/cpu/efm32/families/efm32gg/include/vendor/efm32gg_dmactrl.h
index f9252bcb83..6c5577e6c8 100644
--- a/cpu/efm32/families/efm32gg/include/vendor/efm32gg_dmactrl.h
+++ b/cpu/efm32/families/efm32gg/include/vendor/efm32gg_dmactrl.h
@@ -1,10 +1,9 @@
/***************************************************************************//**
* @file
* @brief EFM32GG_DMACTRL register and bit field definitions
- * @version 5.8.3
*******************************************************************************
* # License
- * Copyright 2019 Silicon Laboratories Inc. www.silabs.com
+ * Copyright 2020 Silicon Laboratories Inc. www.silabs.com
*******************************************************************************
*
* SPDX-License-Identifier: Zlib
diff --git a/cpu/efm32/families/efm32gg/include/vendor/efm32gg_dmareq.h b/cpu/efm32/families/efm32gg/include/vendor/efm32gg_dmareq.h
index 840b21fd32..9048d9f185 100644
--- a/cpu/efm32/families/efm32gg/include/vendor/efm32gg_dmareq.h
+++ b/cpu/efm32/families/efm32gg/include/vendor/efm32gg_dmareq.h
@@ -1,10 +1,9 @@
/***************************************************************************//**
* @file
* @brief EFM32GG_DMAREQ register and bit field definitions
- * @version 5.8.3
*******************************************************************************
* # License
- * Copyright 2019 Silicon Laboratories Inc. www.silabs.com
+ * Copyright 2020 Silicon Laboratories Inc. www.silabs.com
*******************************************************************************
*
* SPDX-License-Identifier: Zlib
diff --git a/cpu/efm32/families/efm32gg/include/vendor/efm32gg_ebi.h b/cpu/efm32/families/efm32gg/include/vendor/efm32gg_ebi.h
index e4fbb93de7..0755d0b370 100644
--- a/cpu/efm32/families/efm32gg/include/vendor/efm32gg_ebi.h
+++ b/cpu/efm32/families/efm32gg/include/vendor/efm32gg_ebi.h
@@ -1,10 +1,9 @@
/***************************************************************************//**
* @file
* @brief EFM32GG_EBI register and bit field definitions
- * @version 5.8.3
*******************************************************************************
* # License
- * Copyright 2019 Silicon Laboratories Inc. www.silabs.com
+ * Copyright 2020 Silicon Laboratories Inc. www.silabs.com
*******************************************************************************
*
* SPDX-License-Identifier: Zlib
diff --git a/cpu/efm32/families/efm32gg/include/vendor/efm32gg_emu.h b/cpu/efm32/families/efm32gg/include/vendor/efm32gg_emu.h
index d666bbca6e..6a30760c15 100644
--- a/cpu/efm32/families/efm32gg/include/vendor/efm32gg_emu.h
+++ b/cpu/efm32/families/efm32gg/include/vendor/efm32gg_emu.h
@@ -1,10 +1,9 @@
/***************************************************************************//**
* @file
* @brief EFM32GG_EMU register and bit field definitions
- * @version 5.8.3
*******************************************************************************
* # License
- * Copyright 2019 Silicon Laboratories Inc. www.silabs.com
+ * Copyright 2020 Silicon Laboratories Inc. www.silabs.com
*******************************************************************************
*
* SPDX-License-Identifier: Zlib
@@ -120,13 +119,13 @@ typedef struct {
#define _EMU_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for EMU_LOCKKEY */
#define _EMU_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for EMU_LOCKKEY */
#define _EMU_LOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_LOCK */
-#define _EMU_LOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for EMU_LOCK */
#define _EMU_LOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for EMU_LOCK */
+#define _EMU_LOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for EMU_LOCK */
#define _EMU_LOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for EMU_LOCK */
#define _EMU_LOCK_LOCKKEY_UNLOCK 0x0000ADE8UL /**< Mode UNLOCK for EMU_LOCK */
#define EMU_LOCK_LOCKKEY_DEFAULT (_EMU_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_LOCK */
-#define EMU_LOCK_LOCKKEY_LOCK (_EMU_LOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for EMU_LOCK */
#define EMU_LOCK_LOCKKEY_UNLOCKED (_EMU_LOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for EMU_LOCK */
+#define EMU_LOCK_LOCKKEY_LOCK (_EMU_LOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for EMU_LOCK */
#define EMU_LOCK_LOCKKEY_LOCKED (_EMU_LOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for EMU_LOCK */
#define EMU_LOCK_LOCKKEY_UNLOCK (_EMU_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for EMU_LOCK */
diff --git a/cpu/efm32/families/efm32gg/include/vendor/efm32gg_etm.h b/cpu/efm32/families/efm32gg/include/vendor/efm32gg_etm.h
index ba88876680..d77f5de01d 100644
--- a/cpu/efm32/families/efm32gg/include/vendor/efm32gg_etm.h
+++ b/cpu/efm32/families/efm32gg/include/vendor/efm32gg_etm.h
@@ -1,10 +1,9 @@
/***************************************************************************//**
* @file
* @brief EFM32GG_ETM register and bit field definitions
- * @version 5.8.3
*******************************************************************************
* # License
- * Copyright 2019 Silicon Laboratories Inc. www.silabs.com
+ * Copyright 2020 Silicon Laboratories Inc. www.silabs.com
*******************************************************************************
*
* SPDX-License-Identifier: Zlib
diff --git a/cpu/efm32/families/efm32gg/include/vendor/efm32gg_gpio.h b/cpu/efm32/families/efm32gg/include/vendor/efm32gg_gpio.h
index 5de4413545..2d5360bbf5 100644
--- a/cpu/efm32/families/efm32gg/include/vendor/efm32gg_gpio.h
+++ b/cpu/efm32/families/efm32gg/include/vendor/efm32gg_gpio.h
@@ -1,10 +1,9 @@
/***************************************************************************//**
* @file
* @brief EFM32GG_GPIO register and bit field definitions
- * @version 5.8.3
*******************************************************************************
* # License
- * Copyright 2019 Silicon Laboratories Inc. www.silabs.com
+ * Copyright 2020 Silicon Laboratories Inc. www.silabs.com
*******************************************************************************
*
* SPDX-License-Identifier: Zlib
@@ -1125,13 +1124,13 @@ typedef struct {
#define _GPIO_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for GPIO_LOCKKEY */
#define _GPIO_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for GPIO_LOCKKEY */
#define _GPIO_LOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_LOCK */
-#define _GPIO_LOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for GPIO_LOCK */
#define _GPIO_LOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for GPIO_LOCK */
+#define _GPIO_LOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for GPIO_LOCK */
#define _GPIO_LOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for GPIO_LOCK */
#define _GPIO_LOCK_LOCKKEY_UNLOCK 0x0000A534UL /**< Mode UNLOCK for GPIO_LOCK */
#define GPIO_LOCK_LOCKKEY_DEFAULT (_GPIO_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_LOCK */
-#define GPIO_LOCK_LOCKKEY_LOCK (_GPIO_LOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for GPIO_LOCK */
#define GPIO_LOCK_LOCKKEY_UNLOCKED (_GPIO_LOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for GPIO_LOCK */
+#define GPIO_LOCK_LOCKKEY_LOCK (_GPIO_LOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for GPIO_LOCK */
#define GPIO_LOCK_LOCKKEY_LOCKED (_GPIO_LOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for GPIO_LOCK */
#define GPIO_LOCK_LOCKKEY_UNLOCK (_GPIO_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for GPIO_LOCK */
diff --git a/cpu/efm32/families/efm32gg/include/vendor/efm32gg_gpio_p.h b/cpu/efm32/families/efm32gg/include/vendor/efm32gg_gpio_p.h
index 6af475d3ad..20c3153ab0 100644
--- a/cpu/efm32/families/efm32gg/include/vendor/efm32gg_gpio_p.h
+++ b/cpu/efm32/families/efm32gg/include/vendor/efm32gg_gpio_p.h
@@ -1,10 +1,9 @@
/***************************************************************************//**
* @file
* @brief EFM32GG_GPIO_P register and bit field definitions
- * @version 5.8.3
*******************************************************************************
* # License
- * Copyright 2019 Silicon Laboratories Inc. www.silabs.com
+ * Copyright 2020 Silicon Laboratories Inc. www.silabs.com
*******************************************************************************
*
* SPDX-License-Identifier: Zlib
diff --git a/cpu/efm32/families/efm32gg/include/vendor/efm32gg_i2c.h b/cpu/efm32/families/efm32gg/include/vendor/efm32gg_i2c.h
index 94916cf8fa..4a0c222da5 100644
--- a/cpu/efm32/families/efm32gg/include/vendor/efm32gg_i2c.h
+++ b/cpu/efm32/families/efm32gg/include/vendor/efm32gg_i2c.h
@@ -1,10 +1,9 @@
/***************************************************************************//**
* @file
* @brief EFM32GG_I2C register and bit field definitions
- * @version 5.8.3
*******************************************************************************
* # License
- * Copyright 2019 Silicon Laboratories Inc. www.silabs.com
+ * Copyright 2020 Silicon Laboratories Inc. www.silabs.com
*******************************************************************************
*
* SPDX-License-Identifier: Zlib
diff --git a/cpu/efm32/families/efm32gg/include/vendor/efm32gg_lcd.h b/cpu/efm32/families/efm32gg/include/vendor/efm32gg_lcd.h
index 7bf18bf28c..3194ae9ecb 100644
--- a/cpu/efm32/families/efm32gg/include/vendor/efm32gg_lcd.h
+++ b/cpu/efm32/families/efm32gg/include/vendor/efm32gg_lcd.h
@@ -1,10 +1,9 @@
/***************************************************************************//**
* @file
* @brief EFM32GG_LCD register and bit field definitions
- * @version 5.8.3
*******************************************************************************
* # License
- * Copyright 2019 Silicon Laboratories Inc. www.silabs.com
+ * Copyright 2020 Silicon Laboratories Inc. www.silabs.com
*******************************************************************************
*
* SPDX-License-Identifier: Zlib
diff --git a/cpu/efm32/families/efm32gg/include/vendor/efm32gg_lesense.h b/cpu/efm32/families/efm32gg/include/vendor/efm32gg_lesense.h
index 68a0fc2756..ba44afd1a2 100644
--- a/cpu/efm32/families/efm32gg/include/vendor/efm32gg_lesense.h
+++ b/cpu/efm32/families/efm32gg/include/vendor/efm32gg_lesense.h
@@ -1,10 +1,9 @@
/***************************************************************************//**
* @file
* @brief EFM32GG_LESENSE register and bit field definitions
- * @version 5.8.3
*******************************************************************************
* # License
- * Copyright 2019 Silicon Laboratories Inc. www.silabs.com
+ * Copyright 2020 Silicon Laboratories Inc. www.silabs.com
*******************************************************************************
*
* SPDX-License-Identifier: Zlib
@@ -1731,27 +1730,27 @@ typedef struct {
#define _LESENSE_ST_TCONFA_PRSACT_MASK 0x7000UL /**< Bit mask for LESENSE_PRSACT */
#define _LESENSE_ST_TCONFA_PRSACT_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_ST_TCONFA */
#define _LESENSE_ST_TCONFA_PRSACT_NONE 0x00000000UL /**< Mode NONE for LESENSE_ST_TCONFA */
-#define _LESENSE_ST_TCONFA_PRSACT_UP 0x00000001UL /**< Mode UP for LESENSE_ST_TCONFA */
#define _LESENSE_ST_TCONFA_PRSACT_PRS0 0x00000001UL /**< Mode PRS0 for LESENSE_ST_TCONFA */
-#define _LESENSE_ST_TCONFA_PRSACT_PRS1 0x00000002UL /**< Mode PRS1 for LESENSE_ST_TCONFA */
+#define _LESENSE_ST_TCONFA_PRSACT_UP 0x00000001UL /**< Mode UP for LESENSE_ST_TCONFA */
#define _LESENSE_ST_TCONFA_PRSACT_DOWN 0x00000002UL /**< Mode DOWN for LESENSE_ST_TCONFA */
+#define _LESENSE_ST_TCONFA_PRSACT_PRS1 0x00000002UL /**< Mode PRS1 for LESENSE_ST_TCONFA */
#define _LESENSE_ST_TCONFA_PRSACT_PRS01 0x00000003UL /**< Mode PRS01 for LESENSE_ST_TCONFA */
#define _LESENSE_ST_TCONFA_PRSACT_PRS2 0x00000004UL /**< Mode PRS2 for LESENSE_ST_TCONFA */
-#define _LESENSE_ST_TCONFA_PRSACT_PRS02 0x00000005UL /**< Mode PRS02 for LESENSE_ST_TCONFA */
#define _LESENSE_ST_TCONFA_PRSACT_UPANDPRS2 0x00000005UL /**< Mode UPANDPRS2 for LESENSE_ST_TCONFA */
+#define _LESENSE_ST_TCONFA_PRSACT_PRS02 0x00000005UL /**< Mode PRS02 for LESENSE_ST_TCONFA */
#define _LESENSE_ST_TCONFA_PRSACT_PRS12 0x00000006UL /**< Mode PRS12 for LESENSE_ST_TCONFA */
#define _LESENSE_ST_TCONFA_PRSACT_DOWNANDPRS2 0x00000006UL /**< Mode DOWNANDPRS2 for LESENSE_ST_TCONFA */
#define _LESENSE_ST_TCONFA_PRSACT_PRS012 0x00000007UL /**< Mode PRS012 for LESENSE_ST_TCONFA */
#define LESENSE_ST_TCONFA_PRSACT_DEFAULT (_LESENSE_ST_TCONFA_PRSACT_DEFAULT << 12) /**< Shifted mode DEFAULT for LESENSE_ST_TCONFA */
#define LESENSE_ST_TCONFA_PRSACT_NONE (_LESENSE_ST_TCONFA_PRSACT_NONE << 12) /**< Shifted mode NONE for LESENSE_ST_TCONFA */
-#define LESENSE_ST_TCONFA_PRSACT_UP (_LESENSE_ST_TCONFA_PRSACT_UP << 12) /**< Shifted mode UP for LESENSE_ST_TCONFA */
#define LESENSE_ST_TCONFA_PRSACT_PRS0 (_LESENSE_ST_TCONFA_PRSACT_PRS0 << 12) /**< Shifted mode PRS0 for LESENSE_ST_TCONFA */
-#define LESENSE_ST_TCONFA_PRSACT_PRS1 (_LESENSE_ST_TCONFA_PRSACT_PRS1 << 12) /**< Shifted mode PRS1 for LESENSE_ST_TCONFA */
+#define LESENSE_ST_TCONFA_PRSACT_UP (_LESENSE_ST_TCONFA_PRSACT_UP << 12) /**< Shifted mode UP for LESENSE_ST_TCONFA */
#define LESENSE_ST_TCONFA_PRSACT_DOWN (_LESENSE_ST_TCONFA_PRSACT_DOWN << 12) /**< Shifted mode DOWN for LESENSE_ST_TCONFA */
+#define LESENSE_ST_TCONFA_PRSACT_PRS1 (_LESENSE_ST_TCONFA_PRSACT_PRS1 << 12) /**< Shifted mode PRS1 for LESENSE_ST_TCONFA */
#define LESENSE_ST_TCONFA_PRSACT_PRS01 (_LESENSE_ST_TCONFA_PRSACT_PRS01 << 12) /**< Shifted mode PRS01 for LESENSE_ST_TCONFA */
#define LESENSE_ST_TCONFA_PRSACT_PRS2 (_LESENSE_ST_TCONFA_PRSACT_PRS2 << 12) /**< Shifted mode PRS2 for LESENSE_ST_TCONFA */
-#define LESENSE_ST_TCONFA_PRSACT_PRS02 (_LESENSE_ST_TCONFA_PRSACT_PRS02 << 12) /**< Shifted mode PRS02 for LESENSE_ST_TCONFA */
#define LESENSE_ST_TCONFA_PRSACT_UPANDPRS2 (_LESENSE_ST_TCONFA_PRSACT_UPANDPRS2 << 12) /**< Shifted mode UPANDPRS2 for LESENSE_ST_TCONFA */
+#define LESENSE_ST_TCONFA_PRSACT_PRS02 (_LESENSE_ST_TCONFA_PRSACT_PRS02 << 12) /**< Shifted mode PRS02 for LESENSE_ST_TCONFA */
#define LESENSE_ST_TCONFA_PRSACT_PRS12 (_LESENSE_ST_TCONFA_PRSACT_PRS12 << 12) /**< Shifted mode PRS12 for LESENSE_ST_TCONFA */
#define LESENSE_ST_TCONFA_PRSACT_DOWNANDPRS2 (_LESENSE_ST_TCONFA_PRSACT_DOWNANDPRS2 << 12) /**< Shifted mode DOWNANDPRS2 for LESENSE_ST_TCONFA */
#define LESENSE_ST_TCONFA_PRSACT_PRS012 (_LESENSE_ST_TCONFA_PRSACT_PRS012 << 12) /**< Shifted mode PRS012 for LESENSE_ST_TCONFA */
@@ -1785,27 +1784,27 @@ typedef struct {
#define _LESENSE_ST_TCONFB_PRSACT_MASK 0x7000UL /**< Bit mask for LESENSE_PRSACT */
#define _LESENSE_ST_TCONFB_PRSACT_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_ST_TCONFB */
#define _LESENSE_ST_TCONFB_PRSACT_NONE 0x00000000UL /**< Mode NONE for LESENSE_ST_TCONFB */
-#define _LESENSE_ST_TCONFB_PRSACT_UP 0x00000001UL /**< Mode UP for LESENSE_ST_TCONFB */
#define _LESENSE_ST_TCONFB_PRSACT_PRS0 0x00000001UL /**< Mode PRS0 for LESENSE_ST_TCONFB */
-#define _LESENSE_ST_TCONFB_PRSACT_PRS1 0x00000002UL /**< Mode PRS1 for LESENSE_ST_TCONFB */
+#define _LESENSE_ST_TCONFB_PRSACT_UP 0x00000001UL /**< Mode UP for LESENSE_ST_TCONFB */
#define _LESENSE_ST_TCONFB_PRSACT_DOWN 0x00000002UL /**< Mode DOWN for LESENSE_ST_TCONFB */
+#define _LESENSE_ST_TCONFB_PRSACT_PRS1 0x00000002UL /**< Mode PRS1 for LESENSE_ST_TCONFB */
#define _LESENSE_ST_TCONFB_PRSACT_PRS01 0x00000003UL /**< Mode PRS01 for LESENSE_ST_TCONFB */
#define _LESENSE_ST_TCONFB_PRSACT_PRS2 0x00000004UL /**< Mode PRS2 for LESENSE_ST_TCONFB */
-#define _LESENSE_ST_TCONFB_PRSACT_PRS02 0x00000005UL /**< Mode PRS02 for LESENSE_ST_TCONFB */
#define _LESENSE_ST_TCONFB_PRSACT_UPANDPRS2 0x00000005UL /**< Mode UPANDPRS2 for LESENSE_ST_TCONFB */
+#define _LESENSE_ST_TCONFB_PRSACT_PRS02 0x00000005UL /**< Mode PRS02 for LESENSE_ST_TCONFB */
#define _LESENSE_ST_TCONFB_PRSACT_PRS12 0x00000006UL /**< Mode PRS12 for LESENSE_ST_TCONFB */
#define _LESENSE_ST_TCONFB_PRSACT_DOWNANDPRS2 0x00000006UL /**< Mode DOWNANDPRS2 for LESENSE_ST_TCONFB */
#define _LESENSE_ST_TCONFB_PRSACT_PRS012 0x00000007UL /**< Mode PRS012 for LESENSE_ST_TCONFB */
#define LESENSE_ST_TCONFB_PRSACT_DEFAULT (_LESENSE_ST_TCONFB_PRSACT_DEFAULT << 12) /**< Shifted mode DEFAULT for LESENSE_ST_TCONFB */
#define LESENSE_ST_TCONFB_PRSACT_NONE (_LESENSE_ST_TCONFB_PRSACT_NONE << 12) /**< Shifted mode NONE for LESENSE_ST_TCONFB */
-#define LESENSE_ST_TCONFB_PRSACT_UP (_LESENSE_ST_TCONFB_PRSACT_UP << 12) /**< Shifted mode UP for LESENSE_ST_TCONFB */
#define LESENSE_ST_TCONFB_PRSACT_PRS0 (_LESENSE_ST_TCONFB_PRSACT_PRS0 << 12) /**< Shifted mode PRS0 for LESENSE_ST_TCONFB */
-#define LESENSE_ST_TCONFB_PRSACT_PRS1 (_LESENSE_ST_TCONFB_PRSACT_PRS1 << 12) /**< Shifted mode PRS1 for LESENSE_ST_TCONFB */
+#define LESENSE_ST_TCONFB_PRSACT_UP (_LESENSE_ST_TCONFB_PRSACT_UP << 12) /**< Shifted mode UP for LESENSE_ST_TCONFB */
#define LESENSE_ST_TCONFB_PRSACT_DOWN (_LESENSE_ST_TCONFB_PRSACT_DOWN << 12) /**< Shifted mode DOWN for LESENSE_ST_TCONFB */
+#define LESENSE_ST_TCONFB_PRSACT_PRS1 (_LESENSE_ST_TCONFB_PRSACT_PRS1 << 12) /**< Shifted mode PRS1 for LESENSE_ST_TCONFB */
#define LESENSE_ST_TCONFB_PRSACT_PRS01 (_LESENSE_ST_TCONFB_PRSACT_PRS01 << 12) /**< Shifted mode PRS01 for LESENSE_ST_TCONFB */
#define LESENSE_ST_TCONFB_PRSACT_PRS2 (_LESENSE_ST_TCONFB_PRSACT_PRS2 << 12) /**< Shifted mode PRS2 for LESENSE_ST_TCONFB */
-#define LESENSE_ST_TCONFB_PRSACT_PRS02 (_LESENSE_ST_TCONFB_PRSACT_PRS02 << 12) /**< Shifted mode PRS02 for LESENSE_ST_TCONFB */
#define LESENSE_ST_TCONFB_PRSACT_UPANDPRS2 (_LESENSE_ST_TCONFB_PRSACT_UPANDPRS2 << 12) /**< Shifted mode UPANDPRS2 for LESENSE_ST_TCONFB */
+#define LESENSE_ST_TCONFB_PRSACT_PRS02 (_LESENSE_ST_TCONFB_PRSACT_PRS02 << 12) /**< Shifted mode PRS02 for LESENSE_ST_TCONFB */
#define LESENSE_ST_TCONFB_PRSACT_PRS12 (_LESENSE_ST_TCONFB_PRSACT_PRS12 << 12) /**< Shifted mode PRS12 for LESENSE_ST_TCONFB */
#define LESENSE_ST_TCONFB_PRSACT_DOWNANDPRS2 (_LESENSE_ST_TCONFB_PRSACT_DOWNANDPRS2 << 12) /**< Shifted mode DOWNANDPRS2 for LESENSE_ST_TCONFB */
#define LESENSE_ST_TCONFB_PRSACT_PRS012 (_LESENSE_ST_TCONFB_PRSACT_PRS012 << 12) /**< Shifted mode PRS012 for LESENSE_ST_TCONFB */
diff --git a/cpu/efm32/families/efm32gg/include/vendor/efm32gg_lesense_buf.h b/cpu/efm32/families/efm32gg/include/vendor/efm32gg_lesense_buf.h
index 239ecf175e..db9d622bc5 100644
--- a/cpu/efm32/families/efm32gg/include/vendor/efm32gg_lesense_buf.h
+++ b/cpu/efm32/families/efm32gg/include/vendor/efm32gg_lesense_buf.h
@@ -1,10 +1,9 @@
/***************************************************************************//**
* @file
* @brief EFM32GG_LESENSE_BUF register and bit field definitions
- * @version 5.8.3
*******************************************************************************
* # License
- * Copyright 2019 Silicon Laboratories Inc. www.silabs.com
+ * Copyright 2020 Silicon Laboratories Inc. www.silabs.com
*******************************************************************************
*
* SPDX-License-Identifier: Zlib
diff --git a/cpu/efm32/families/efm32gg/include/vendor/efm32gg_lesense_ch.h b/cpu/efm32/families/efm32gg/include/vendor/efm32gg_lesense_ch.h
index 7c84f83596..ddfb8c2a16 100644
--- a/cpu/efm32/families/efm32gg/include/vendor/efm32gg_lesense_ch.h
+++ b/cpu/efm32/families/efm32gg/include/vendor/efm32gg_lesense_ch.h
@@ -1,10 +1,9 @@
/***************************************************************************//**
* @file
* @brief EFM32GG_LESENSE_CH register and bit field definitions
- * @version 5.8.3
*******************************************************************************
* # License
- * Copyright 2019 Silicon Laboratories Inc. www.silabs.com
+ * Copyright 2020 Silicon Laboratories Inc. www.silabs.com
*******************************************************************************
*
* SPDX-License-Identifier: Zlib
diff --git a/cpu/efm32/families/efm32gg/include/vendor/efm32gg_lesense_st.h b/cpu/efm32/families/efm32gg/include/vendor/efm32gg_lesense_st.h
index abeac3eba1..67166a7a59 100644
--- a/cpu/efm32/families/efm32gg/include/vendor/efm32gg_lesense_st.h
+++ b/cpu/efm32/families/efm32gg/include/vendor/efm32gg_lesense_st.h
@@ -1,10 +1,9 @@
/***************************************************************************//**
* @file
* @brief EFM32GG_LESENSE_ST register and bit field definitions
- * @version 5.8.3
*******************************************************************************
* # License
- * Copyright 2019 Silicon Laboratories Inc. www.silabs.com
+ * Copyright 2020 Silicon Laboratories Inc. www.silabs.com
*******************************************************************************
*
* SPDX-License-Identifier: Zlib
diff --git a/cpu/efm32/families/efm32gg/include/vendor/efm32gg_letimer.h b/cpu/efm32/families/efm32gg/include/vendor/efm32gg_letimer.h
index 263840b46f..7d4b9390fa 100644
--- a/cpu/efm32/families/efm32gg/include/vendor/efm32gg_letimer.h
+++ b/cpu/efm32/families/efm32gg/include/vendor/efm32gg_letimer.h
@@ -1,10 +1,9 @@
/***************************************************************************//**
* @file
* @brief EFM32GG_LETIMER register and bit field definitions
- * @version 5.8.3
*******************************************************************************
* # License
- * Copyright 2019 Silicon Laboratories Inc. www.silabs.com
+ * Copyright 2020 Silicon Laboratories Inc. www.silabs.com
*******************************************************************************
*
* SPDX-License-Identifier: Zlib
diff --git a/cpu/efm32/families/efm32gg/include/vendor/efm32gg_leuart.h b/cpu/efm32/families/efm32gg/include/vendor/efm32gg_leuart.h
index 2c72fcb542..979558683e 100644
--- a/cpu/efm32/families/efm32gg/include/vendor/efm32gg_leuart.h
+++ b/cpu/efm32/families/efm32gg/include/vendor/efm32gg_leuart.h
@@ -1,10 +1,9 @@
/***************************************************************************//**
* @file
* @brief EFM32GG_LEUART register and bit field definitions
- * @version 5.8.3
*******************************************************************************
* # License
- * Copyright 2019 Silicon Laboratories Inc. www.silabs.com
+ * Copyright 2020 Silicon Laboratories Inc. www.silabs.com
*******************************************************************************
*
* SPDX-License-Identifier: Zlib
diff --git a/cpu/efm32/families/efm32gg/include/vendor/efm32gg_msc.h b/cpu/efm32/families/efm32gg/include/vendor/efm32gg_msc.h
index 2251bef218..11abe3d92f 100644
--- a/cpu/efm32/families/efm32gg/include/vendor/efm32gg_msc.h
+++ b/cpu/efm32/families/efm32gg/include/vendor/efm32gg_msc.h
@@ -1,10 +1,9 @@
/***************************************************************************//**
* @file
* @brief EFM32GG_MSC register and bit field definitions
- * @version 5.8.3
*******************************************************************************
* # License
- * Copyright 2019 Silicon Laboratories Inc. www.silabs.com
+ * Copyright 2020 Silicon Laboratories Inc. www.silabs.com
*******************************************************************************
*
* SPDX-License-Identifier: Zlib
@@ -394,13 +393,13 @@ typedef struct {
#define _MSC_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for MSC_LOCKKEY */
#define _MSC_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for MSC_LOCKKEY */
#define _MSC_LOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_LOCK */
-#define _MSC_LOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for MSC_LOCK */
#define _MSC_LOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for MSC_LOCK */
+#define _MSC_LOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for MSC_LOCK */
#define _MSC_LOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for MSC_LOCK */
#define _MSC_LOCK_LOCKKEY_UNLOCK 0x00001B71UL /**< Mode UNLOCK for MSC_LOCK */
#define MSC_LOCK_LOCKKEY_DEFAULT (_MSC_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_LOCK */
-#define MSC_LOCK_LOCKKEY_LOCK (_MSC_LOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for MSC_LOCK */
#define MSC_LOCK_LOCKKEY_UNLOCKED (_MSC_LOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for MSC_LOCK */
+#define MSC_LOCK_LOCKKEY_LOCK (_MSC_LOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for MSC_LOCK */
#define MSC_LOCK_LOCKKEY_LOCKED (_MSC_LOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for MSC_LOCK */
#define MSC_LOCK_LOCKKEY_UNLOCK (_MSC_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for MSC_LOCK */
@@ -461,13 +460,13 @@ typedef struct {
#define _MSC_MASSLOCK_MASK 0x0000FFFFUL /**< Mask for MSC_MASSLOCK */
#define _MSC_MASSLOCK_LOCKKEY_SHIFT 0 /**< Shift value for MSC_LOCKKEY */
#define _MSC_MASSLOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for MSC_LOCKKEY */
-#define _MSC_MASSLOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for MSC_MASSLOCK */
#define _MSC_MASSLOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for MSC_MASSLOCK */
+#define _MSC_MASSLOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for MSC_MASSLOCK */
#define _MSC_MASSLOCK_LOCKKEY_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_MASSLOCK */
#define _MSC_MASSLOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for MSC_MASSLOCK */
#define _MSC_MASSLOCK_LOCKKEY_UNLOCK 0x0000631AUL /**< Mode UNLOCK for MSC_MASSLOCK */
-#define MSC_MASSLOCK_LOCKKEY_LOCK (_MSC_MASSLOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for MSC_MASSLOCK */
#define MSC_MASSLOCK_LOCKKEY_UNLOCKED (_MSC_MASSLOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for MSC_MASSLOCK */
+#define MSC_MASSLOCK_LOCKKEY_LOCK (_MSC_MASSLOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for MSC_MASSLOCK */
#define MSC_MASSLOCK_LOCKKEY_DEFAULT (_MSC_MASSLOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_MASSLOCK */
#define MSC_MASSLOCK_LOCKKEY_LOCKED (_MSC_MASSLOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for MSC_MASSLOCK */
#define MSC_MASSLOCK_LOCKKEY_UNLOCK (_MSC_MASSLOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for MSC_MASSLOCK */
diff --git a/cpu/efm32/families/efm32gg/include/vendor/efm32gg_pcnt.h b/cpu/efm32/families/efm32gg/include/vendor/efm32gg_pcnt.h
index 4cc4e39a04..5339861b34 100644
--- a/cpu/efm32/families/efm32gg/include/vendor/efm32gg_pcnt.h
+++ b/cpu/efm32/families/efm32gg/include/vendor/efm32gg_pcnt.h
@@ -1,10 +1,9 @@
/***************************************************************************//**
* @file
* @brief EFM32GG_PCNT register and bit field definitions
- * @version 5.8.3
*******************************************************************************
* # License
- * Copyright 2019 Silicon Laboratories Inc. www.silabs.com
+ * Copyright 2020 Silicon Laboratories Inc. www.silabs.com
*******************************************************************************
*
* SPDX-License-Identifier: Zlib
diff --git a/cpu/efm32/families/efm32gg/include/vendor/efm32gg_prs.h b/cpu/efm32/families/efm32gg/include/vendor/efm32gg_prs.h
index 6dc440847b..2c7cfea9a7 100644
--- a/cpu/efm32/families/efm32gg/include/vendor/efm32gg_prs.h
+++ b/cpu/efm32/families/efm32gg/include/vendor/efm32gg_prs.h
@@ -1,10 +1,9 @@
/***************************************************************************//**
* @file
* @brief EFM32GG_PRS register and bit field definitions
- * @version 5.8.3
*******************************************************************************
* # License
- * Copyright 2019 Silicon Laboratories Inc. www.silabs.com
+ * Copyright 2020 Silicon Laboratories Inc. www.silabs.com
*******************************************************************************
*
* SPDX-License-Identifier: Zlib
diff --git a/cpu/efm32/families/efm32gg/include/vendor/efm32gg_prs_ch.h b/cpu/efm32/families/efm32gg/include/vendor/efm32gg_prs_ch.h
index ffe86f282e..db2ac9c0d5 100644
--- a/cpu/efm32/families/efm32gg/include/vendor/efm32gg_prs_ch.h
+++ b/cpu/efm32/families/efm32gg/include/vendor/efm32gg_prs_ch.h
@@ -1,10 +1,9 @@
/***************************************************************************//**
* @file
* @brief EFM32GG_PRS_CH register and bit field definitions
- * @version 5.8.3
*******************************************************************************
* # License
- * Copyright 2019 Silicon Laboratories Inc. www.silabs.com
+ * Copyright 2020 Silicon Laboratories Inc. www.silabs.com
*******************************************************************************
*
* SPDX-License-Identifier: Zlib
diff --git a/cpu/efm32/families/efm32gg/include/vendor/efm32gg_prs_signals.h b/cpu/efm32/families/efm32gg/include/vendor/efm32gg_prs_signals.h
index 8172b2afdf..da551b865d 100644
--- a/cpu/efm32/families/efm32gg/include/vendor/efm32gg_prs_signals.h
+++ b/cpu/efm32/families/efm32gg/include/vendor/efm32gg_prs_signals.h
@@ -1,10 +1,9 @@
/***************************************************************************//**
* @file
* @brief EFM32GG_PRS_SIGNALS register and bit field definitions
- * @version 5.8.3
*******************************************************************************
* # License
- * Copyright 2019 Silicon Laboratories Inc. www.silabs.com
+ * Copyright 2020 Silicon Laboratories Inc. www.silabs.com
*******************************************************************************
*
* SPDX-License-Identifier: Zlib
diff --git a/cpu/efm32/families/efm32gg/include/vendor/efm32gg_rmu.h b/cpu/efm32/families/efm32gg/include/vendor/efm32gg_rmu.h
index 6df3af9a53..b3fb5b4af4 100644
--- a/cpu/efm32/families/efm32gg/include/vendor/efm32gg_rmu.h
+++ b/cpu/efm32/families/efm32gg/include/vendor/efm32gg_rmu.h
@@ -1,10 +1,9 @@
/***************************************************************************//**
* @file
* @brief EFM32GG_RMU register and bit field definitions
- * @version 5.8.3
*******************************************************************************
* # License
- * Copyright 2019 Silicon Laboratories Inc. www.silabs.com
+ * Copyright 2020 Silicon Laboratories Inc. www.silabs.com
*******************************************************************************
*
* SPDX-License-Identifier: Zlib
diff --git a/cpu/efm32/families/efm32gg/include/vendor/efm32gg_romtable.h b/cpu/efm32/families/efm32gg/include/vendor/efm32gg_romtable.h
index 6ae4ae9ff0..15e909ac29 100644
--- a/cpu/efm32/families/efm32gg/include/vendor/efm32gg_romtable.h
+++ b/cpu/efm32/families/efm32gg/include/vendor/efm32gg_romtable.h
@@ -1,10 +1,9 @@
/***************************************************************************//**
* @file
* @brief EFM32GG_ROMTABLE register and bit field definitions
- * @version 5.8.3
*******************************************************************************
* # License
- * Copyright 2019 Silicon Laboratories Inc. www.silabs.com
+ * Copyright 2020 Silicon Laboratories Inc. www.silabs.com
*******************************************************************************
*
* SPDX-License-Identifier: Zlib
diff --git a/cpu/efm32/families/efm32gg/include/vendor/efm32gg_rtc.h b/cpu/efm32/families/efm32gg/include/vendor/efm32gg_rtc.h
index 3db7271815..680bbc549f 100644
--- a/cpu/efm32/families/efm32gg/include/vendor/efm32gg_rtc.h
+++ b/cpu/efm32/families/efm32gg/include/vendor/efm32gg_rtc.h
@@ -1,10 +1,9 @@
/***************************************************************************//**
* @file
* @brief EFM32GG_RTC register and bit field definitions
- * @version 5.8.3
*******************************************************************************
* # License
- * Copyright 2019 Silicon Laboratories Inc. www.silabs.com
+ * Copyright 2020 Silicon Laboratories Inc. www.silabs.com
*******************************************************************************
*
* SPDX-License-Identifier: Zlib
diff --git a/cpu/efm32/families/efm32gg/include/vendor/efm32gg_timer.h b/cpu/efm32/families/efm32gg/include/vendor/efm32gg_timer.h
index 0bbe102d4c..421d008313 100644
--- a/cpu/efm32/families/efm32gg/include/vendor/efm32gg_timer.h
+++ b/cpu/efm32/families/efm32gg/include/vendor/efm32gg_timer.h
@@ -1,10 +1,9 @@
/***************************************************************************//**
* @file
* @brief EFM32GG_TIMER register and bit field definitions
- * @version 5.8.3
*******************************************************************************
* # License
- * Copyright 2019 Silicon Laboratories Inc. www.silabs.com
+ * Copyright 2020 Silicon Laboratories Inc. www.silabs.com
*******************************************************************************
*
* SPDX-License-Identifier: Zlib
@@ -963,13 +962,13 @@ typedef struct {
#define _TIMER_DTLOCK_LOCKKEY_SHIFT 0 /**< Shift value for TIMER_LOCKKEY */
#define _TIMER_DTLOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for TIMER_LOCKKEY */
#define _TIMER_DTLOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTLOCK */
-#define _TIMER_DTLOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for TIMER_DTLOCK */
#define _TIMER_DTLOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for TIMER_DTLOCK */
+#define _TIMER_DTLOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for TIMER_DTLOCK */
#define _TIMER_DTLOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for TIMER_DTLOCK */
#define _TIMER_DTLOCK_LOCKKEY_UNLOCK 0x0000CE80UL /**< Mode UNLOCK for TIMER_DTLOCK */
#define TIMER_DTLOCK_LOCKKEY_DEFAULT (_TIMER_DTLOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_DTLOCK */
-#define TIMER_DTLOCK_LOCKKEY_LOCK (_TIMER_DTLOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for TIMER_DTLOCK */
#define TIMER_DTLOCK_LOCKKEY_UNLOCKED (_TIMER_DTLOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for TIMER_DTLOCK */
+#define TIMER_DTLOCK_LOCKKEY_LOCK (_TIMER_DTLOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for TIMER_DTLOCK */
#define TIMER_DTLOCK_LOCKKEY_LOCKED (_TIMER_DTLOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for TIMER_DTLOCK */
#define TIMER_DTLOCK_LOCKKEY_UNLOCK (_TIMER_DTLOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for TIMER_DTLOCK */
diff --git a/cpu/efm32/families/efm32gg/include/vendor/efm32gg_timer_cc.h b/cpu/efm32/families/efm32gg/include/vendor/efm32gg_timer_cc.h
index f2470f63f9..27adb1a047 100644
--- a/cpu/efm32/families/efm32gg/include/vendor/efm32gg_timer_cc.h
+++ b/cpu/efm32/families/efm32gg/include/vendor/efm32gg_timer_cc.h
@@ -1,10 +1,9 @@
/***************************************************************************//**
* @file
* @brief EFM32GG_TIMER_CC register and bit field definitions
- * @version 5.8.3
*******************************************************************************
* # License
- * Copyright 2019 Silicon Laboratories Inc. www.silabs.com
+ * Copyright 2020 Silicon Laboratories Inc. www.silabs.com
*******************************************************************************
*
* SPDX-License-Identifier: Zlib
diff --git a/cpu/efm32/families/efm32gg/include/vendor/efm32gg_uart.h b/cpu/efm32/families/efm32gg/include/vendor/efm32gg_uart.h
index 4322ec2ee6..fe424cd2cb 100644
--- a/cpu/efm32/families/efm32gg/include/vendor/efm32gg_uart.h
+++ b/cpu/efm32/families/efm32gg/include/vendor/efm32gg_uart.h
@@ -1,10 +1,9 @@
/***************************************************************************//**
* @file
* @brief EFM32GG_UART register and bit field definitions
- * @version 5.8.3
*******************************************************************************
* # License
- * Copyright 2019 Silicon Laboratories Inc. www.silabs.com
+ * Copyright 2020 Silicon Laboratories Inc. www.silabs.com
*******************************************************************************
*
* SPDX-License-Identifier: Zlib
diff --git a/cpu/efm32/families/efm32gg/include/vendor/efm32gg_usart.h b/cpu/efm32/families/efm32gg/include/vendor/efm32gg_usart.h
index 3d6f2cea80..ade2dca025 100644
--- a/cpu/efm32/families/efm32gg/include/vendor/efm32gg_usart.h
+++ b/cpu/efm32/families/efm32gg/include/vendor/efm32gg_usart.h
@@ -1,10 +1,9 @@
/***************************************************************************//**
* @file
* @brief EFM32GG_USART register and bit field definitions
- * @version 5.8.3
*******************************************************************************
* # License
- * Copyright 2019 Silicon Laboratories Inc. www.silabs.com
+ * Copyright 2020 Silicon Laboratories Inc. www.silabs.com
*******************************************************************************
*
* SPDX-License-Identifier: Zlib
diff --git a/cpu/efm32/families/efm32gg/include/vendor/efm32gg_usb.h b/cpu/efm32/families/efm32gg/include/vendor/efm32gg_usb.h
index aab1cd709d..7de196c37f 100644
--- a/cpu/efm32/families/efm32gg/include/vendor/efm32gg_usb.h
+++ b/cpu/efm32/families/efm32gg/include/vendor/efm32gg_usb.h
@@ -1,10 +1,9 @@
/***************************************************************************//**
* @file
* @brief EFM32GG_USB register and bit field definitions
- * @version 5.8.3
*******************************************************************************
* # License
- * Copyright 2019 Silicon Laboratories Inc. www.silabs.com
+ * Copyright 2020 Silicon Laboratories Inc. www.silabs.com
*******************************************************************************
*
* SPDX-License-Identifier: Zlib
diff --git a/cpu/efm32/families/efm32gg/include/vendor/efm32gg_usb_diep.h b/cpu/efm32/families/efm32gg/include/vendor/efm32gg_usb_diep.h
index ec6796cf0a..15df3ae078 100644
--- a/cpu/efm32/families/efm32gg/include/vendor/efm32gg_usb_diep.h
+++ b/cpu/efm32/families/efm32gg/include/vendor/efm32gg_usb_diep.h
@@ -1,10 +1,9 @@
/***************************************************************************//**
* @file
* @brief EFM32GG_USB_DIEP register and bit field definitions
- * @version 5.8.3
*******************************************************************************
* # License
- * Copyright 2019 Silicon Laboratories Inc. www.silabs.com
+ * Copyright 2020 Silicon Laboratories Inc. www.silabs.com
*******************************************************************************
*
* SPDX-License-Identifier: Zlib
diff --git a/cpu/efm32/families/efm32gg/include/vendor/efm32gg_usb_doep.h b/cpu/efm32/families/efm32gg/include/vendor/efm32gg_usb_doep.h
index 76093b6d7c..c784d43822 100644
--- a/cpu/efm32/families/efm32gg/include/vendor/efm32gg_usb_doep.h
+++ b/cpu/efm32/families/efm32gg/include/vendor/efm32gg_usb_doep.h
@@ -1,10 +1,9 @@
/***************************************************************************//**
* @file
* @brief EFM32GG_USB_DOEP register and bit field definitions
- * @version 5.8.3
*******************************************************************************
* # License
- * Copyright 2019 Silicon Laboratories Inc. www.silabs.com
+ * Copyright 2020 Silicon Laboratories Inc. www.silabs.com
*******************************************************************************
*
* SPDX-License-Identifier: Zlib
diff --git a/cpu/efm32/families/efm32gg/include/vendor/efm32gg_usb_hc.h b/cpu/efm32/families/efm32gg/include/vendor/efm32gg_usb_hc.h
index 43d1aad99e..dbad44c955 100644
--- a/cpu/efm32/families/efm32gg/include/vendor/efm32gg_usb_hc.h
+++ b/cpu/efm32/families/efm32gg/include/vendor/efm32gg_usb_hc.h
@@ -1,10 +1,9 @@
/***************************************************************************//**
* @file
* @brief EFM32GG_USB_HC register and bit field definitions
- * @version 5.8.3
*******************************************************************************
* # License
- * Copyright 2019 Silicon Laboratories Inc. www.silabs.com
+ * Copyright 2020 Silicon Laboratories Inc. www.silabs.com
*******************************************************************************
*
* SPDX-License-Identifier: Zlib
diff --git a/cpu/efm32/families/efm32gg/include/vendor/efm32gg_vcmp.h b/cpu/efm32/families/efm32gg/include/vendor/efm32gg_vcmp.h
index 8b7a4d0bad..3b0e870f08 100644
--- a/cpu/efm32/families/efm32gg/include/vendor/efm32gg_vcmp.h
+++ b/cpu/efm32/families/efm32gg/include/vendor/efm32gg_vcmp.h
@@ -1,10 +1,9 @@
/***************************************************************************//**
* @file
* @brief EFM32GG_VCMP register and bit field definitions
- * @version 5.8.3
*******************************************************************************
* # License
- * Copyright 2019 Silicon Laboratories Inc. www.silabs.com
+ * Copyright 2020 Silicon Laboratories Inc. www.silabs.com
*******************************************************************************
*
* SPDX-License-Identifier: Zlib
diff --git a/cpu/efm32/families/efm32gg/include/vendor/efm32gg_wdog.h b/cpu/efm32/families/efm32gg/include/vendor/efm32gg_wdog.h
index 9afbe560a2..31130303da 100644
--- a/cpu/efm32/families/efm32gg/include/vendor/efm32gg_wdog.h
+++ b/cpu/efm32/families/efm32gg/include/vendor/efm32gg_wdog.h
@@ -1,10 +1,9 @@
/***************************************************************************//**
* @file
* @brief EFM32GG_WDOG register and bit field definitions
- * @version 5.8.3
*******************************************************************************
* # License
- * Copyright 2019 Silicon Laboratories Inc. www.silabs.com
+ * Copyright 2020 Silicon Laboratories Inc. www.silabs.com
*******************************************************************************
*
* SPDX-License-Identifier: Zlib
diff --git a/cpu/efm32/families/efm32gg/include/vendor/em_device.h b/cpu/efm32/families/efm32gg/include/vendor/em_device.h
index c8d1d02469..0205b6e7fc 100644
--- a/cpu/efm32/families/efm32gg/include/vendor/em_device.h
+++ b/cpu/efm32/families/efm32gg/include/vendor/em_device.h
@@ -11,10 +11,9 @@
* Add "#include "em_device.h" to your source files
* @endverbatim
*
- * @version 5.8.3
*******************************************************************************
* # License
- * Copyright 2019 Silicon Laboratories Inc. www.silabs.com
+ * Copyright 2020 Silicon Laboratories Inc. www.silabs.com
*******************************************************************************
*
* SPDX-License-Identifier: Zlib
diff --git a/cpu/efm32/families/efm32gg/include/vendor/system_efm32gg.h b/cpu/efm32/families/efm32gg/include/vendor/system_efm32gg.h
index 62f608dfd1..fbe13a6b62 100644
--- a/cpu/efm32/families/efm32gg/include/vendor/system_efm32gg.h
+++ b/cpu/efm32/families/efm32gg/include/vendor/system_efm32gg.h
@@ -1,10 +1,9 @@
/***************************************************************************//**
* @file
* @brief CMSIS Cortex-M3 System Layer for EFM32GG devices.
- * @version 5.8.3
*******************************************************************************
* # License
- * Copyright 2019 Silicon Laboratories Inc. www.silabs.com
+ * Copyright 2020 Silicon Laboratories Inc. www.silabs.com
*******************************************************************************
*
* SPDX-License-Identifier: Zlib
@@ -47,12 +46,29 @@ extern "C" {
* @{
******************************************************************************/
+/*******************************************************************************
+ ****************************** TYPEDEFS ***********************************
+ ******************************************************************************/
+
+/* Interrupt vectortable entry */
+typedef union {
+ void (*pFunc)(void);
+ void *topOfStack;
+} tVectorEntry;
+
/*******************************************************************************
************************** GLOBAL VARIABLES *******************************
******************************************************************************/
extern uint32_t SystemCoreClock; /**< System Clock Frequency (Core Clock) */
+#if defined(__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+#if defined(__ICCARM__) /* IAR requires the __vector_table symbol */
+#define __Vectors __vector_table
+#endif
+extern const tVectorEntry __Vectors[];
+#endif
+
/*******************************************************************************
***************************** PROTOTYPES **********************************
******************************************************************************/
diff --git a/cpu/efm32/families/efm32gg/system.c b/cpu/efm32/families/efm32gg/system.c
index f90288911d..7fe85777b6 100644
--- a/cpu/efm32/families/efm32gg/system.c
+++ b/cpu/efm32/families/efm32gg/system.c
@@ -1,10 +1,9 @@
/***************************************************************************//**
* @file
* @brief CMSIS Cortex-M3 System Layer for EFM32GG devices.
- * @version 5.8.3
*******************************************************************************
* # License
- * Copyright 2019 Silicon Laboratories Inc. www.silabs.com
+ * Copyright 2020 Silicon Laboratories Inc. www.silabs.com
*******************************************************************************
*
* SPDX-License-Identifier: Zlib
@@ -106,13 +105,6 @@ uint32_t SystemCoreClock = 14000000UL;
************************** GLOBAL FUNCTIONS *******************************
******************************************************************************/
-#if defined(__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
-#if defined(__ICCARM__) /* IAR requires the __vector_table symbol */
-#define __Vectors __vector_table
-#endif
-extern uint32_t __Vectors;
-#endif
-
/***************************************************************************//**
* @brief
* Get the current core clock frequency.
diff --git a/cpu/efm32/families/efm32lg/include/vendor/efm32lg990f256.h b/cpu/efm32/families/efm32lg/include/vendor/efm32lg990f256.h
index b39ab20074..021d8a6198 100644
--- a/cpu/efm32/families/efm32lg/include/vendor/efm32lg990f256.h
+++ b/cpu/efm32/families/efm32lg/include/vendor/efm32lg990f256.h
@@ -2,10 +2,9 @@
* @file
* @brief CMSIS Cortex-M Peripheral Access Layer Header File
* for EFM32LG990F256
- * @version 5.8.3
*******************************************************************************
* # License
- * Copyright 2019 Silicon Laboratories Inc. www.silabs.com
+ * Copyright 2020 Silicon Laboratories Inc. www.silabs.com
*******************************************************************************
*
* SPDX-License-Identifier: Zlib
@@ -145,6 +144,30 @@ typedef enum IRQn{
#define PART_NUMBER "EFM32LG990F256" /**< Part Number */
/** Memory Base addresses and limits */
+#define RAM_MEM_BASE (0x20000000UL) /**< RAM base address */
+#define RAM_MEM_SIZE (0x40000UL) /**< RAM available address space */
+#define RAM_MEM_END (0x2003FFFFUL) /**< RAM end address */
+#define RAM_MEM_BITS (0x18UL) /**< RAM used bits */
+#define EBI_CODE_MEM_BASE (0x12000000UL) /**< EBI_CODE base address */
+#define EBI_CODE_MEM_SIZE (0xE000000UL) /**< EBI_CODE available address space */
+#define EBI_CODE_MEM_END (0x1FFFFFFFUL) /**< EBI_CODE end address */
+#define EBI_CODE_MEM_BITS (0x28UL) /**< EBI_CODE used bits */
+#define USBC_MEM_BASE (0x40100000UL) /**< USBC base address */
+#define USBC_MEM_SIZE (0x40000UL) /**< USBC available address space */
+#define USBC_MEM_END (0x4013FFFFUL) /**< USBC end address */
+#define USBC_MEM_BITS (0x18UL) /**< USBC used bits */
+#define RAM_CODE_MEM_BASE (0x10000000UL) /**< RAM_CODE base address */
+#define RAM_CODE_MEM_SIZE (0x20000UL) /**< RAM_CODE available address space */
+#define RAM_CODE_MEM_END (0x1001FFFFUL) /**< RAM_CODE end address */
+#define RAM_CODE_MEM_BITS (0x17UL) /**< RAM_CODE used bits */
+#define PER_MEM_BASE (0x40000000UL) /**< PER base address */
+#define PER_MEM_SIZE (0xE0000UL) /**< PER available address space */
+#define PER_MEM_END (0x400DFFFFUL) /**< PER end address */
+#define PER_MEM_BITS (0x20UL) /**< PER used bits */
+#define EBI_MEM_BASE (0x80000000UL) /**< EBI base address */
+#define EBI_MEM_SIZE (0x40000000UL) /**< EBI available address space */
+#define EBI_MEM_END (0xBFFFFFFFUL) /**< EBI end address */
+#define EBI_MEM_BITS (0x30UL) /**< EBI used bits */
#define FLASH_MEM_BASE (0x0UL) /**< FLASH base address */
#define FLASH_MEM_SIZE (0x10000000UL) /**< FLASH available address space */
#define FLASH_MEM_END (0xFFFFFFFUL) /**< FLASH end address */
@@ -153,30 +176,6 @@ typedef enum IRQn{
#define AES_MEM_SIZE (0x400UL) /**< AES available address space */
#define AES_MEM_END (0x400E03FFUL) /**< AES end address */
#define AES_MEM_BITS (0x10UL) /**< AES used bits */
-#define USBC_MEM_BASE (0x40100000UL) /**< USBC base address */
-#define USBC_MEM_SIZE (0x40000UL) /**< USBC available address space */
-#define USBC_MEM_END (0x4013FFFFUL) /**< USBC end address */
-#define USBC_MEM_BITS (0x18UL) /**< USBC used bits */
-#define EBI_CODE_MEM_BASE (0x12000000UL) /**< EBI_CODE base address */
-#define EBI_CODE_MEM_SIZE (0xE000000UL) /**< EBI_CODE available address space */
-#define EBI_CODE_MEM_END (0x1FFFFFFFUL) /**< EBI_CODE end address */
-#define EBI_CODE_MEM_BITS (0x28UL) /**< EBI_CODE used bits */
-#define PER_MEM_BASE (0x40000000UL) /**< PER base address */
-#define PER_MEM_SIZE (0xE0000UL) /**< PER available address space */
-#define PER_MEM_END (0x400DFFFFUL) /**< PER end address */
-#define PER_MEM_BITS (0x20UL) /**< PER used bits */
-#define RAM_MEM_BASE (0x20000000UL) /**< RAM base address */
-#define RAM_MEM_SIZE (0x40000UL) /**< RAM available address space */
-#define RAM_MEM_END (0x2003FFFFUL) /**< RAM end address */
-#define RAM_MEM_BITS (0x18UL) /**< RAM used bits */
-#define RAM_CODE_MEM_BASE (0x10000000UL) /**< RAM_CODE base address */
-#define RAM_CODE_MEM_SIZE (0x20000UL) /**< RAM_CODE available address space */
-#define RAM_CODE_MEM_END (0x1001FFFFUL) /**< RAM_CODE end address */
-#define RAM_CODE_MEM_BITS (0x17UL) /**< RAM_CODE used bits */
-#define EBI_MEM_BASE (0x80000000UL) /**< EBI base address */
-#define EBI_MEM_SIZE (0x40000000UL) /**< EBI available address space */
-#define EBI_MEM_END (0xBFFFFFFFUL) /**< EBI end address */
-#define EBI_MEM_BITS (0x30UL) /**< EBI used bits */
/** Bit banding area */
#define BITBAND_PER_BASE (0x42000000UL) /**< Peripheral Address Space bit-band area */
diff --git a/cpu/efm32/families/efm32lg/include/vendor/efm32lg_acmp.h b/cpu/efm32/families/efm32lg/include/vendor/efm32lg_acmp.h
index c6ed0f7cab..6dd9063cfc 100644
--- a/cpu/efm32/families/efm32lg/include/vendor/efm32lg_acmp.h
+++ b/cpu/efm32/families/efm32lg/include/vendor/efm32lg_acmp.h
@@ -1,10 +1,9 @@
/***************************************************************************//**
* @file
* @brief EFM32LG_ACMP register and bit field definitions
- * @version 5.8.3
*******************************************************************************
* # License
- * Copyright 2019 Silicon Laboratories Inc. www.silabs.com
+ * Copyright 2020 Silicon Laboratories Inc. www.silabs.com
*******************************************************************************
*
* SPDX-License-Identifier: Zlib
diff --git a/cpu/efm32/families/efm32lg/include/vendor/efm32lg_adc.h b/cpu/efm32/families/efm32lg/include/vendor/efm32lg_adc.h
index 6fe73cd442..388d2e985c 100644
--- a/cpu/efm32/families/efm32lg/include/vendor/efm32lg_adc.h
+++ b/cpu/efm32/families/efm32lg/include/vendor/efm32lg_adc.h
@@ -1,10 +1,9 @@
/***************************************************************************//**
* @file
* @brief EFM32LG_ADC register and bit field definitions
- * @version 5.8.3
*******************************************************************************
* # License
- * Copyright 2019 Silicon Laboratories Inc. www.silabs.com
+ * Copyright 2020 Silicon Laboratories Inc. www.silabs.com
*******************************************************************************
*
* SPDX-License-Identifier: Zlib
@@ -263,16 +262,16 @@ typedef struct {
#define _ADC_SINGLECTRL_INPUTSEL_SHIFT 8 /**< Shift value for ADC_INPUTSEL */
#define _ADC_SINGLECTRL_INPUTSEL_MASK 0xF00UL /**< Bit mask for ADC_INPUTSEL */
#define _ADC_SINGLECTRL_INPUTSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SINGLECTRL */
-#define _ADC_SINGLECTRL_INPUTSEL_CH0 0x00000000UL /**< Mode CH0 for ADC_SINGLECTRL */
#define _ADC_SINGLECTRL_INPUTSEL_CH0CH1 0x00000000UL /**< Mode CH0CH1 for ADC_SINGLECTRL */
-#define _ADC_SINGLECTRL_INPUTSEL_CH1 0x00000001UL /**< Mode CH1 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_INPUTSEL_CH0 0x00000000UL /**< Mode CH0 for ADC_SINGLECTRL */
#define _ADC_SINGLECTRL_INPUTSEL_CH2CH3 0x00000001UL /**< Mode CH2CH3 for ADC_SINGLECTRL */
-#define _ADC_SINGLECTRL_INPUTSEL_CH2 0x00000002UL /**< Mode CH2 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_INPUTSEL_CH1 0x00000001UL /**< Mode CH1 for ADC_SINGLECTRL */
#define _ADC_SINGLECTRL_INPUTSEL_CH4CH5 0x00000002UL /**< Mode CH4CH5 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_INPUTSEL_CH2 0x00000002UL /**< Mode CH2 for ADC_SINGLECTRL */
#define _ADC_SINGLECTRL_INPUTSEL_CH6CH7 0x00000003UL /**< Mode CH6CH7 for ADC_SINGLECTRL */
#define _ADC_SINGLECTRL_INPUTSEL_CH3 0x00000003UL /**< Mode CH3 for ADC_SINGLECTRL */
-#define _ADC_SINGLECTRL_INPUTSEL_CH4 0x00000004UL /**< Mode CH4 for ADC_SINGLECTRL */
#define _ADC_SINGLECTRL_INPUTSEL_DIFF0 0x00000004UL /**< Mode DIFF0 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_INPUTSEL_CH4 0x00000004UL /**< Mode CH4 for ADC_SINGLECTRL */
#define _ADC_SINGLECTRL_INPUTSEL_CH5 0x00000005UL /**< Mode CH5 for ADC_SINGLECTRL */
#define _ADC_SINGLECTRL_INPUTSEL_CH6 0x00000006UL /**< Mode CH6 for ADC_SINGLECTRL */
#define _ADC_SINGLECTRL_INPUTSEL_CH7 0x00000007UL /**< Mode CH7 for ADC_SINGLECTRL */
@@ -284,16 +283,16 @@ typedef struct {
#define _ADC_SINGLECTRL_INPUTSEL_DAC0OUT0 0x0000000DUL /**< Mode DAC0OUT0 for ADC_SINGLECTRL */
#define _ADC_SINGLECTRL_INPUTSEL_DAC0OUT1 0x0000000EUL /**< Mode DAC0OUT1 for ADC_SINGLECTRL */
#define ADC_SINGLECTRL_INPUTSEL_DEFAULT (_ADC_SINGLECTRL_INPUTSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for ADC_SINGLECTRL */
-#define ADC_SINGLECTRL_INPUTSEL_CH0 (_ADC_SINGLECTRL_INPUTSEL_CH0 << 8) /**< Shifted mode CH0 for ADC_SINGLECTRL */
#define ADC_SINGLECTRL_INPUTSEL_CH0CH1 (_ADC_SINGLECTRL_INPUTSEL_CH0CH1 << 8) /**< Shifted mode CH0CH1 for ADC_SINGLECTRL */
-#define ADC_SINGLECTRL_INPUTSEL_CH1 (_ADC_SINGLECTRL_INPUTSEL_CH1 << 8) /**< Shifted mode CH1 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_INPUTSEL_CH0 (_ADC_SINGLECTRL_INPUTSEL_CH0 << 8) /**< Shifted mode CH0 for ADC_SINGLECTRL */
#define ADC_SINGLECTRL_INPUTSEL_CH2CH3 (_ADC_SINGLECTRL_INPUTSEL_CH2CH3 << 8) /**< Shifted mode CH2CH3 for ADC_SINGLECTRL */
-#define ADC_SINGLECTRL_INPUTSEL_CH2 (_ADC_SINGLECTRL_INPUTSEL_CH2 << 8) /**< Shifted mode CH2 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_INPUTSEL_CH1 (_ADC_SINGLECTRL_INPUTSEL_CH1 << 8) /**< Shifted mode CH1 for ADC_SINGLECTRL */
#define ADC_SINGLECTRL_INPUTSEL_CH4CH5 (_ADC_SINGLECTRL_INPUTSEL_CH4CH5 << 8) /**< Shifted mode CH4CH5 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_INPUTSEL_CH2 (_ADC_SINGLECTRL_INPUTSEL_CH2 << 8) /**< Shifted mode CH2 for ADC_SINGLECTRL */
#define ADC_SINGLECTRL_INPUTSEL_CH6CH7 (_ADC_SINGLECTRL_INPUTSEL_CH6CH7 << 8) /**< Shifted mode CH6CH7 for ADC_SINGLECTRL */
#define ADC_SINGLECTRL_INPUTSEL_CH3 (_ADC_SINGLECTRL_INPUTSEL_CH3 << 8) /**< Shifted mode CH3 for ADC_SINGLECTRL */
-#define ADC_SINGLECTRL_INPUTSEL_CH4 (_ADC_SINGLECTRL_INPUTSEL_CH4 << 8) /**< Shifted mode CH4 for ADC_SINGLECTRL */
#define ADC_SINGLECTRL_INPUTSEL_DIFF0 (_ADC_SINGLECTRL_INPUTSEL_DIFF0 << 8) /**< Shifted mode DIFF0 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_INPUTSEL_CH4 (_ADC_SINGLECTRL_INPUTSEL_CH4 << 8) /**< Shifted mode CH4 for ADC_SINGLECTRL */
#define ADC_SINGLECTRL_INPUTSEL_CH5 (_ADC_SINGLECTRL_INPUTSEL_CH5 << 8) /**< Shifted mode CH5 for ADC_SINGLECTRL */
#define ADC_SINGLECTRL_INPUTSEL_CH6 (_ADC_SINGLECTRL_INPUTSEL_CH6 << 8) /**< Shifted mode CH6 for ADC_SINGLECTRL */
#define ADC_SINGLECTRL_INPUTSEL_CH7 (_ADC_SINGLECTRL_INPUTSEL_CH7 << 8) /**< Shifted mode CH7 for ADC_SINGLECTRL */
@@ -415,12 +414,12 @@ typedef struct {
#define _ADC_SCANCTRL_INPUTMASK_SHIFT 8 /**< Shift value for ADC_INPUTMASK */
#define _ADC_SCANCTRL_INPUTMASK_MASK 0xFF00UL /**< Bit mask for ADC_INPUTMASK */
#define _ADC_SCANCTRL_INPUTMASK_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SCANCTRL */
-#define _ADC_SCANCTRL_INPUTMASK_CH0 0x00000001UL /**< Mode CH0 for ADC_SCANCTRL */
#define _ADC_SCANCTRL_INPUTMASK_CH0CH1 0x00000001UL /**< Mode CH0CH1 for ADC_SCANCTRL */
-#define _ADC_SCANCTRL_INPUTMASK_CH1 0x00000002UL /**< Mode CH1 for ADC_SCANCTRL */
+#define _ADC_SCANCTRL_INPUTMASK_CH0 0x00000001UL /**< Mode CH0 for ADC_SCANCTRL */
#define _ADC_SCANCTRL_INPUTMASK_CH2CH3 0x00000002UL /**< Mode CH2CH3 for ADC_SCANCTRL */
-#define _ADC_SCANCTRL_INPUTMASK_CH2 0x00000004UL /**< Mode CH2 for ADC_SCANCTRL */
+#define _ADC_SCANCTRL_INPUTMASK_CH1 0x00000002UL /**< Mode CH1 for ADC_SCANCTRL */
#define _ADC_SCANCTRL_INPUTMASK_CH4CH5 0x00000004UL /**< Mode CH4CH5 for ADC_SCANCTRL */
+#define _ADC_SCANCTRL_INPUTMASK_CH2 0x00000004UL /**< Mode CH2 for ADC_SCANCTRL */
#define _ADC_SCANCTRL_INPUTMASK_CH6CH7 0x00000008UL /**< Mode CH6CH7 for ADC_SCANCTRL */
#define _ADC_SCANCTRL_INPUTMASK_CH3 0x00000008UL /**< Mode CH3 for ADC_SCANCTRL */
#define _ADC_SCANCTRL_INPUTMASK_CH4 0x00000010UL /**< Mode CH4 for ADC_SCANCTRL */
@@ -428,12 +427,12 @@ typedef struct {
#define _ADC_SCANCTRL_INPUTMASK_CH6 0x00000040UL /**< Mode CH6 for ADC_SCANCTRL */
#define _ADC_SCANCTRL_INPUTMASK_CH7 0x00000080UL /**< Mode CH7 for ADC_SCANCTRL */
#define ADC_SCANCTRL_INPUTMASK_DEFAULT (_ADC_SCANCTRL_INPUTMASK_DEFAULT << 8) /**< Shifted mode DEFAULT for ADC_SCANCTRL */
-#define ADC_SCANCTRL_INPUTMASK_CH0 (_ADC_SCANCTRL_INPUTMASK_CH0 << 8) /**< Shifted mode CH0 for ADC_SCANCTRL */
#define ADC_SCANCTRL_INPUTMASK_CH0CH1 (_ADC_SCANCTRL_INPUTMASK_CH0CH1 << 8) /**< Shifted mode CH0CH1 for ADC_SCANCTRL */
-#define ADC_SCANCTRL_INPUTMASK_CH1 (_ADC_SCANCTRL_INPUTMASK_CH1 << 8) /**< Shifted mode CH1 for ADC_SCANCTRL */
+#define ADC_SCANCTRL_INPUTMASK_CH0 (_ADC_SCANCTRL_INPUTMASK_CH0 << 8) /**< Shifted mode CH0 for ADC_SCANCTRL */
#define ADC_SCANCTRL_INPUTMASK_CH2CH3 (_ADC_SCANCTRL_INPUTMASK_CH2CH3 << 8) /**< Shifted mode CH2CH3 for ADC_SCANCTRL */
-#define ADC_SCANCTRL_INPUTMASK_CH2 (_ADC_SCANCTRL_INPUTMASK_CH2 << 8) /**< Shifted mode CH2 for ADC_SCANCTRL */
+#define ADC_SCANCTRL_INPUTMASK_CH1 (_ADC_SCANCTRL_INPUTMASK_CH1 << 8) /**< Shifted mode CH1 for ADC_SCANCTRL */
#define ADC_SCANCTRL_INPUTMASK_CH4CH5 (_ADC_SCANCTRL_INPUTMASK_CH4CH5 << 8) /**< Shifted mode CH4CH5 for ADC_SCANCTRL */
+#define ADC_SCANCTRL_INPUTMASK_CH2 (_ADC_SCANCTRL_INPUTMASK_CH2 << 8) /**< Shifted mode CH2 for ADC_SCANCTRL */
#define ADC_SCANCTRL_INPUTMASK_CH6CH7 (_ADC_SCANCTRL_INPUTMASK_CH6CH7 << 8) /**< Shifted mode CH6CH7 for ADC_SCANCTRL */
#define ADC_SCANCTRL_INPUTMASK_CH3 (_ADC_SCANCTRL_INPUTMASK_CH3 << 8) /**< Shifted mode CH3 for ADC_SCANCTRL */
#define ADC_SCANCTRL_INPUTMASK_CH4 (_ADC_SCANCTRL_INPUTMASK_CH4 << 8) /**< Shifted mode CH4 for ADC_SCANCTRL */
diff --git a/cpu/efm32/families/efm32lg/include/vendor/efm32lg_aes.h b/cpu/efm32/families/efm32lg/include/vendor/efm32lg_aes.h
index a7c38f5896..9dc541bb2b 100644
--- a/cpu/efm32/families/efm32lg/include/vendor/efm32lg_aes.h
+++ b/cpu/efm32/families/efm32lg/include/vendor/efm32lg_aes.h
@@ -1,10 +1,9 @@
/***************************************************************************//**
* @file
* @brief EFM32LG_AES register and bit field definitions
- * @version 5.8.3
*******************************************************************************
* # License
- * Copyright 2019 Silicon Laboratories Inc. www.silabs.com
+ * Copyright 2020 Silicon Laboratories Inc. www.silabs.com
*******************************************************************************
*
* SPDX-License-Identifier: Zlib
diff --git a/cpu/efm32/families/efm32lg/include/vendor/efm32lg_af_pins.h b/cpu/efm32/families/efm32lg/include/vendor/efm32lg_af_pins.h
index d22688ce82..72a6915099 100644
--- a/cpu/efm32/families/efm32lg/include/vendor/efm32lg_af_pins.h
+++ b/cpu/efm32/families/efm32lg/include/vendor/efm32lg_af_pins.h
@@ -1,10 +1,9 @@
/***************************************************************************//**
* @file
* @brief EFM32LG_AF_PINS register and bit field definitions
- * @version 5.8.3
*******************************************************************************
* # License
- * Copyright 2019 Silicon Laboratories Inc. www.silabs.com
+ * Copyright 2020 Silicon Laboratories Inc. www.silabs.com
*******************************************************************************
*
* SPDX-License-Identifier: Zlib
diff --git a/cpu/efm32/families/efm32lg/include/vendor/efm32lg_af_ports.h b/cpu/efm32/families/efm32lg/include/vendor/efm32lg_af_ports.h
index 39797c4372..4a2f32c572 100644
--- a/cpu/efm32/families/efm32lg/include/vendor/efm32lg_af_ports.h
+++ b/cpu/efm32/families/efm32lg/include/vendor/efm32lg_af_ports.h
@@ -1,10 +1,9 @@
/***************************************************************************//**
* @file
* @brief EFM32LG_AF_PORTS register and bit field definitions
- * @version 5.8.3
*******************************************************************************
* # License
- * Copyright 2019 Silicon Laboratories Inc. www.silabs.com
+ * Copyright 2020 Silicon Laboratories Inc. www.silabs.com
*******************************************************************************
*
* SPDX-License-Identifier: Zlib
diff --git a/cpu/efm32/families/efm32lg/include/vendor/efm32lg_burtc.h b/cpu/efm32/families/efm32lg/include/vendor/efm32lg_burtc.h
index c45dbf9ea6..f6dea07f8f 100644
--- a/cpu/efm32/families/efm32lg/include/vendor/efm32lg_burtc.h
+++ b/cpu/efm32/families/efm32lg/include/vendor/efm32lg_burtc.h
@@ -1,10 +1,9 @@
/***************************************************************************//**
* @file
* @brief EFM32LG_BURTC register and bit field definitions
- * @version 5.8.3
*******************************************************************************
* # License
- * Copyright 2019 Silicon Laboratories Inc. www.silabs.com
+ * Copyright 2020 Silicon Laboratories Inc. www.silabs.com
*******************************************************************************
*
* SPDX-License-Identifier: Zlib
@@ -264,13 +263,13 @@ typedef struct {
#define _BURTC_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for BURTC_LOCKKEY */
#define _BURTC_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for BURTC_LOCKKEY */
#define _BURTC_LOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_LOCK */
-#define _BURTC_LOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for BURTC_LOCK */
#define _BURTC_LOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for BURTC_LOCK */
+#define _BURTC_LOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for BURTC_LOCK */
#define _BURTC_LOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for BURTC_LOCK */
#define _BURTC_LOCK_LOCKKEY_UNLOCK 0x0000AEE8UL /**< Mode UNLOCK for BURTC_LOCK */
#define BURTC_LOCK_LOCKKEY_DEFAULT (_BURTC_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for BURTC_LOCK */
-#define BURTC_LOCK_LOCKKEY_LOCK (_BURTC_LOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for BURTC_LOCK */
#define BURTC_LOCK_LOCKKEY_UNLOCKED (_BURTC_LOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for BURTC_LOCK */
+#define BURTC_LOCK_LOCKKEY_LOCK (_BURTC_LOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for BURTC_LOCK */
#define BURTC_LOCK_LOCKKEY_LOCKED (_BURTC_LOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for BURTC_LOCK */
#define BURTC_LOCK_LOCKKEY_UNLOCK (_BURTC_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for BURTC_LOCK */
diff --git a/cpu/efm32/families/efm32lg/include/vendor/efm32lg_burtc_ret.h b/cpu/efm32/families/efm32lg/include/vendor/efm32lg_burtc_ret.h
index be133e875d..3d96857db0 100644
--- a/cpu/efm32/families/efm32lg/include/vendor/efm32lg_burtc_ret.h
+++ b/cpu/efm32/families/efm32lg/include/vendor/efm32lg_burtc_ret.h
@@ -1,10 +1,9 @@
/***************************************************************************//**
* @file
* @brief EFM32LG_BURTC_RET register and bit field definitions
- * @version 5.8.3
*******************************************************************************
* # License
- * Copyright 2019 Silicon Laboratories Inc. www.silabs.com
+ * Copyright 2020 Silicon Laboratories Inc. www.silabs.com
*******************************************************************************
*
* SPDX-License-Identifier: Zlib
diff --git a/cpu/efm32/families/efm32lg/include/vendor/efm32lg_calibrate.h b/cpu/efm32/families/efm32lg/include/vendor/efm32lg_calibrate.h
index b68e4c6c69..27cd599165 100644
--- a/cpu/efm32/families/efm32lg/include/vendor/efm32lg_calibrate.h
+++ b/cpu/efm32/families/efm32lg/include/vendor/efm32lg_calibrate.h
@@ -1,10 +1,9 @@
/***************************************************************************//**
* @file
* @brief EFM32LG_CALIBRATE register and bit field definitions
- * @version 5.8.3
*******************************************************************************
* # License
- * Copyright 2019 Silicon Laboratories Inc. www.silabs.com
+ * Copyright 2020 Silicon Laboratories Inc. www.silabs.com
*******************************************************************************
*
* SPDX-License-Identifier: Zlib
diff --git a/cpu/efm32/families/efm32lg/include/vendor/efm32lg_cmu.h b/cpu/efm32/families/efm32lg/include/vendor/efm32lg_cmu.h
index a858092644..754348cbac 100644
--- a/cpu/efm32/families/efm32lg/include/vendor/efm32lg_cmu.h
+++ b/cpu/efm32/families/efm32lg/include/vendor/efm32lg_cmu.h
@@ -1,10 +1,9 @@
/***************************************************************************//**
* @file
* @brief EFM32LG_CMU register and bit field definitions
- * @version 5.8.3
*******************************************************************************
* # License
- * Copyright 2019 Silicon Laboratories Inc. www.silabs.com
+ * Copyright 2020 Silicon Laboratories Inc. www.silabs.com
*******************************************************************************
*
* SPDX-License-Identifier: Zlib
@@ -1247,13 +1246,13 @@ typedef struct {
#define _CMU_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for CMU_LOCKKEY */
#define _CMU_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for CMU_LOCKKEY */
#define _CMU_LOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LOCK */
-#define _CMU_LOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for CMU_LOCK */
#define _CMU_LOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for CMU_LOCK */
+#define _CMU_LOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for CMU_LOCK */
#define _CMU_LOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for CMU_LOCK */
#define _CMU_LOCK_LOCKKEY_UNLOCK 0x0000580EUL /**< Mode UNLOCK for CMU_LOCK */
#define CMU_LOCK_LOCKKEY_DEFAULT (_CMU_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LOCK */
-#define CMU_LOCK_LOCKKEY_LOCK (_CMU_LOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for CMU_LOCK */
#define CMU_LOCK_LOCKKEY_UNLOCKED (_CMU_LOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for CMU_LOCK */
+#define CMU_LOCK_LOCKKEY_LOCK (_CMU_LOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for CMU_LOCK */
#define CMU_LOCK_LOCKKEY_LOCKED (_CMU_LOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for CMU_LOCK */
#define CMU_LOCK_LOCKKEY_UNLOCK (_CMU_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for CMU_LOCK */
diff --git a/cpu/efm32/families/efm32lg/include/vendor/efm32lg_dac.h b/cpu/efm32/families/efm32lg/include/vendor/efm32lg_dac.h
index 362b8835e7..96c3785940 100644
--- a/cpu/efm32/families/efm32lg/include/vendor/efm32lg_dac.h
+++ b/cpu/efm32/families/efm32lg/include/vendor/efm32lg_dac.h
@@ -1,10 +1,9 @@
/***************************************************************************//**
* @file
* @brief EFM32LG_DAC register and bit field definitions
- * @version 5.8.3
*******************************************************************************
* # License
- * Copyright 2019 Silicon Laboratories Inc. www.silabs.com
+ * Copyright 2020 Silicon Laboratories Inc. www.silabs.com
*******************************************************************************
*
* SPDX-License-Identifier: Zlib
diff --git a/cpu/efm32/families/efm32lg/include/vendor/efm32lg_devinfo.h b/cpu/efm32/families/efm32lg/include/vendor/efm32lg_devinfo.h
index b913471944..e7b0393d99 100644
--- a/cpu/efm32/families/efm32lg/include/vendor/efm32lg_devinfo.h
+++ b/cpu/efm32/families/efm32lg/include/vendor/efm32lg_devinfo.h
@@ -1,10 +1,9 @@
/***************************************************************************//**
* @file
* @brief EFM32LG_DEVINFO register and bit field definitions
- * @version 5.8.3
*******************************************************************************
* # License
- * Copyright 2019 Silicon Laboratories Inc. www.silabs.com
+ * Copyright 2020 Silicon Laboratories Inc. www.silabs.com
*******************************************************************************
*
* SPDX-License-Identifier: Zlib
diff --git a/cpu/efm32/families/efm32lg/include/vendor/efm32lg_dma.h b/cpu/efm32/families/efm32lg/include/vendor/efm32lg_dma.h
index b5c5a82f0c..3c76ad08b1 100644
--- a/cpu/efm32/families/efm32lg/include/vendor/efm32lg_dma.h
+++ b/cpu/efm32/families/efm32lg/include/vendor/efm32lg_dma.h
@@ -1,10 +1,9 @@
/***************************************************************************//**
* @file
* @brief EFM32LG_DMA register and bit field definitions
- * @version 5.8.3
*******************************************************************************
* # License
- * Copyright 2019 Silicon Laboratories Inc. www.silabs.com
+ * Copyright 2020 Silicon Laboratories Inc. www.silabs.com
*******************************************************************************
*
* SPDX-License-Identifier: Zlib
diff --git a/cpu/efm32/families/efm32lg/include/vendor/efm32lg_dma_ch.h b/cpu/efm32/families/efm32lg/include/vendor/efm32lg_dma_ch.h
index e170b33295..3d803e24fc 100644
--- a/cpu/efm32/families/efm32lg/include/vendor/efm32lg_dma_ch.h
+++ b/cpu/efm32/families/efm32lg/include/vendor/efm32lg_dma_ch.h
@@ -1,10 +1,9 @@
/***************************************************************************//**
* @file
* @brief EFM32LG_DMA_CH register and bit field definitions
- * @version 5.8.3
*******************************************************************************
* # License
- * Copyright 2019 Silicon Laboratories Inc. www.silabs.com
+ * Copyright 2020 Silicon Laboratories Inc. www.silabs.com
*******************************************************************************
*
* SPDX-License-Identifier: Zlib
diff --git a/cpu/efm32/families/efm32lg/include/vendor/efm32lg_dma_descriptor.h b/cpu/efm32/families/efm32lg/include/vendor/efm32lg_dma_descriptor.h
index 7426740cf6..f6d688cb97 100644
--- a/cpu/efm32/families/efm32lg/include/vendor/efm32lg_dma_descriptor.h
+++ b/cpu/efm32/families/efm32lg/include/vendor/efm32lg_dma_descriptor.h
@@ -1,10 +1,9 @@
/***************************************************************************//**
* @file
* @brief EFM32LG_DMA_DESCRIPTOR register and bit field definitions
- * @version 5.8.3
*******************************************************************************
* # License
- * Copyright 2019 Silicon Laboratories Inc. www.silabs.com
+ * Copyright 2020 Silicon Laboratories Inc. www.silabs.com
*******************************************************************************
*
* SPDX-License-Identifier: Zlib
diff --git a/cpu/efm32/families/efm32lg/include/vendor/efm32lg_dmactrl.h b/cpu/efm32/families/efm32lg/include/vendor/efm32lg_dmactrl.h
index e59b214047..fdede0961c 100644
--- a/cpu/efm32/families/efm32lg/include/vendor/efm32lg_dmactrl.h
+++ b/cpu/efm32/families/efm32lg/include/vendor/efm32lg_dmactrl.h
@@ -1,10 +1,9 @@
/***************************************************************************//**
* @file
* @brief EFM32LG_DMACTRL register and bit field definitions
- * @version 5.8.3
*******************************************************************************
* # License
- * Copyright 2019 Silicon Laboratories Inc. www.silabs.com
+ * Copyright 2020 Silicon Laboratories Inc. www.silabs.com
*******************************************************************************
*
* SPDX-License-Identifier: Zlib
diff --git a/cpu/efm32/families/efm32lg/include/vendor/efm32lg_dmareq.h b/cpu/efm32/families/efm32lg/include/vendor/efm32lg_dmareq.h
index 99cceaac9f..3bd3a76016 100644
--- a/cpu/efm32/families/efm32lg/include/vendor/efm32lg_dmareq.h
+++ b/cpu/efm32/families/efm32lg/include/vendor/efm32lg_dmareq.h
@@ -1,10 +1,9 @@
/***************************************************************************//**
* @file
* @brief EFM32LG_DMAREQ register and bit field definitions
- * @version 5.8.3
*******************************************************************************
* # License
- * Copyright 2019 Silicon Laboratories Inc. www.silabs.com
+ * Copyright 2020 Silicon Laboratories Inc. www.silabs.com
*******************************************************************************
*
* SPDX-License-Identifier: Zlib
diff --git a/cpu/efm32/families/efm32lg/include/vendor/efm32lg_ebi.h b/cpu/efm32/families/efm32lg/include/vendor/efm32lg_ebi.h
index 969309a628..f997ab3836 100644
--- a/cpu/efm32/families/efm32lg/include/vendor/efm32lg_ebi.h
+++ b/cpu/efm32/families/efm32lg/include/vendor/efm32lg_ebi.h
@@ -1,10 +1,9 @@
/***************************************************************************//**
* @file
* @brief EFM32LG_EBI register and bit field definitions
- * @version 5.8.3
*******************************************************************************
* # License
- * Copyright 2019 Silicon Laboratories Inc. www.silabs.com
+ * Copyright 2020 Silicon Laboratories Inc. www.silabs.com
*******************************************************************************
*
* SPDX-License-Identifier: Zlib
diff --git a/cpu/efm32/families/efm32lg/include/vendor/efm32lg_emu.h b/cpu/efm32/families/efm32lg/include/vendor/efm32lg_emu.h
index 2c312a3fc3..108d231669 100644
--- a/cpu/efm32/families/efm32lg/include/vendor/efm32lg_emu.h
+++ b/cpu/efm32/families/efm32lg/include/vendor/efm32lg_emu.h
@@ -1,10 +1,9 @@
/***************************************************************************//**
* @file
* @brief EFM32LG_EMU register and bit field definitions
- * @version 5.8.3
*******************************************************************************
* # License
- * Copyright 2019 Silicon Laboratories Inc. www.silabs.com
+ * Copyright 2020 Silicon Laboratories Inc. www.silabs.com
*******************************************************************************
*
* SPDX-License-Identifier: Zlib
@@ -107,13 +106,13 @@ typedef struct {
#define _EMU_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for EMU_LOCKKEY */
#define _EMU_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for EMU_LOCKKEY */
#define _EMU_LOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_LOCK */
-#define _EMU_LOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for EMU_LOCK */
#define _EMU_LOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for EMU_LOCK */
+#define _EMU_LOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for EMU_LOCK */
#define _EMU_LOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for EMU_LOCK */
#define _EMU_LOCK_LOCKKEY_UNLOCK 0x0000ADE8UL /**< Mode UNLOCK for EMU_LOCK */
#define EMU_LOCK_LOCKKEY_DEFAULT (_EMU_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_LOCK */
-#define EMU_LOCK_LOCKKEY_LOCK (_EMU_LOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for EMU_LOCK */
#define EMU_LOCK_LOCKKEY_UNLOCKED (_EMU_LOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for EMU_LOCK */
+#define EMU_LOCK_LOCKKEY_LOCK (_EMU_LOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for EMU_LOCK */
#define EMU_LOCK_LOCKKEY_LOCKED (_EMU_LOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for EMU_LOCK */
#define EMU_LOCK_LOCKKEY_UNLOCK (_EMU_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for EMU_LOCK */
diff --git a/cpu/efm32/families/efm32lg/include/vendor/efm32lg_etm.h b/cpu/efm32/families/efm32lg/include/vendor/efm32lg_etm.h
index 165eeddb2e..30ea35335a 100644
--- a/cpu/efm32/families/efm32lg/include/vendor/efm32lg_etm.h
+++ b/cpu/efm32/families/efm32lg/include/vendor/efm32lg_etm.h
@@ -1,10 +1,9 @@
/***************************************************************************//**
* @file
* @brief EFM32LG_ETM register and bit field definitions
- * @version 5.8.3
*******************************************************************************
* # License
- * Copyright 2019 Silicon Laboratories Inc. www.silabs.com
+ * Copyright 2020 Silicon Laboratories Inc. www.silabs.com
*******************************************************************************
*
* SPDX-License-Identifier: Zlib
diff --git a/cpu/efm32/families/efm32lg/include/vendor/efm32lg_gpio.h b/cpu/efm32/families/efm32lg/include/vendor/efm32lg_gpio.h
index 9197fd6ce8..6b69684f93 100644
--- a/cpu/efm32/families/efm32lg/include/vendor/efm32lg_gpio.h
+++ b/cpu/efm32/families/efm32lg/include/vendor/efm32lg_gpio.h
@@ -1,10 +1,9 @@
/***************************************************************************//**
* @file
* @brief EFM32LG_GPIO register and bit field definitions
- * @version 5.8.3
*******************************************************************************
* # License
- * Copyright 2019 Silicon Laboratories Inc. www.silabs.com
+ * Copyright 2020 Silicon Laboratories Inc. www.silabs.com
*******************************************************************************
*
* SPDX-License-Identifier: Zlib
@@ -1125,13 +1124,13 @@ typedef struct {
#define _GPIO_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for GPIO_LOCKKEY */
#define _GPIO_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for GPIO_LOCKKEY */
#define _GPIO_LOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_LOCK */
-#define _GPIO_LOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for GPIO_LOCK */
#define _GPIO_LOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for GPIO_LOCK */
+#define _GPIO_LOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for GPIO_LOCK */
#define _GPIO_LOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for GPIO_LOCK */
#define _GPIO_LOCK_LOCKKEY_UNLOCK 0x0000A534UL /**< Mode UNLOCK for GPIO_LOCK */
#define GPIO_LOCK_LOCKKEY_DEFAULT (_GPIO_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_LOCK */
-#define GPIO_LOCK_LOCKKEY_LOCK (_GPIO_LOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for GPIO_LOCK */
#define GPIO_LOCK_LOCKKEY_UNLOCKED (_GPIO_LOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for GPIO_LOCK */
+#define GPIO_LOCK_LOCKKEY_LOCK (_GPIO_LOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for GPIO_LOCK */
#define GPIO_LOCK_LOCKKEY_LOCKED (_GPIO_LOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for GPIO_LOCK */
#define GPIO_LOCK_LOCKKEY_UNLOCK (_GPIO_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for GPIO_LOCK */
diff --git a/cpu/efm32/families/efm32lg/include/vendor/efm32lg_gpio_p.h b/cpu/efm32/families/efm32lg/include/vendor/efm32lg_gpio_p.h
index 0fa7feb05e..2137394bc4 100644
--- a/cpu/efm32/families/efm32lg/include/vendor/efm32lg_gpio_p.h
+++ b/cpu/efm32/families/efm32lg/include/vendor/efm32lg_gpio_p.h
@@ -1,10 +1,9 @@
/***************************************************************************//**
* @file
* @brief EFM32LG_GPIO_P register and bit field definitions
- * @version 5.8.3
*******************************************************************************
* # License
- * Copyright 2019 Silicon Laboratories Inc. www.silabs.com
+ * Copyright 2020 Silicon Laboratories Inc. www.silabs.com
*******************************************************************************
*
* SPDX-License-Identifier: Zlib
diff --git a/cpu/efm32/families/efm32lg/include/vendor/efm32lg_i2c.h b/cpu/efm32/families/efm32lg/include/vendor/efm32lg_i2c.h
index 63d9819030..c51a6d8e27 100644
--- a/cpu/efm32/families/efm32lg/include/vendor/efm32lg_i2c.h
+++ b/cpu/efm32/families/efm32lg/include/vendor/efm32lg_i2c.h
@@ -1,10 +1,9 @@
/***************************************************************************//**
* @file
* @brief EFM32LG_I2C register and bit field definitions
- * @version 5.8.3
*******************************************************************************
* # License
- * Copyright 2019 Silicon Laboratories Inc. www.silabs.com
+ * Copyright 2020 Silicon Laboratories Inc. www.silabs.com
*******************************************************************************
*
* SPDX-License-Identifier: Zlib
diff --git a/cpu/efm32/families/efm32lg/include/vendor/efm32lg_lcd.h b/cpu/efm32/families/efm32lg/include/vendor/efm32lg_lcd.h
index 99a2d435dd..abcfe0b474 100644
--- a/cpu/efm32/families/efm32lg/include/vendor/efm32lg_lcd.h
+++ b/cpu/efm32/families/efm32lg/include/vendor/efm32lg_lcd.h
@@ -1,10 +1,9 @@
/***************************************************************************//**
* @file
* @brief EFM32LG_LCD register and bit field definitions
- * @version 5.8.3
*******************************************************************************
* # License
- * Copyright 2019 Silicon Laboratories Inc. www.silabs.com
+ * Copyright 2020 Silicon Laboratories Inc. www.silabs.com
*******************************************************************************
*
* SPDX-License-Identifier: Zlib
diff --git a/cpu/efm32/families/efm32lg/include/vendor/efm32lg_lesense.h b/cpu/efm32/families/efm32lg/include/vendor/efm32lg_lesense.h
index 237ad6e9bf..199a700a22 100644
--- a/cpu/efm32/families/efm32lg/include/vendor/efm32lg_lesense.h
+++ b/cpu/efm32/families/efm32lg/include/vendor/efm32lg_lesense.h
@@ -1,10 +1,9 @@
/***************************************************************************//**
* @file
* @brief EFM32LG_LESENSE register and bit field definitions
- * @version 5.8.3
*******************************************************************************
* # License
- * Copyright 2019 Silicon Laboratories Inc. www.silabs.com
+ * Copyright 2020 Silicon Laboratories Inc. www.silabs.com
*******************************************************************************
*
* SPDX-License-Identifier: Zlib
@@ -1731,27 +1730,27 @@ typedef struct {
#define _LESENSE_ST_TCONFA_PRSACT_MASK 0x7000UL /**< Bit mask for LESENSE_PRSACT */
#define _LESENSE_ST_TCONFA_PRSACT_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_ST_TCONFA */
#define _LESENSE_ST_TCONFA_PRSACT_NONE 0x00000000UL /**< Mode NONE for LESENSE_ST_TCONFA */
-#define _LESENSE_ST_TCONFA_PRSACT_UP 0x00000001UL /**< Mode UP for LESENSE_ST_TCONFA */
#define _LESENSE_ST_TCONFA_PRSACT_PRS0 0x00000001UL /**< Mode PRS0 for LESENSE_ST_TCONFA */
-#define _LESENSE_ST_TCONFA_PRSACT_PRS1 0x00000002UL /**< Mode PRS1 for LESENSE_ST_TCONFA */
+#define _LESENSE_ST_TCONFA_PRSACT_UP 0x00000001UL /**< Mode UP for LESENSE_ST_TCONFA */
#define _LESENSE_ST_TCONFA_PRSACT_DOWN 0x00000002UL /**< Mode DOWN for LESENSE_ST_TCONFA */
+#define _LESENSE_ST_TCONFA_PRSACT_PRS1 0x00000002UL /**< Mode PRS1 for LESENSE_ST_TCONFA */
#define _LESENSE_ST_TCONFA_PRSACT_PRS01 0x00000003UL /**< Mode PRS01 for LESENSE_ST_TCONFA */
#define _LESENSE_ST_TCONFA_PRSACT_PRS2 0x00000004UL /**< Mode PRS2 for LESENSE_ST_TCONFA */
-#define _LESENSE_ST_TCONFA_PRSACT_PRS02 0x00000005UL /**< Mode PRS02 for LESENSE_ST_TCONFA */
#define _LESENSE_ST_TCONFA_PRSACT_UPANDPRS2 0x00000005UL /**< Mode UPANDPRS2 for LESENSE_ST_TCONFA */
+#define _LESENSE_ST_TCONFA_PRSACT_PRS02 0x00000005UL /**< Mode PRS02 for LESENSE_ST_TCONFA */
#define _LESENSE_ST_TCONFA_PRSACT_PRS12 0x00000006UL /**< Mode PRS12 for LESENSE_ST_TCONFA */
#define _LESENSE_ST_TCONFA_PRSACT_DOWNANDPRS2 0x00000006UL /**< Mode DOWNANDPRS2 for LESENSE_ST_TCONFA */
#define _LESENSE_ST_TCONFA_PRSACT_PRS012 0x00000007UL /**< Mode PRS012 for LESENSE_ST_TCONFA */
#define LESENSE_ST_TCONFA_PRSACT_DEFAULT (_LESENSE_ST_TCONFA_PRSACT_DEFAULT << 12) /**< Shifted mode DEFAULT for LESENSE_ST_TCONFA */
#define LESENSE_ST_TCONFA_PRSACT_NONE (_LESENSE_ST_TCONFA_PRSACT_NONE << 12) /**< Shifted mode NONE for LESENSE_ST_TCONFA */
-#define LESENSE_ST_TCONFA_PRSACT_UP (_LESENSE_ST_TCONFA_PRSACT_UP << 12) /**< Shifted mode UP for LESENSE_ST_TCONFA */
#define LESENSE_ST_TCONFA_PRSACT_PRS0 (_LESENSE_ST_TCONFA_PRSACT_PRS0 << 12) /**< Shifted mode PRS0 for LESENSE_ST_TCONFA */
-#define LESENSE_ST_TCONFA_PRSACT_PRS1 (_LESENSE_ST_TCONFA_PRSACT_PRS1 << 12) /**< Shifted mode PRS1 for LESENSE_ST_TCONFA */
+#define LESENSE_ST_TCONFA_PRSACT_UP (_LESENSE_ST_TCONFA_PRSACT_UP << 12) /**< Shifted mode UP for LESENSE_ST_TCONFA */
#define LESENSE_ST_TCONFA_PRSACT_DOWN (_LESENSE_ST_TCONFA_PRSACT_DOWN << 12) /**< Shifted mode DOWN for LESENSE_ST_TCONFA */
+#define LESENSE_ST_TCONFA_PRSACT_PRS1 (_LESENSE_ST_TCONFA_PRSACT_PRS1 << 12) /**< Shifted mode PRS1 for LESENSE_ST_TCONFA */
#define LESENSE_ST_TCONFA_PRSACT_PRS01 (_LESENSE_ST_TCONFA_PRSACT_PRS01 << 12) /**< Shifted mode PRS01 for LESENSE_ST_TCONFA */
#define LESENSE_ST_TCONFA_PRSACT_PRS2 (_LESENSE_ST_TCONFA_PRSACT_PRS2 << 12) /**< Shifted mode PRS2 for LESENSE_ST_TCONFA */
-#define LESENSE_ST_TCONFA_PRSACT_PRS02 (_LESENSE_ST_TCONFA_PRSACT_PRS02 << 12) /**< Shifted mode PRS02 for LESENSE_ST_TCONFA */
#define LESENSE_ST_TCONFA_PRSACT_UPANDPRS2 (_LESENSE_ST_TCONFA_PRSACT_UPANDPRS2 << 12) /**< Shifted mode UPANDPRS2 for LESENSE_ST_TCONFA */
+#define LESENSE_ST_TCONFA_PRSACT_PRS02 (_LESENSE_ST_TCONFA_PRSACT_PRS02 << 12) /**< Shifted mode PRS02 for LESENSE_ST_TCONFA */
#define LESENSE_ST_TCONFA_PRSACT_PRS12 (_LESENSE_ST_TCONFA_PRSACT_PRS12 << 12) /**< Shifted mode PRS12 for LESENSE_ST_TCONFA */
#define LESENSE_ST_TCONFA_PRSACT_DOWNANDPRS2 (_LESENSE_ST_TCONFA_PRSACT_DOWNANDPRS2 << 12) /**< Shifted mode DOWNANDPRS2 for LESENSE_ST_TCONFA */
#define LESENSE_ST_TCONFA_PRSACT_PRS012 (_LESENSE_ST_TCONFA_PRSACT_PRS012 << 12) /**< Shifted mode PRS012 for LESENSE_ST_TCONFA */
@@ -1785,27 +1784,27 @@ typedef struct {
#define _LESENSE_ST_TCONFB_PRSACT_MASK 0x7000UL /**< Bit mask for LESENSE_PRSACT */
#define _LESENSE_ST_TCONFB_PRSACT_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_ST_TCONFB */
#define _LESENSE_ST_TCONFB_PRSACT_NONE 0x00000000UL /**< Mode NONE for LESENSE_ST_TCONFB */
-#define _LESENSE_ST_TCONFB_PRSACT_UP 0x00000001UL /**< Mode UP for LESENSE_ST_TCONFB */
#define _LESENSE_ST_TCONFB_PRSACT_PRS0 0x00000001UL /**< Mode PRS0 for LESENSE_ST_TCONFB */
-#define _LESENSE_ST_TCONFB_PRSACT_PRS1 0x00000002UL /**< Mode PRS1 for LESENSE_ST_TCONFB */
+#define _LESENSE_ST_TCONFB_PRSACT_UP 0x00000001UL /**< Mode UP for LESENSE_ST_TCONFB */
#define _LESENSE_ST_TCONFB_PRSACT_DOWN 0x00000002UL /**< Mode DOWN for LESENSE_ST_TCONFB */
+#define _LESENSE_ST_TCONFB_PRSACT_PRS1 0x00000002UL /**< Mode PRS1 for LESENSE_ST_TCONFB */
#define _LESENSE_ST_TCONFB_PRSACT_PRS01 0x00000003UL /**< Mode PRS01 for LESENSE_ST_TCONFB */
#define _LESENSE_ST_TCONFB_PRSACT_PRS2 0x00000004UL /**< Mode PRS2 for LESENSE_ST_TCONFB */
-#define _LESENSE_ST_TCONFB_PRSACT_PRS02 0x00000005UL /**< Mode PRS02 for LESENSE_ST_TCONFB */
#define _LESENSE_ST_TCONFB_PRSACT_UPANDPRS2 0x00000005UL /**< Mode UPANDPRS2 for LESENSE_ST_TCONFB */
+#define _LESENSE_ST_TCONFB_PRSACT_PRS02 0x00000005UL /**< Mode PRS02 for LESENSE_ST_TCONFB */
#define _LESENSE_ST_TCONFB_PRSACT_PRS12 0x00000006UL /**< Mode PRS12 for LESENSE_ST_TCONFB */
#define _LESENSE_ST_TCONFB_PRSACT_DOWNANDPRS2 0x00000006UL /**< Mode DOWNANDPRS2 for LESENSE_ST_TCONFB */
#define _LESENSE_ST_TCONFB_PRSACT_PRS012 0x00000007UL /**< Mode PRS012 for LESENSE_ST_TCONFB */
#define LESENSE_ST_TCONFB_PRSACT_DEFAULT (_LESENSE_ST_TCONFB_PRSACT_DEFAULT << 12) /**< Shifted mode DEFAULT for LESENSE_ST_TCONFB */
#define LESENSE_ST_TCONFB_PRSACT_NONE (_LESENSE_ST_TCONFB_PRSACT_NONE << 12) /**< Shifted mode NONE for LESENSE_ST_TCONFB */
-#define LESENSE_ST_TCONFB_PRSACT_UP (_LESENSE_ST_TCONFB_PRSACT_UP << 12) /**< Shifted mode UP for LESENSE_ST_TCONFB */
#define LESENSE_ST_TCONFB_PRSACT_PRS0 (_LESENSE_ST_TCONFB_PRSACT_PRS0 << 12) /**< Shifted mode PRS0 for LESENSE_ST_TCONFB */
-#define LESENSE_ST_TCONFB_PRSACT_PRS1 (_LESENSE_ST_TCONFB_PRSACT_PRS1 << 12) /**< Shifted mode PRS1 for LESENSE_ST_TCONFB */
+#define LESENSE_ST_TCONFB_PRSACT_UP (_LESENSE_ST_TCONFB_PRSACT_UP << 12) /**< Shifted mode UP for LESENSE_ST_TCONFB */
#define LESENSE_ST_TCONFB_PRSACT_DOWN (_LESENSE_ST_TCONFB_PRSACT_DOWN << 12) /**< Shifted mode DOWN for LESENSE_ST_TCONFB */
+#define LESENSE_ST_TCONFB_PRSACT_PRS1 (_LESENSE_ST_TCONFB_PRSACT_PRS1 << 12) /**< Shifted mode PRS1 for LESENSE_ST_TCONFB */
#define LESENSE_ST_TCONFB_PRSACT_PRS01 (_LESENSE_ST_TCONFB_PRSACT_PRS01 << 12) /**< Shifted mode PRS01 for LESENSE_ST_TCONFB */
#define LESENSE_ST_TCONFB_PRSACT_PRS2 (_LESENSE_ST_TCONFB_PRSACT_PRS2 << 12) /**< Shifted mode PRS2 for LESENSE_ST_TCONFB */
-#define LESENSE_ST_TCONFB_PRSACT_PRS02 (_LESENSE_ST_TCONFB_PRSACT_PRS02 << 12) /**< Shifted mode PRS02 for LESENSE_ST_TCONFB */
#define LESENSE_ST_TCONFB_PRSACT_UPANDPRS2 (_LESENSE_ST_TCONFB_PRSACT_UPANDPRS2 << 12) /**< Shifted mode UPANDPRS2 for LESENSE_ST_TCONFB */
+#define LESENSE_ST_TCONFB_PRSACT_PRS02 (_LESENSE_ST_TCONFB_PRSACT_PRS02 << 12) /**< Shifted mode PRS02 for LESENSE_ST_TCONFB */
#define LESENSE_ST_TCONFB_PRSACT_PRS12 (_LESENSE_ST_TCONFB_PRSACT_PRS12 << 12) /**< Shifted mode PRS12 for LESENSE_ST_TCONFB */
#define LESENSE_ST_TCONFB_PRSACT_DOWNANDPRS2 (_LESENSE_ST_TCONFB_PRSACT_DOWNANDPRS2 << 12) /**< Shifted mode DOWNANDPRS2 for LESENSE_ST_TCONFB */
#define LESENSE_ST_TCONFB_PRSACT_PRS012 (_LESENSE_ST_TCONFB_PRSACT_PRS012 << 12) /**< Shifted mode PRS012 for LESENSE_ST_TCONFB */
diff --git a/cpu/efm32/families/efm32lg/include/vendor/efm32lg_lesense_buf.h b/cpu/efm32/families/efm32lg/include/vendor/efm32lg_lesense_buf.h
index c0ce33fe11..697452acb8 100644
--- a/cpu/efm32/families/efm32lg/include/vendor/efm32lg_lesense_buf.h
+++ b/cpu/efm32/families/efm32lg/include/vendor/efm32lg_lesense_buf.h
@@ -1,10 +1,9 @@
/***************************************************************************//**
* @file
* @brief EFM32LG_LESENSE_BUF register and bit field definitions
- * @version 5.8.3
*******************************************************************************
* # License
- * Copyright 2019 Silicon Laboratories Inc. www.silabs.com
+ * Copyright 2020 Silicon Laboratories Inc. www.silabs.com
*******************************************************************************
*
* SPDX-License-Identifier: Zlib
diff --git a/cpu/efm32/families/efm32lg/include/vendor/efm32lg_lesense_ch.h b/cpu/efm32/families/efm32lg/include/vendor/efm32lg_lesense_ch.h
index 5d4bde3e22..24c5abed6c 100644
--- a/cpu/efm32/families/efm32lg/include/vendor/efm32lg_lesense_ch.h
+++ b/cpu/efm32/families/efm32lg/include/vendor/efm32lg_lesense_ch.h
@@ -1,10 +1,9 @@
/***************************************************************************//**
* @file
* @brief EFM32LG_LESENSE_CH register and bit field definitions
- * @version 5.8.3
*******************************************************************************
* # License
- * Copyright 2019 Silicon Laboratories Inc. www.silabs.com
+ * Copyright 2020 Silicon Laboratories Inc. www.silabs.com
*******************************************************************************
*
* SPDX-License-Identifier: Zlib
diff --git a/cpu/efm32/families/efm32lg/include/vendor/efm32lg_lesense_st.h b/cpu/efm32/families/efm32lg/include/vendor/efm32lg_lesense_st.h
index 40a8874152..e3b768d7a0 100644
--- a/cpu/efm32/families/efm32lg/include/vendor/efm32lg_lesense_st.h
+++ b/cpu/efm32/families/efm32lg/include/vendor/efm32lg_lesense_st.h
@@ -1,10 +1,9 @@
/***************************************************************************//**
* @file
* @brief EFM32LG_LESENSE_ST register and bit field definitions
- * @version 5.8.3
*******************************************************************************
* # License
- * Copyright 2019 Silicon Laboratories Inc. www.silabs.com
+ * Copyright 2020 Silicon Laboratories Inc. www.silabs.com
*******************************************************************************
*
* SPDX-License-Identifier: Zlib
diff --git a/cpu/efm32/families/efm32lg/include/vendor/efm32lg_letimer.h b/cpu/efm32/families/efm32lg/include/vendor/efm32lg_letimer.h
index a63d2eb2c3..25da657857 100644
--- a/cpu/efm32/families/efm32lg/include/vendor/efm32lg_letimer.h
+++ b/cpu/efm32/families/efm32lg/include/vendor/efm32lg_letimer.h
@@ -1,10 +1,9 @@
/***************************************************************************//**
* @file
* @brief EFM32LG_LETIMER register and bit field definitions
- * @version 5.8.3
*******************************************************************************
* # License
- * Copyright 2019 Silicon Laboratories Inc. www.silabs.com
+ * Copyright 2020 Silicon Laboratories Inc. www.silabs.com
*******************************************************************************
*
* SPDX-License-Identifier: Zlib
diff --git a/cpu/efm32/families/efm32lg/include/vendor/efm32lg_leuart.h b/cpu/efm32/families/efm32lg/include/vendor/efm32lg_leuart.h
index 5e95d94dc8..f02399bdad 100644
--- a/cpu/efm32/families/efm32lg/include/vendor/efm32lg_leuart.h
+++ b/cpu/efm32/families/efm32lg/include/vendor/efm32lg_leuart.h
@@ -1,10 +1,9 @@
/***************************************************************************//**
* @file
* @brief EFM32LG_LEUART register and bit field definitions
- * @version 5.8.3
*******************************************************************************
* # License
- * Copyright 2019 Silicon Laboratories Inc. www.silabs.com
+ * Copyright 2020 Silicon Laboratories Inc. www.silabs.com
*******************************************************************************
*
* SPDX-License-Identifier: Zlib
diff --git a/cpu/efm32/families/efm32lg/include/vendor/efm32lg_msc.h b/cpu/efm32/families/efm32lg/include/vendor/efm32lg_msc.h
index 19eb585a3f..446f180236 100644
--- a/cpu/efm32/families/efm32lg/include/vendor/efm32lg_msc.h
+++ b/cpu/efm32/families/efm32lg/include/vendor/efm32lg_msc.h
@@ -1,10 +1,9 @@
/***************************************************************************//**
* @file
* @brief EFM32LG_MSC register and bit field definitions
- * @version 5.8.3
*******************************************************************************
* # License
- * Copyright 2019 Silicon Laboratories Inc. www.silabs.com
+ * Copyright 2020 Silicon Laboratories Inc. www.silabs.com
*******************************************************************************
*
* SPDX-License-Identifier: Zlib
@@ -364,13 +363,13 @@ typedef struct {
#define _MSC_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for MSC_LOCKKEY */
#define _MSC_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for MSC_LOCKKEY */
#define _MSC_LOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_LOCK */
-#define _MSC_LOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for MSC_LOCK */
#define _MSC_LOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for MSC_LOCK */
+#define _MSC_LOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for MSC_LOCK */
#define _MSC_LOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for MSC_LOCK */
#define _MSC_LOCK_LOCKKEY_UNLOCK 0x00001B71UL /**< Mode UNLOCK for MSC_LOCK */
#define MSC_LOCK_LOCKKEY_DEFAULT (_MSC_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_LOCK */
-#define MSC_LOCK_LOCKKEY_LOCK (_MSC_LOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for MSC_LOCK */
#define MSC_LOCK_LOCKKEY_UNLOCKED (_MSC_LOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for MSC_LOCK */
+#define MSC_LOCK_LOCKKEY_LOCK (_MSC_LOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for MSC_LOCK */
#define MSC_LOCK_LOCKKEY_LOCKED (_MSC_LOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for MSC_LOCK */
#define MSC_LOCK_LOCKKEY_UNLOCK (_MSC_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for MSC_LOCK */
@@ -431,13 +430,13 @@ typedef struct {
#define _MSC_MASSLOCK_MASK 0x0000FFFFUL /**< Mask for MSC_MASSLOCK */
#define _MSC_MASSLOCK_LOCKKEY_SHIFT 0 /**< Shift value for MSC_LOCKKEY */
#define _MSC_MASSLOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for MSC_LOCKKEY */
-#define _MSC_MASSLOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for MSC_MASSLOCK */
#define _MSC_MASSLOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for MSC_MASSLOCK */
+#define _MSC_MASSLOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for MSC_MASSLOCK */
#define _MSC_MASSLOCK_LOCKKEY_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_MASSLOCK */
#define _MSC_MASSLOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for MSC_MASSLOCK */
#define _MSC_MASSLOCK_LOCKKEY_UNLOCK 0x0000631AUL /**< Mode UNLOCK for MSC_MASSLOCK */
-#define MSC_MASSLOCK_LOCKKEY_LOCK (_MSC_MASSLOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for MSC_MASSLOCK */
#define MSC_MASSLOCK_LOCKKEY_UNLOCKED (_MSC_MASSLOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for MSC_MASSLOCK */
+#define MSC_MASSLOCK_LOCKKEY_LOCK (_MSC_MASSLOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for MSC_MASSLOCK */
#define MSC_MASSLOCK_LOCKKEY_DEFAULT (_MSC_MASSLOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_MASSLOCK */
#define MSC_MASSLOCK_LOCKKEY_LOCKED (_MSC_MASSLOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for MSC_MASSLOCK */
#define MSC_MASSLOCK_LOCKKEY_UNLOCK (_MSC_MASSLOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for MSC_MASSLOCK */
diff --git a/cpu/efm32/families/efm32lg/include/vendor/efm32lg_pcnt.h b/cpu/efm32/families/efm32lg/include/vendor/efm32lg_pcnt.h
index b408dd60ab..5943aef466 100644
--- a/cpu/efm32/families/efm32lg/include/vendor/efm32lg_pcnt.h
+++ b/cpu/efm32/families/efm32lg/include/vendor/efm32lg_pcnt.h
@@ -1,10 +1,9 @@
/***************************************************************************//**
* @file
* @brief EFM32LG_PCNT register and bit field definitions
- * @version 5.8.3
*******************************************************************************
* # License
- * Copyright 2019 Silicon Laboratories Inc. www.silabs.com
+ * Copyright 2020 Silicon Laboratories Inc. www.silabs.com
*******************************************************************************
*
* SPDX-License-Identifier: Zlib
diff --git a/cpu/efm32/families/efm32lg/include/vendor/efm32lg_prs.h b/cpu/efm32/families/efm32lg/include/vendor/efm32lg_prs.h
index d92852ef1f..f73bc83e37 100644
--- a/cpu/efm32/families/efm32lg/include/vendor/efm32lg_prs.h
+++ b/cpu/efm32/families/efm32lg/include/vendor/efm32lg_prs.h
@@ -1,10 +1,9 @@
/***************************************************************************//**
* @file
* @brief EFM32LG_PRS register and bit field definitions
- * @version 5.8.3
*******************************************************************************
* # License
- * Copyright 2019 Silicon Laboratories Inc. www.silabs.com
+ * Copyright 2020 Silicon Laboratories Inc. www.silabs.com
*******************************************************************************
*
* SPDX-License-Identifier: Zlib
diff --git a/cpu/efm32/families/efm32lg/include/vendor/efm32lg_prs_ch.h b/cpu/efm32/families/efm32lg/include/vendor/efm32lg_prs_ch.h
index 2a8dda5d6e..60df796c3c 100644
--- a/cpu/efm32/families/efm32lg/include/vendor/efm32lg_prs_ch.h
+++ b/cpu/efm32/families/efm32lg/include/vendor/efm32lg_prs_ch.h
@@ -1,10 +1,9 @@
/***************************************************************************//**
* @file
* @brief EFM32LG_PRS_CH register and bit field definitions
- * @version 5.8.3
*******************************************************************************
* # License
- * Copyright 2019 Silicon Laboratories Inc. www.silabs.com
+ * Copyright 2020 Silicon Laboratories Inc. www.silabs.com
*******************************************************************************
*
* SPDX-License-Identifier: Zlib
diff --git a/cpu/efm32/families/efm32lg/include/vendor/efm32lg_prs_signals.h b/cpu/efm32/families/efm32lg/include/vendor/efm32lg_prs_signals.h
index 561abc8786..f7fb34bea7 100644
--- a/cpu/efm32/families/efm32lg/include/vendor/efm32lg_prs_signals.h
+++ b/cpu/efm32/families/efm32lg/include/vendor/efm32lg_prs_signals.h
@@ -1,10 +1,9 @@
/***************************************************************************//**
* @file
* @brief EFM32LG_PRS_SIGNALS register and bit field definitions
- * @version 5.8.3
*******************************************************************************
* # License
- * Copyright 2019 Silicon Laboratories Inc. www.silabs.com
+ * Copyright 2020 Silicon Laboratories Inc. www.silabs.com
*******************************************************************************
*
* SPDX-License-Identifier: Zlib
diff --git a/cpu/efm32/families/efm32lg/include/vendor/efm32lg_rmu.h b/cpu/efm32/families/efm32lg/include/vendor/efm32lg_rmu.h
index 7343af1551..bec50f458e 100644
--- a/cpu/efm32/families/efm32lg/include/vendor/efm32lg_rmu.h
+++ b/cpu/efm32/families/efm32lg/include/vendor/efm32lg_rmu.h
@@ -1,10 +1,9 @@
/***************************************************************************//**
* @file
* @brief EFM32LG_RMU register and bit field definitions
- * @version 5.8.3
*******************************************************************************
* # License
- * Copyright 2019 Silicon Laboratories Inc. www.silabs.com
+ * Copyright 2020 Silicon Laboratories Inc. www.silabs.com
*******************************************************************************
*
* SPDX-License-Identifier: Zlib
diff --git a/cpu/efm32/families/efm32lg/include/vendor/efm32lg_romtable.h b/cpu/efm32/families/efm32lg/include/vendor/efm32lg_romtable.h
index ca6cdce68d..80b8f29ef8 100644
--- a/cpu/efm32/families/efm32lg/include/vendor/efm32lg_romtable.h
+++ b/cpu/efm32/families/efm32lg/include/vendor/efm32lg_romtable.h
@@ -1,10 +1,9 @@
/***************************************************************************//**
* @file
* @brief EFM32LG_ROMTABLE register and bit field definitions
- * @version 5.8.3
*******************************************************************************
* # License
- * Copyright 2019 Silicon Laboratories Inc. www.silabs.com
+ * Copyright 2020 Silicon Laboratories Inc. www.silabs.com
*******************************************************************************
*
* SPDX-License-Identifier: Zlib
diff --git a/cpu/efm32/families/efm32lg/include/vendor/efm32lg_rtc.h b/cpu/efm32/families/efm32lg/include/vendor/efm32lg_rtc.h
index e03049ef34..6fb1b73d29 100644
--- a/cpu/efm32/families/efm32lg/include/vendor/efm32lg_rtc.h
+++ b/cpu/efm32/families/efm32lg/include/vendor/efm32lg_rtc.h
@@ -1,10 +1,9 @@
/***************************************************************************//**
* @file
* @brief EFM32LG_RTC register and bit field definitions
- * @version 5.8.3
*******************************************************************************
* # License
- * Copyright 2019 Silicon Laboratories Inc. www.silabs.com
+ * Copyright 2020 Silicon Laboratories Inc. www.silabs.com
*******************************************************************************
*
* SPDX-License-Identifier: Zlib
diff --git a/cpu/efm32/families/efm32lg/include/vendor/efm32lg_timer.h b/cpu/efm32/families/efm32lg/include/vendor/efm32lg_timer.h
index 7c6494141e..c710d32057 100644
--- a/cpu/efm32/families/efm32lg/include/vendor/efm32lg_timer.h
+++ b/cpu/efm32/families/efm32lg/include/vendor/efm32lg_timer.h
@@ -1,10 +1,9 @@
/***************************************************************************//**
* @file
* @brief EFM32LG_TIMER register and bit field definitions
- * @version 5.8.3
*******************************************************************************
* # License
- * Copyright 2019 Silicon Laboratories Inc. www.silabs.com
+ * Copyright 2020 Silicon Laboratories Inc. www.silabs.com
*******************************************************************************
*
* SPDX-License-Identifier: Zlib
@@ -963,13 +962,13 @@ typedef struct {
#define _TIMER_DTLOCK_LOCKKEY_SHIFT 0 /**< Shift value for TIMER_LOCKKEY */
#define _TIMER_DTLOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for TIMER_LOCKKEY */
#define _TIMER_DTLOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTLOCK */
-#define _TIMER_DTLOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for TIMER_DTLOCK */
#define _TIMER_DTLOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for TIMER_DTLOCK */
+#define _TIMER_DTLOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for TIMER_DTLOCK */
#define _TIMER_DTLOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for TIMER_DTLOCK */
#define _TIMER_DTLOCK_LOCKKEY_UNLOCK 0x0000CE80UL /**< Mode UNLOCK for TIMER_DTLOCK */
#define TIMER_DTLOCK_LOCKKEY_DEFAULT (_TIMER_DTLOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_DTLOCK */
-#define TIMER_DTLOCK_LOCKKEY_LOCK (_TIMER_DTLOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for TIMER_DTLOCK */
#define TIMER_DTLOCK_LOCKKEY_UNLOCKED (_TIMER_DTLOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for TIMER_DTLOCK */
+#define TIMER_DTLOCK_LOCKKEY_LOCK (_TIMER_DTLOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for TIMER_DTLOCK */
#define TIMER_DTLOCK_LOCKKEY_LOCKED (_TIMER_DTLOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for TIMER_DTLOCK */
#define TIMER_DTLOCK_LOCKKEY_UNLOCK (_TIMER_DTLOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for TIMER_DTLOCK */
diff --git a/cpu/efm32/families/efm32lg/include/vendor/efm32lg_timer_cc.h b/cpu/efm32/families/efm32lg/include/vendor/efm32lg_timer_cc.h
index bfde025d71..994606a461 100644
--- a/cpu/efm32/families/efm32lg/include/vendor/efm32lg_timer_cc.h
+++ b/cpu/efm32/families/efm32lg/include/vendor/efm32lg_timer_cc.h
@@ -1,10 +1,9 @@
/***************************************************************************//**
* @file
* @brief EFM32LG_TIMER_CC register and bit field definitions
- * @version 5.8.3
*******************************************************************************
* # License
- * Copyright 2019 Silicon Laboratories Inc. www.silabs.com
+ * Copyright 2020 Silicon Laboratories Inc. www.silabs.com
*******************************************************************************
*
* SPDX-License-Identifier: Zlib
diff --git a/cpu/efm32/families/efm32lg/include/vendor/efm32lg_uart.h b/cpu/efm32/families/efm32lg/include/vendor/efm32lg_uart.h
index ab3338b3bd..fe6eddf93b 100644
--- a/cpu/efm32/families/efm32lg/include/vendor/efm32lg_uart.h
+++ b/cpu/efm32/families/efm32lg/include/vendor/efm32lg_uart.h
@@ -1,10 +1,9 @@
/***************************************************************************//**
* @file
* @brief EFM32LG_UART register and bit field definitions
- * @version 5.8.3
*******************************************************************************
* # License
- * Copyright 2019 Silicon Laboratories Inc. www.silabs.com
+ * Copyright 2020 Silicon Laboratories Inc. www.silabs.com
*******************************************************************************
*
* SPDX-License-Identifier: Zlib
diff --git a/cpu/efm32/families/efm32lg/include/vendor/efm32lg_usart.h b/cpu/efm32/families/efm32lg/include/vendor/efm32lg_usart.h
index e5ac6bde48..3cb24a4525 100644
--- a/cpu/efm32/families/efm32lg/include/vendor/efm32lg_usart.h
+++ b/cpu/efm32/families/efm32lg/include/vendor/efm32lg_usart.h
@@ -1,10 +1,9 @@
/***************************************************************************//**
* @file
* @brief EFM32LG_USART register and bit field definitions
- * @version 5.8.3
*******************************************************************************
* # License
- * Copyright 2019 Silicon Laboratories Inc. www.silabs.com
+ * Copyright 2020 Silicon Laboratories Inc. www.silabs.com
*******************************************************************************
*
* SPDX-License-Identifier: Zlib
diff --git a/cpu/efm32/families/efm32lg/include/vendor/efm32lg_usb.h b/cpu/efm32/families/efm32lg/include/vendor/efm32lg_usb.h
index f1a6fb9cc1..dfb8800e89 100644
--- a/cpu/efm32/families/efm32lg/include/vendor/efm32lg_usb.h
+++ b/cpu/efm32/families/efm32lg/include/vendor/efm32lg_usb.h
@@ -1,10 +1,9 @@
/***************************************************************************//**
* @file
* @brief EFM32LG_USB register and bit field definitions
- * @version 5.8.3
*******************************************************************************
* # License
- * Copyright 2019 Silicon Laboratories Inc. www.silabs.com
+ * Copyright 2020 Silicon Laboratories Inc. www.silabs.com
*******************************************************************************
*
* SPDX-License-Identifier: Zlib
diff --git a/cpu/efm32/families/efm32lg/include/vendor/efm32lg_usb_diep.h b/cpu/efm32/families/efm32lg/include/vendor/efm32lg_usb_diep.h
index cb757a4886..72c8766d9c 100644
--- a/cpu/efm32/families/efm32lg/include/vendor/efm32lg_usb_diep.h
+++ b/cpu/efm32/families/efm32lg/include/vendor/efm32lg_usb_diep.h
@@ -1,10 +1,9 @@
/***************************************************************************//**
* @file
* @brief EFM32LG_USB_DIEP register and bit field definitions
- * @version 5.8.3
*******************************************************************************
* # License
- * Copyright 2019 Silicon Laboratories Inc. www.silabs.com
+ * Copyright 2020 Silicon Laboratories Inc. www.silabs.com
*******************************************************************************
*
* SPDX-License-Identifier: Zlib
diff --git a/cpu/efm32/families/efm32lg/include/vendor/efm32lg_usb_doep.h b/cpu/efm32/families/efm32lg/include/vendor/efm32lg_usb_doep.h
index 3509f3fd63..c31385c281 100644
--- a/cpu/efm32/families/efm32lg/include/vendor/efm32lg_usb_doep.h
+++ b/cpu/efm32/families/efm32lg/include/vendor/efm32lg_usb_doep.h
@@ -1,10 +1,9 @@
/***************************************************************************//**
* @file
* @brief EFM32LG_USB_DOEP register and bit field definitions
- * @version 5.8.3
*******************************************************************************
* # License
- * Copyright 2019 Silicon Laboratories Inc. www.silabs.com
+ * Copyright 2020 Silicon Laboratories Inc. www.silabs.com
*******************************************************************************
*
* SPDX-License-Identifier: Zlib
diff --git a/cpu/efm32/families/efm32lg/include/vendor/efm32lg_usb_hc.h b/cpu/efm32/families/efm32lg/include/vendor/efm32lg_usb_hc.h
index 10187be768..6795f3beae 100644
--- a/cpu/efm32/families/efm32lg/include/vendor/efm32lg_usb_hc.h
+++ b/cpu/efm32/families/efm32lg/include/vendor/efm32lg_usb_hc.h
@@ -1,10 +1,9 @@
/***************************************************************************//**
* @file
* @brief EFM32LG_USB_HC register and bit field definitions
- * @version 5.8.3
*******************************************************************************
* # License
- * Copyright 2019 Silicon Laboratories Inc. www.silabs.com
+ * Copyright 2020 Silicon Laboratories Inc. www.silabs.com
*******************************************************************************
*
* SPDX-License-Identifier: Zlib
diff --git a/cpu/efm32/families/efm32lg/include/vendor/efm32lg_vcmp.h b/cpu/efm32/families/efm32lg/include/vendor/efm32lg_vcmp.h
index 39d851d054..ef8c46cd4a 100644
--- a/cpu/efm32/families/efm32lg/include/vendor/efm32lg_vcmp.h
+++ b/cpu/efm32/families/efm32lg/include/vendor/efm32lg_vcmp.h
@@ -1,10 +1,9 @@
/***************************************************************************//**
* @file
* @brief EFM32LG_VCMP register and bit field definitions
- * @version 5.8.3
*******************************************************************************
* # License
- * Copyright 2019 Silicon Laboratories Inc. www.silabs.com
+ * Copyright 2020 Silicon Laboratories Inc. www.silabs.com
*******************************************************************************
*
* SPDX-License-Identifier: Zlib
diff --git a/cpu/efm32/families/efm32lg/include/vendor/efm32lg_wdog.h b/cpu/efm32/families/efm32lg/include/vendor/efm32lg_wdog.h
index eeec5ebd78..f56f166820 100644
--- a/cpu/efm32/families/efm32lg/include/vendor/efm32lg_wdog.h
+++ b/cpu/efm32/families/efm32lg/include/vendor/efm32lg_wdog.h
@@ -1,10 +1,9 @@
/***************************************************************************//**
* @file
* @brief EFM32LG_WDOG register and bit field definitions
- * @version 5.8.3
*******************************************************************************
* # License
- * Copyright 2019 Silicon Laboratories Inc. www.silabs.com
+ * Copyright 2020 Silicon Laboratories Inc. www.silabs.com
*******************************************************************************
*
* SPDX-License-Identifier: Zlib
diff --git a/cpu/efm32/families/efm32lg/include/vendor/em_device.h b/cpu/efm32/families/efm32lg/include/vendor/em_device.h
index dcc70312e4..b7e705c1c9 100644
--- a/cpu/efm32/families/efm32lg/include/vendor/em_device.h
+++ b/cpu/efm32/families/efm32lg/include/vendor/em_device.h
@@ -11,10 +11,9 @@
* Add "#include "em_device.h" to your source files
* @endverbatim
*
- * @version 5.8.3
*******************************************************************************
* # License
- * Copyright 2019 Silicon Laboratories Inc. www.silabs.com
+ * Copyright 2020 Silicon Laboratories Inc. www.silabs.com
*******************************************************************************
*
* SPDX-License-Identifier: Zlib
diff --git a/cpu/efm32/families/efm32lg/include/vendor/system_efm32lg.h b/cpu/efm32/families/efm32lg/include/vendor/system_efm32lg.h
index af0082a603..90b1daed73 100644
--- a/cpu/efm32/families/efm32lg/include/vendor/system_efm32lg.h
+++ b/cpu/efm32/families/efm32lg/include/vendor/system_efm32lg.h
@@ -1,10 +1,9 @@
/***************************************************************************//**
* @file
* @brief CMSIS Cortex-M3 System Layer for EFM32LG devices.
- * @version 5.8.3
*******************************************************************************
* # License
- * Copyright 2019 Silicon Laboratories Inc. www.silabs.com
+ * Copyright 2020 Silicon Laboratories Inc. www.silabs.com
*******************************************************************************
*
* SPDX-License-Identifier: Zlib
@@ -47,12 +46,29 @@ extern "C" {
* @{
******************************************************************************/
+/*******************************************************************************
+ ****************************** TYPEDEFS ***********************************
+ ******************************************************************************/
+
+/* Interrupt vectortable entry */
+typedef union {
+ void (*pFunc)(void);
+ void *topOfStack;
+} tVectorEntry;
+
/*******************************************************************************
************************** GLOBAL VARIABLES *******************************
******************************************************************************/
extern uint32_t SystemCoreClock; /**< System Clock Frequency (Core Clock) */
+#if defined(__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+#if defined(__ICCARM__) /* IAR requires the __vector_table symbol */
+#define __Vectors __vector_table
+#endif
+extern const tVectorEntry __Vectors[];
+#endif
+
/*******************************************************************************
***************************** PROTOTYPES **********************************
******************************************************************************/
diff --git a/cpu/efm32/families/efm32lg/system.c b/cpu/efm32/families/efm32lg/system.c
index 0bb00132d1..ccc1ae327a 100644
--- a/cpu/efm32/families/efm32lg/system.c
+++ b/cpu/efm32/families/efm32lg/system.c
@@ -1,10 +1,9 @@
/***************************************************************************//**
* @file
* @brief CMSIS Cortex-M3 System Layer for EFM32LG devices.
- * @version 5.8.3
*******************************************************************************
* # License
- * Copyright 2019 Silicon Laboratories Inc. www.silabs.com
+ * Copyright 2020 Silicon Laboratories Inc. www.silabs.com
*******************************************************************************
*
* SPDX-License-Identifier: Zlib
@@ -106,13 +105,6 @@ uint32_t SystemCoreClock = 14000000UL;
************************** GLOBAL FUNCTIONS *******************************
******************************************************************************/
-#if defined(__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
-#if defined(__ICCARM__) /* IAR requires the __vector_table symbol */
-#define __Vectors __vector_table
-#endif
-extern uint32_t __Vectors;
-#endif
-
/***************************************************************************//**
* @brief
* Get the current core clock frequency.
diff --git a/cpu/efm32/families/efm32pg12b/include/vendor/efm32pg12b500f1024gl125.h b/cpu/efm32/families/efm32pg12b/include/vendor/efm32pg12b500f1024gl125.h
index bd69b24150..d8a6b4b89a 100644
--- a/cpu/efm32/families/efm32pg12b/include/vendor/efm32pg12b500f1024gl125.h
+++ b/cpu/efm32/families/efm32pg12b/include/vendor/efm32pg12b500f1024gl125.h
@@ -2,10 +2,9 @@
* @file
* @brief CMSIS Cortex-M Peripheral Access Layer Header File
* for EFM32PG12B500F1024GL125
- * @version 5.8.3
*******************************************************************************
* # License
- * Copyright 2019 Silicon Laboratories Inc. www.silabs.com
+ * Copyright 2020 Silicon Laboratories Inc. www.silabs.com
*******************************************************************************
*
* SPDX-License-Identifier: Zlib
@@ -153,58 +152,18 @@ typedef enum IRQn{
#define PART_NUMBER "EFM32PG12B500F1024GL125" /**< Part Number */
/** Memory Base addresses and limits */
-#define RAM0_CODE_MEM_BASE (0x10000000UL) /**< RAM0_CODE base address */
-#define RAM0_CODE_MEM_SIZE (0x20000UL) /**< RAM0_CODE available address space */
-#define RAM0_CODE_MEM_END (0x1001FFFFUL) /**< RAM0_CODE end address */
-#define RAM0_CODE_MEM_BITS (0x00000011UL) /**< RAM0_CODE used bits */
-#define RAM2_MEM_BASE (0x20040000UL) /**< RAM2 base address */
-#define RAM2_MEM_SIZE (0x800UL) /**< RAM2 available address space */
-#define RAM2_MEM_END (0x200407FFUL) /**< RAM2 end address */
-#define RAM2_MEM_BITS (0x0000000BUL) /**< RAM2 used bits */
-#define RAM1_MEM_BASE (0x20020000UL) /**< RAM1 base address */
-#define RAM1_MEM_SIZE (0x20000UL) /**< RAM1 available address space */
-#define RAM1_MEM_END (0x2003FFFFUL) /**< RAM1 end address */
-#define RAM1_MEM_BITS (0x00000011UL) /**< RAM1 used bits */
#define CRYPTO1_BITCLR_MEM_BASE (0x440F0400UL) /**< CRYPTO1_BITCLR base address */
#define CRYPTO1_BITCLR_MEM_SIZE (0x400UL) /**< CRYPTO1_BITCLR available address space */
#define CRYPTO1_BITCLR_MEM_END (0x440F07FFUL) /**< CRYPTO1_BITCLR end address */
#define CRYPTO1_BITCLR_MEM_BITS (0x0000000AUL) /**< CRYPTO1_BITCLR used bits */
-#define PER_MEM_BASE (0x40000000UL) /**< PER base address */
-#define PER_MEM_SIZE (0xF0000UL) /**< PER available address space */
-#define PER_MEM_END (0x400EFFFFUL) /**< PER end address */
-#define PER_MEM_BITS (0x00000014UL) /**< PER used bits */
-#define RAM1_CODE_MEM_BASE (0x10020000UL) /**< RAM1_CODE base address */
-#define RAM1_CODE_MEM_SIZE (0x20000UL) /**< RAM1_CODE available address space */
-#define RAM1_CODE_MEM_END (0x1003FFFFUL) /**< RAM1_CODE end address */
-#define RAM1_CODE_MEM_BITS (0x00000011UL) /**< RAM1_CODE used bits */
-#define CRYPTO1_MEM_BASE (0x400F0400UL) /**< CRYPTO1 base address */
-#define CRYPTO1_MEM_SIZE (0x400UL) /**< CRYPTO1 available address space */
-#define CRYPTO1_MEM_END (0x400F07FFUL) /**< CRYPTO1 end address */
-#define CRYPTO1_MEM_BITS (0x0000000AUL) /**< CRYPTO1 used bits */
-#define FLASH_MEM_BASE (0x00000000UL) /**< FLASH base address */
-#define FLASH_MEM_SIZE (0x10000000UL) /**< FLASH available address space */
-#define FLASH_MEM_END (0x0FFFFFFFUL) /**< FLASH end address */
-#define FLASH_MEM_BITS (0x0000001CUL) /**< FLASH used bits */
-#define CRYPTO0_MEM_BASE (0x400F0000UL) /**< CRYPTO0 base address */
-#define CRYPTO0_MEM_SIZE (0x400UL) /**< CRYPTO0 available address space */
-#define CRYPTO0_MEM_END (0x400F03FFUL) /**< CRYPTO0 end address */
-#define CRYPTO0_MEM_BITS (0x0000000AUL) /**< CRYPTO0 used bits */
-#define CRYPTO_MEM_BASE CRYPTO0_MEM_BASE /**< Alias for CRYPTO0_MEM_BASE */
-#define CRYPTO_MEM_SIZE CRYPTO0_MEM_SIZE /**< Alias for CRYPTO0_MEM_SIZE */
-#define CRYPTO_MEM_END CRYPTO0_MEM_END /**< Alias for CRYPTO0_MEM_END */
-#define CRYPTO_MEM_BITS CRYPTO0_MEM_BITS /**< Alias for CRYPTO0_MEM_BITS */
-#define PER_BITCLR_MEM_BASE (0x44000000UL) /**< PER_BITCLR base address */
-#define PER_BITCLR_MEM_SIZE (0xF0000UL) /**< PER_BITCLR available address space */
-#define PER_BITCLR_MEM_END (0x440EFFFFUL) /**< PER_BITCLR end address */
-#define PER_BITCLR_MEM_BITS (0x00000014UL) /**< PER_BITCLR used bits */
-#define CRYPTO0_BITSET_MEM_BASE (0x460F0000UL) /**< CRYPTO0_BITSET base address */
-#define CRYPTO0_BITSET_MEM_SIZE (0x400UL) /**< CRYPTO0_BITSET available address space */
-#define CRYPTO0_BITSET_MEM_END (0x460F03FFUL) /**< CRYPTO0_BITSET end address */
-#define CRYPTO0_BITSET_MEM_BITS (0x0000000AUL) /**< CRYPTO0_BITSET used bits */
-#define CRYPTO_BITSET_MEM_BASE CRYPTO0_BITSET_MEM_BASE /**< Alias for CRYPTO0_BITSET_MEM_BASE */
-#define CRYPTO_BITSET_MEM_SIZE CRYPTO0_BITSET_MEM_SIZE /**< Alias for CRYPTO0_BITSET_MEM_SIZE */
-#define CRYPTO_BITSET_MEM_END CRYPTO0_BITSET_MEM_END /**< Alias for CRYPTO0_BITSET_MEM_END */
-#define CRYPTO_BITSET_MEM_BITS CRYPTO0_BITSET_MEM_BITS /**< Alias for CRYPTO0_BITSET_MEM_BITS */
+#define RAM1_MEM_BASE (0x20020000UL) /**< RAM1 base address */
+#define RAM1_MEM_SIZE (0x20000UL) /**< RAM1 available address space */
+#define RAM1_MEM_END (0x2003FFFFUL) /**< RAM1 end address */
+#define RAM1_MEM_BITS (0x00000011UL) /**< RAM1 used bits */
+#define RAM2_MEM_BASE (0x20040000UL) /**< RAM2 base address */
+#define RAM2_MEM_SIZE (0x800UL) /**< RAM2 available address space */
+#define RAM2_MEM_END (0x200407FFUL) /**< RAM2 end address */
+#define RAM2_MEM_BITS (0x0000000BUL) /**< RAM2 used bits */
#define CRYPTO0_BITCLR_MEM_BASE (0x440F0000UL) /**< CRYPTO0_BITCLR base address */
#define CRYPTO0_BITCLR_MEM_SIZE (0x400UL) /**< CRYPTO0_BITCLR available address space */
#define CRYPTO0_BITCLR_MEM_END (0x440F03FFUL) /**< CRYPTO0_BITCLR end address */
@@ -213,22 +172,62 @@ typedef enum IRQn{
#define CRYPTO_BITCLR_MEM_SIZE CRYPTO0_BITCLR_MEM_SIZE /**< Alias for CRYPTO0_BITCLR_MEM_SIZE */
#define CRYPTO_BITCLR_MEM_END CRYPTO0_BITCLR_MEM_END /**< Alias for CRYPTO0_BITCLR_MEM_END */
#define CRYPTO_BITCLR_MEM_BITS CRYPTO0_BITCLR_MEM_BITS /**< Alias for CRYPTO0_BITCLR_MEM_BITS */
-#define PER_BITSET_MEM_BASE (0x46000000UL) /**< PER_BITSET base address */
-#define PER_BITSET_MEM_SIZE (0xF0000UL) /**< PER_BITSET available address space */
-#define PER_BITSET_MEM_END (0x460EFFFFUL) /**< PER_BITSET end address */
-#define PER_BITSET_MEM_BITS (0x00000014UL) /**< PER_BITSET used bits */
+#define CRYPTO1_MEM_BASE (0x400F0400UL) /**< CRYPTO1 base address */
+#define CRYPTO1_MEM_SIZE (0x400UL) /**< CRYPTO1 available address space */
+#define CRYPTO1_MEM_END (0x400F07FFUL) /**< CRYPTO1 end address */
+#define CRYPTO1_MEM_BITS (0x0000000AUL) /**< CRYPTO1 used bits */
+#define CRYPTO0_BITSET_MEM_BASE (0x460F0000UL) /**< CRYPTO0_BITSET base address */
+#define CRYPTO0_BITSET_MEM_SIZE (0x400UL) /**< CRYPTO0_BITSET available address space */
+#define CRYPTO0_BITSET_MEM_END (0x460F03FFUL) /**< CRYPTO0_BITSET end address */
+#define CRYPTO0_BITSET_MEM_BITS (0x0000000AUL) /**< CRYPTO0_BITSET used bits */
+#define CRYPTO_BITSET_MEM_BASE CRYPTO0_BITSET_MEM_BASE /**< Alias for CRYPTO0_BITSET_MEM_BASE */
+#define CRYPTO_BITSET_MEM_SIZE CRYPTO0_BITSET_MEM_SIZE /**< Alias for CRYPTO0_BITSET_MEM_SIZE */
+#define CRYPTO_BITSET_MEM_END CRYPTO0_BITSET_MEM_END /**< Alias for CRYPTO0_BITSET_MEM_END */
+#define CRYPTO_BITSET_MEM_BITS CRYPTO0_BITSET_MEM_BITS /**< Alias for CRYPTO0_BITSET_MEM_BITS */
+#define RAM1_CODE_MEM_BASE (0x10020000UL) /**< RAM1_CODE base address */
+#define RAM1_CODE_MEM_SIZE (0x20000UL) /**< RAM1_CODE available address space */
+#define RAM1_CODE_MEM_END (0x1003FFFFUL) /**< RAM1_CODE end address */
+#define RAM1_CODE_MEM_BITS (0x00000011UL) /**< RAM1_CODE used bits */
+#define RAM0_CODE_MEM_BASE (0x10000000UL) /**< RAM0_CODE base address */
+#define RAM0_CODE_MEM_SIZE (0x20000UL) /**< RAM0_CODE available address space */
+#define RAM0_CODE_MEM_END (0x1001FFFFUL) /**< RAM0_CODE end address */
+#define RAM0_CODE_MEM_BITS (0x00000011UL) /**< RAM0_CODE used bits */
+#define FLASH_MEM_BASE (0x00000000UL) /**< FLASH base address */
+#define FLASH_MEM_SIZE (0x10000000UL) /**< FLASH available address space */
+#define FLASH_MEM_END (0x0FFFFFFFUL) /**< FLASH end address */
+#define FLASH_MEM_BITS (0x0000001CUL) /**< FLASH used bits */
#define CRYPTO1_BITSET_MEM_BASE (0x460F0400UL) /**< CRYPTO1_BITSET base address */
#define CRYPTO1_BITSET_MEM_SIZE (0x400UL) /**< CRYPTO1_BITSET available address space */
#define CRYPTO1_BITSET_MEM_END (0x460F07FFUL) /**< CRYPTO1_BITSET end address */
#define CRYPTO1_BITSET_MEM_BITS (0x0000000AUL) /**< CRYPTO1_BITSET used bits */
-#define RAM2_CODE_MEM_BASE (0x10040000UL) /**< RAM2_CODE base address */
-#define RAM2_CODE_MEM_SIZE (0x800UL) /**< RAM2_CODE available address space */
-#define RAM2_CODE_MEM_END (0x100407FFUL) /**< RAM2_CODE end address */
-#define RAM2_CODE_MEM_BITS (0x0000000BUL) /**< RAM2_CODE used bits */
#define RAM_MEM_BASE (0x20000000UL) /**< RAM base address */
#define RAM_MEM_SIZE (0x20000UL) /**< RAM available address space */
#define RAM_MEM_END (0x2001FFFFUL) /**< RAM end address */
#define RAM_MEM_BITS (0x00000011UL) /**< RAM used bits */
+#define CRYPTO0_MEM_BASE (0x400F0000UL) /**< CRYPTO0 base address */
+#define CRYPTO0_MEM_SIZE (0x400UL) /**< CRYPTO0 available address space */
+#define CRYPTO0_MEM_END (0x400F03FFUL) /**< CRYPTO0 end address */
+#define CRYPTO0_MEM_BITS (0x0000000AUL) /**< CRYPTO0 used bits */
+#define CRYPTO_MEM_BASE CRYPTO0_MEM_BASE /**< Alias for CRYPTO0_MEM_BASE */
+#define CRYPTO_MEM_SIZE CRYPTO0_MEM_SIZE /**< Alias for CRYPTO0_MEM_SIZE */
+#define CRYPTO_MEM_END CRYPTO0_MEM_END /**< Alias for CRYPTO0_MEM_END */
+#define CRYPTO_MEM_BITS CRYPTO0_MEM_BITS /**< Alias for CRYPTO0_MEM_BITS */
+#define PER_BITSET_MEM_BASE (0x46000000UL) /**< PER_BITSET base address */
+#define PER_BITSET_MEM_SIZE (0xF0000UL) /**< PER_BITSET available address space */
+#define PER_BITSET_MEM_END (0x460EFFFFUL) /**< PER_BITSET end address */
+#define PER_BITSET_MEM_BITS (0x00000014UL) /**< PER_BITSET used bits */
+#define PER_MEM_BASE (0x40000000UL) /**< PER base address */
+#define PER_MEM_SIZE (0xF0000UL) /**< PER available address space */
+#define PER_MEM_END (0x400EFFFFUL) /**< PER end address */
+#define PER_MEM_BITS (0x00000014UL) /**< PER used bits */
+#define RAM2_CODE_MEM_BASE (0x10040000UL) /**< RAM2_CODE base address */
+#define RAM2_CODE_MEM_SIZE (0x800UL) /**< RAM2_CODE available address space */
+#define RAM2_CODE_MEM_END (0x100407FFUL) /**< RAM2_CODE end address */
+#define RAM2_CODE_MEM_BITS (0x0000000BUL) /**< RAM2_CODE used bits */
+#define PER_BITCLR_MEM_BASE (0x44000000UL) /**< PER_BITCLR base address */
+#define PER_BITCLR_MEM_SIZE (0xF0000UL) /**< PER_BITCLR available address space */
+#define PER_BITCLR_MEM_END (0x440EFFFFUL) /**< PER_BITCLR end address */
+#define PER_BITCLR_MEM_BITS (0x00000014UL) /**< PER_BITCLR used bits */
/** Bit banding area */
#define BITBAND_PER_BASE (0x42000000UL) /**< Peripheral Address Space bit-band area */
@@ -1013,13 +1012,13 @@ typedef enum IRQn{
#define _WTIMER_LOCK_TIMERLOCKKEY_SHIFT 0 /**< Shift value for TIMER_TIMERLOCKKEY */
#define _WTIMER_LOCK_TIMERLOCKKEY_MASK 0xFFFFUL /**< Bit mask for TIMER_TIMERLOCKKEY */
#define _WTIMER_LOCK_TIMERLOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_LOCK */
-#define _WTIMER_LOCK_TIMERLOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for WTIMER_LOCK */
#define _WTIMER_LOCK_TIMERLOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for WTIMER_LOCK */
+#define _WTIMER_LOCK_TIMERLOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for WTIMER_LOCK */
#define _WTIMER_LOCK_TIMERLOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for WTIMER_LOCK */
#define _WTIMER_LOCK_TIMERLOCKKEY_UNLOCK 0x0000CE80UL /**< Mode UNLOCK for WTIMER_LOCK */
#define WTIMER_LOCK_TIMERLOCKKEY_DEFAULT (_WTIMER_LOCK_TIMERLOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_LOCK */
-#define WTIMER_LOCK_TIMERLOCKKEY_LOCK (_WTIMER_LOCK_TIMERLOCKKEY_LOCK << 0) /**< Shifted mode LOCK for WTIMER_LOCK */
#define WTIMER_LOCK_TIMERLOCKKEY_UNLOCKED (_WTIMER_LOCK_TIMERLOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for WTIMER_LOCK */
+#define WTIMER_LOCK_TIMERLOCKKEY_LOCK (_WTIMER_LOCK_TIMERLOCKKEY_LOCK << 0) /**< Shifted mode LOCK for WTIMER_LOCK */
#define WTIMER_LOCK_TIMERLOCKKEY_LOCKED (_WTIMER_LOCK_TIMERLOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for WTIMER_LOCK */
#define WTIMER_LOCK_TIMERLOCKKEY_UNLOCK (_WTIMER_LOCK_TIMERLOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for WTIMER_LOCK */
@@ -2000,13 +1999,13 @@ typedef enum IRQn{
#define _WTIMER_DTLOCK_LOCKKEY_SHIFT 0 /**< Shift value for TIMER_LOCKKEY */
#define _WTIMER_DTLOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for TIMER_LOCKKEY */
#define _WTIMER_DTLOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTLOCK */
-#define _WTIMER_DTLOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for WTIMER_DTLOCK */
#define _WTIMER_DTLOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for WTIMER_DTLOCK */
+#define _WTIMER_DTLOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for WTIMER_DTLOCK */
#define _WTIMER_DTLOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for WTIMER_DTLOCK */
#define _WTIMER_DTLOCK_LOCKKEY_UNLOCK 0x0000CE80UL /**< Mode UNLOCK for WTIMER_DTLOCK */
#define WTIMER_DTLOCK_LOCKKEY_DEFAULT (_WTIMER_DTLOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTLOCK */
-#define WTIMER_DTLOCK_LOCKKEY_LOCK (_WTIMER_DTLOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for WTIMER_DTLOCK */
#define WTIMER_DTLOCK_LOCKKEY_UNLOCKED (_WTIMER_DTLOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for WTIMER_DTLOCK */
+#define WTIMER_DTLOCK_LOCKKEY_LOCK (_WTIMER_DTLOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for WTIMER_DTLOCK */
#define WTIMER_DTLOCK_LOCKKEY_LOCKED (_WTIMER_DTLOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for WTIMER_DTLOCK */
#define WTIMER_DTLOCK_LOCKKEY_UNLOCK (_WTIMER_DTLOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for WTIMER_DTLOCK */
diff --git a/cpu/efm32/families/efm32pg12b/include/vendor/efm32pg12b_acmp.h b/cpu/efm32/families/efm32pg12b/include/vendor/efm32pg12b_acmp.h
index 16bf24e52a..cfbeb59ca7 100644
--- a/cpu/efm32/families/efm32pg12b/include/vendor/efm32pg12b_acmp.h
+++ b/cpu/efm32/families/efm32pg12b/include/vendor/efm32pg12b_acmp.h
@@ -1,10 +1,9 @@
/***************************************************************************//**
* @file
* @brief EFM32PG12B_ACMP register and bit field definitions
- * @version 5.8.3
*******************************************************************************
* # License
- * Copyright 2019 Silicon Laboratories Inc. www.silabs.com
+ * Copyright 2020 Silicon Laboratories Inc. www.silabs.com
*******************************************************************************
*
* SPDX-License-Identifier: Zlib
@@ -325,6 +324,8 @@ typedef struct {
#define _ACMP_INPUTSEL_POSSEL_APORT4XCH11 0x0000008BUL /**< Mode APORT4XCH11 for ACMP_INPUTSEL */
#define _ACMP_INPUTSEL_POSSEL_APORT4YCH12 0x0000008CUL /**< Mode APORT4YCH12 for ACMP_INPUTSEL */
#define _ACMP_INPUTSEL_POSSEL_APORT4XCH13 0x0000008DUL /**< Mode APORT4XCH13 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_POSSEL_APORT4YCH14 0x0000008EUL /**< Mode APORT4YCH14 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_POSSEL_APORT4XCH15 0x0000008FUL /**< Mode APORT4XCH15 for ACMP_INPUTSEL */
#define _ACMP_INPUTSEL_POSSEL_APORT4YCH16 0x00000090UL /**< Mode APORT4YCH16 for ACMP_INPUTSEL */
#define _ACMP_INPUTSEL_POSSEL_APORT4XCH17 0x00000091UL /**< Mode APORT4XCH17 for ACMP_INPUTSEL */
#define _ACMP_INPUTSEL_POSSEL_APORT4YCH18 0x00000092UL /**< Mode APORT4YCH18 for ACMP_INPUTSEL */
@@ -340,8 +341,6 @@ typedef struct {
#define _ACMP_INPUTSEL_POSSEL_APORT4YCH28 0x0000009CUL /**< Mode APORT4YCH28 for ACMP_INPUTSEL */
#define _ACMP_INPUTSEL_POSSEL_APORT4XCH29 0x0000009DUL /**< Mode APORT4XCH29 for ACMP_INPUTSEL */
#define _ACMP_INPUTSEL_POSSEL_APORT4YCH30 0x0000009EUL /**< Mode APORT4YCH30 for ACMP_INPUTSEL */
-#define _ACMP_INPUTSEL_POSSEL_APORT4YCH14 0x0000009EUL /**< Mode APORT4YCH14 for ACMP_INPUTSEL */
-#define _ACMP_INPUTSEL_POSSEL_APORT4XCH15 0x0000009FUL /**< Mode APORT4XCH15 for ACMP_INPUTSEL */
#define _ACMP_INPUTSEL_POSSEL_APORT4XCH31 0x0000009FUL /**< Mode APORT4XCH31 for ACMP_INPUTSEL */
#define _ACMP_INPUTSEL_POSSEL_DACOUT0 0x000000F2UL /**< Mode DACOUT0 for ACMP_INPUTSEL */
#define _ACMP_INPUTSEL_POSSEL_DACOUT1 0x000000F3UL /**< Mode DACOUT1 for ACMP_INPUTSEL */
@@ -493,6 +492,8 @@ typedef struct {
#define ACMP_INPUTSEL_POSSEL_APORT4XCH11 (_ACMP_INPUTSEL_POSSEL_APORT4XCH11 << 0) /**< Shifted mode APORT4XCH11 for ACMP_INPUTSEL */
#define ACMP_INPUTSEL_POSSEL_APORT4YCH12 (_ACMP_INPUTSEL_POSSEL_APORT4YCH12 << 0) /**< Shifted mode APORT4YCH12 for ACMP_INPUTSEL */
#define ACMP_INPUTSEL_POSSEL_APORT4XCH13 (_ACMP_INPUTSEL_POSSEL_APORT4XCH13 << 0) /**< Shifted mode APORT4XCH13 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_POSSEL_APORT4YCH14 (_ACMP_INPUTSEL_POSSEL_APORT4YCH14 << 0) /**< Shifted mode APORT4YCH14 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_POSSEL_APORT4XCH15 (_ACMP_INPUTSEL_POSSEL_APORT4XCH15 << 0) /**< Shifted mode APORT4XCH15 for ACMP_INPUTSEL */
#define ACMP_INPUTSEL_POSSEL_APORT4YCH16 (_ACMP_INPUTSEL_POSSEL_APORT4YCH16 << 0) /**< Shifted mode APORT4YCH16 for ACMP_INPUTSEL */
#define ACMP_INPUTSEL_POSSEL_APORT4XCH17 (_ACMP_INPUTSEL_POSSEL_APORT4XCH17 << 0) /**< Shifted mode APORT4XCH17 for ACMP_INPUTSEL */
#define ACMP_INPUTSEL_POSSEL_APORT4YCH18 (_ACMP_INPUTSEL_POSSEL_APORT4YCH18 << 0) /**< Shifted mode APORT4YCH18 for ACMP_INPUTSEL */
@@ -508,8 +509,6 @@ typedef struct {
#define ACMP_INPUTSEL_POSSEL_APORT4YCH28 (_ACMP_INPUTSEL_POSSEL_APORT4YCH28 << 0) /**< Shifted mode APORT4YCH28 for ACMP_INPUTSEL */
#define ACMP_INPUTSEL_POSSEL_APORT4XCH29 (_ACMP_INPUTSEL_POSSEL_APORT4XCH29 << 0) /**< Shifted mode APORT4XCH29 for ACMP_INPUTSEL */
#define ACMP_INPUTSEL_POSSEL_APORT4YCH30 (_ACMP_INPUTSEL_POSSEL_APORT4YCH30 << 0) /**< Shifted mode APORT4YCH30 for ACMP_INPUTSEL */
-#define ACMP_INPUTSEL_POSSEL_APORT4YCH14 (_ACMP_INPUTSEL_POSSEL_APORT4YCH14 << 0) /**< Shifted mode APORT4YCH14 for ACMP_INPUTSEL */
-#define ACMP_INPUTSEL_POSSEL_APORT4XCH15 (_ACMP_INPUTSEL_POSSEL_APORT4XCH15 << 0) /**< Shifted mode APORT4XCH15 for ACMP_INPUTSEL */
#define ACMP_INPUTSEL_POSSEL_APORT4XCH31 (_ACMP_INPUTSEL_POSSEL_APORT4XCH31 << 0) /**< Shifted mode APORT4XCH31 for ACMP_INPUTSEL */
#define ACMP_INPUTSEL_POSSEL_DACOUT0 (_ACMP_INPUTSEL_POSSEL_DACOUT0 << 0) /**< Shifted mode DACOUT0 for ACMP_INPUTSEL */
#define ACMP_INPUTSEL_POSSEL_DACOUT1 (_ACMP_INPUTSEL_POSSEL_DACOUT1 << 0) /**< Shifted mode DACOUT1 for ACMP_INPUTSEL */
@@ -663,6 +662,8 @@ typedef struct {
#define _ACMP_INPUTSEL_NEGSEL_APORT4XCH11 0x0000008BUL /**< Mode APORT4XCH11 for ACMP_INPUTSEL */
#define _ACMP_INPUTSEL_NEGSEL_APORT4YCH12 0x0000008CUL /**< Mode APORT4YCH12 for ACMP_INPUTSEL */
#define _ACMP_INPUTSEL_NEGSEL_APORT4XCH13 0x0000008DUL /**< Mode APORT4XCH13 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_NEGSEL_APORT4YCH14 0x0000008EUL /**< Mode APORT4YCH14 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_NEGSEL_APORT4XCH15 0x0000008FUL /**< Mode APORT4XCH15 for ACMP_INPUTSEL */
#define _ACMP_INPUTSEL_NEGSEL_APORT4YCH16 0x00000090UL /**< Mode APORT4YCH16 for ACMP_INPUTSEL */
#define _ACMP_INPUTSEL_NEGSEL_APORT4XCH17 0x00000091UL /**< Mode APORT4XCH17 for ACMP_INPUTSEL */
#define _ACMP_INPUTSEL_NEGSEL_APORT4YCH18 0x00000092UL /**< Mode APORT4YCH18 for ACMP_INPUTSEL */
@@ -678,8 +679,6 @@ typedef struct {
#define _ACMP_INPUTSEL_NEGSEL_APORT4YCH28 0x0000009CUL /**< Mode APORT4YCH28 for ACMP_INPUTSEL */
#define _ACMP_INPUTSEL_NEGSEL_APORT4XCH29 0x0000009DUL /**< Mode APORT4XCH29 for ACMP_INPUTSEL */
#define _ACMP_INPUTSEL_NEGSEL_APORT4YCH30 0x0000009EUL /**< Mode APORT4YCH30 for ACMP_INPUTSEL */
-#define _ACMP_INPUTSEL_NEGSEL_APORT4YCH14 0x0000009EUL /**< Mode APORT4YCH14 for ACMP_INPUTSEL */
-#define _ACMP_INPUTSEL_NEGSEL_APORT4XCH15 0x0000009FUL /**< Mode APORT4XCH15 for ACMP_INPUTSEL */
#define _ACMP_INPUTSEL_NEGSEL_APORT4XCH31 0x0000009FUL /**< Mode APORT4XCH31 for ACMP_INPUTSEL */
#define _ACMP_INPUTSEL_NEGSEL_DACOUT0 0x000000F2UL /**< Mode DACOUT0 for ACMP_INPUTSEL */
#define _ACMP_INPUTSEL_NEGSEL_DACOUT1 0x000000F3UL /**< Mode DACOUT1 for ACMP_INPUTSEL */
@@ -831,6 +830,8 @@ typedef struct {
#define ACMP_INPUTSEL_NEGSEL_APORT4XCH11 (_ACMP_INPUTSEL_NEGSEL_APORT4XCH11 << 8) /**< Shifted mode APORT4XCH11 for ACMP_INPUTSEL */
#define ACMP_INPUTSEL_NEGSEL_APORT4YCH12 (_ACMP_INPUTSEL_NEGSEL_APORT4YCH12 << 8) /**< Shifted mode APORT4YCH12 for ACMP_INPUTSEL */
#define ACMP_INPUTSEL_NEGSEL_APORT4XCH13 (_ACMP_INPUTSEL_NEGSEL_APORT4XCH13 << 8) /**< Shifted mode APORT4XCH13 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_NEGSEL_APORT4YCH14 (_ACMP_INPUTSEL_NEGSEL_APORT4YCH14 << 8) /**< Shifted mode APORT4YCH14 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_NEGSEL_APORT4XCH15 (_ACMP_INPUTSEL_NEGSEL_APORT4XCH15 << 8) /**< Shifted mode APORT4XCH15 for ACMP_INPUTSEL */
#define ACMP_INPUTSEL_NEGSEL_APORT4YCH16 (_ACMP_INPUTSEL_NEGSEL_APORT4YCH16 << 8) /**< Shifted mode APORT4YCH16 for ACMP_INPUTSEL */
#define ACMP_INPUTSEL_NEGSEL_APORT4XCH17 (_ACMP_INPUTSEL_NEGSEL_APORT4XCH17 << 8) /**< Shifted mode APORT4XCH17 for ACMP_INPUTSEL */
#define ACMP_INPUTSEL_NEGSEL_APORT4YCH18 (_ACMP_INPUTSEL_NEGSEL_APORT4YCH18 << 8) /**< Shifted mode APORT4YCH18 for ACMP_INPUTSEL */
@@ -846,8 +847,6 @@ typedef struct {
#define ACMP_INPUTSEL_NEGSEL_APORT4YCH28 (_ACMP_INPUTSEL_NEGSEL_APORT4YCH28 << 8) /**< Shifted mode APORT4YCH28 for ACMP_INPUTSEL */
#define ACMP_INPUTSEL_NEGSEL_APORT4XCH29 (_ACMP_INPUTSEL_NEGSEL_APORT4XCH29 << 8) /**< Shifted mode APORT4XCH29 for ACMP_INPUTSEL */
#define ACMP_INPUTSEL_NEGSEL_APORT4YCH30 (_ACMP_INPUTSEL_NEGSEL_APORT4YCH30 << 8) /**< Shifted mode APORT4YCH30 for ACMP_INPUTSEL */
-#define ACMP_INPUTSEL_NEGSEL_APORT4YCH14 (_ACMP_INPUTSEL_NEGSEL_APORT4YCH14 << 8) /**< Shifted mode APORT4YCH14 for ACMP_INPUTSEL */
-#define ACMP_INPUTSEL_NEGSEL_APORT4XCH15 (_ACMP_INPUTSEL_NEGSEL_APORT4XCH15 << 8) /**< Shifted mode APORT4XCH15 for ACMP_INPUTSEL */
#define ACMP_INPUTSEL_NEGSEL_APORT4XCH31 (_ACMP_INPUTSEL_NEGSEL_APORT4XCH31 << 8) /**< Shifted mode APORT4XCH31 for ACMP_INPUTSEL */
#define ACMP_INPUTSEL_NEGSEL_DACOUT0 (_ACMP_INPUTSEL_NEGSEL_DACOUT0 << 8) /**< Shifted mode DACOUT0 for ACMP_INPUTSEL */
#define ACMP_INPUTSEL_NEGSEL_DACOUT1 (_ACMP_INPUTSEL_NEGSEL_DACOUT1 << 8) /**< Shifted mode DACOUT1 for ACMP_INPUTSEL */
diff --git a/cpu/efm32/families/efm32pg12b/include/vendor/efm32pg12b_adc.h b/cpu/efm32/families/efm32pg12b/include/vendor/efm32pg12b_adc.h
index 1950a1745f..f2b5c72716 100644
--- a/cpu/efm32/families/efm32pg12b/include/vendor/efm32pg12b_adc.h
+++ b/cpu/efm32/families/efm32pg12b/include/vendor/efm32pg12b_adc.h
@@ -1,10 +1,9 @@
/***************************************************************************//**
* @file
* @brief EFM32PG12B_ADC register and bit field definitions
- * @version 5.8.3
*******************************************************************************
* # License
- * Copyright 2019 Silicon Laboratories Inc. www.silabs.com
+ * Copyright 2020 Silicon Laboratories Inc. www.silabs.com
*******************************************************************************
*
* SPDX-License-Identifier: Zlib
@@ -1383,133 +1382,133 @@ typedef struct {
#define _ADC_SCANMASK_SCANINPUTEN_SHIFT 0 /**< Shift value for ADC_SCANINPUTEN */
#define _ADC_SCANMASK_SCANINPUTEN_MASK 0xFFFFFFFFUL /**< Bit mask for ADC_SCANINPUTEN */
#define _ADC_SCANMASK_SCANINPUTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SCANMASK */
-#define _ADC_SCANMASK_SCANINPUTEN_INPUT0INPUT0NEGSEL 0x00000001UL /**< Mode INPUT0INPUT0NEGSEL for ADC_SCANMASK */
#define _ADC_SCANMASK_SCANINPUTEN_INPUT0 0x00000001UL /**< Mode INPUT0 for ADC_SCANMASK */
-#define _ADC_SCANMASK_SCANINPUTEN_INPUT1 0x00000002UL /**< Mode INPUT1 for ADC_SCANMASK */
+#define _ADC_SCANMASK_SCANINPUTEN_INPUT0INPUT0NEGSEL 0x00000001UL /**< Mode INPUT0INPUT0NEGSEL for ADC_SCANMASK */
#define _ADC_SCANMASK_SCANINPUTEN_INPUT1INPUT2 0x00000002UL /**< Mode INPUT1INPUT2 for ADC_SCANMASK */
+#define _ADC_SCANMASK_SCANINPUTEN_INPUT1 0x00000002UL /**< Mode INPUT1 for ADC_SCANMASK */
#define _ADC_SCANMASK_SCANINPUTEN_INPUT2 0x00000004UL /**< Mode INPUT2 for ADC_SCANMASK */
#define _ADC_SCANMASK_SCANINPUTEN_INPUT2INPUT2NEGSEL 0x00000004UL /**< Mode INPUT2INPUT2NEGSEL for ADC_SCANMASK */
-#define _ADC_SCANMASK_SCANINPUTEN_INPUT3 0x00000008UL /**< Mode INPUT3 for ADC_SCANMASK */
#define _ADC_SCANMASK_SCANINPUTEN_INPUT3INPUT4 0x00000008UL /**< Mode INPUT3INPUT4 for ADC_SCANMASK */
-#define _ADC_SCANMASK_SCANINPUTEN_INPUT4 0x00000010UL /**< Mode INPUT4 for ADC_SCANMASK */
+#define _ADC_SCANMASK_SCANINPUTEN_INPUT3 0x00000008UL /**< Mode INPUT3 for ADC_SCANMASK */
#define _ADC_SCANMASK_SCANINPUTEN_INPUT4INPUT4NEGSEL 0x00000010UL /**< Mode INPUT4INPUT4NEGSEL for ADC_SCANMASK */
+#define _ADC_SCANMASK_SCANINPUTEN_INPUT4 0x00000010UL /**< Mode INPUT4 for ADC_SCANMASK */
#define _ADC_SCANMASK_SCANINPUTEN_INPUT5INPUT6 0x00000020UL /**< Mode INPUT5INPUT6 for ADC_SCANMASK */
#define _ADC_SCANMASK_SCANINPUTEN_INPUT5 0x00000020UL /**< Mode INPUT5 for ADC_SCANMASK */
-#define _ADC_SCANMASK_SCANINPUTEN_INPUT6INPUT6NEGSEL 0x00000040UL /**< Mode INPUT6INPUT6NEGSEL for ADC_SCANMASK */
#define _ADC_SCANMASK_SCANINPUTEN_INPUT6 0x00000040UL /**< Mode INPUT6 for ADC_SCANMASK */
-#define _ADC_SCANMASK_SCANINPUTEN_INPUT7 0x00000080UL /**< Mode INPUT7 for ADC_SCANMASK */
+#define _ADC_SCANMASK_SCANINPUTEN_INPUT6INPUT6NEGSEL 0x00000040UL /**< Mode INPUT6INPUT6NEGSEL for ADC_SCANMASK */
#define _ADC_SCANMASK_SCANINPUTEN_INPUT7INPUT0 0x00000080UL /**< Mode INPUT7INPUT0 for ADC_SCANMASK */
-#define _ADC_SCANMASK_SCANINPUTEN_INPUT8INPUT9 0x00000100UL /**< Mode INPUT8INPUT9 for ADC_SCANMASK */
+#define _ADC_SCANMASK_SCANINPUTEN_INPUT7 0x00000080UL /**< Mode INPUT7 for ADC_SCANMASK */
#define _ADC_SCANMASK_SCANINPUTEN_INPUT8 0x00000100UL /**< Mode INPUT8 for ADC_SCANMASK */
-#define _ADC_SCANMASK_SCANINPUTEN_INPUT9 0x00000200UL /**< Mode INPUT9 for ADC_SCANMASK */
+#define _ADC_SCANMASK_SCANINPUTEN_INPUT8INPUT9 0x00000100UL /**< Mode INPUT8INPUT9 for ADC_SCANMASK */
#define _ADC_SCANMASK_SCANINPUTEN_INPUT9INPUT9NEGSEL 0x00000200UL /**< Mode INPUT9INPUT9NEGSEL for ADC_SCANMASK */
-#define _ADC_SCANMASK_SCANINPUTEN_INPUT10INPUT11 0x00000400UL /**< Mode INPUT10INPUT11 for ADC_SCANMASK */
+#define _ADC_SCANMASK_SCANINPUTEN_INPUT9 0x00000200UL /**< Mode INPUT9 for ADC_SCANMASK */
#define _ADC_SCANMASK_SCANINPUTEN_INPUT10 0x00000400UL /**< Mode INPUT10 for ADC_SCANMASK */
-#define _ADC_SCANMASK_SCANINPUTEN_INPUT11INPUT11NEGSEL 0x00000800UL /**< Mode INPUT11INPUT11NEGSEL for ADC_SCANMASK */
+#define _ADC_SCANMASK_SCANINPUTEN_INPUT10INPUT11 0x00000400UL /**< Mode INPUT10INPUT11 for ADC_SCANMASK */
#define _ADC_SCANMASK_SCANINPUTEN_INPUT11 0x00000800UL /**< Mode INPUT11 for ADC_SCANMASK */
-#define _ADC_SCANMASK_SCANINPUTEN_INPUT12INPUT13 0x00001000UL /**< Mode INPUT12INPUT13 for ADC_SCANMASK */
+#define _ADC_SCANMASK_SCANINPUTEN_INPUT11INPUT11NEGSEL 0x00000800UL /**< Mode INPUT11INPUT11NEGSEL for ADC_SCANMASK */
#define _ADC_SCANMASK_SCANINPUTEN_INPUT12 0x00001000UL /**< Mode INPUT12 for ADC_SCANMASK */
-#define _ADC_SCANMASK_SCANINPUTEN_INPUT13INPUT13NEGSEL 0x00002000UL /**< Mode INPUT13INPUT13NEGSEL for ADC_SCANMASK */
+#define _ADC_SCANMASK_SCANINPUTEN_INPUT12INPUT13 0x00001000UL /**< Mode INPUT12INPUT13 for ADC_SCANMASK */
#define _ADC_SCANMASK_SCANINPUTEN_INPUT13 0x00002000UL /**< Mode INPUT13 for ADC_SCANMASK */
-#define _ADC_SCANMASK_SCANINPUTEN_INPUT14INPUT15 0x00004000UL /**< Mode INPUT14INPUT15 for ADC_SCANMASK */
+#define _ADC_SCANMASK_SCANINPUTEN_INPUT13INPUT13NEGSEL 0x00002000UL /**< Mode INPUT13INPUT13NEGSEL for ADC_SCANMASK */
#define _ADC_SCANMASK_SCANINPUTEN_INPUT14 0x00004000UL /**< Mode INPUT14 for ADC_SCANMASK */
-#define _ADC_SCANMASK_SCANINPUTEN_INPUT15INPUT15NEGSEL 0x00008000UL /**< Mode INPUT15INPUT15NEGSEL for ADC_SCANMASK */
+#define _ADC_SCANMASK_SCANINPUTEN_INPUT14INPUT15 0x00004000UL /**< Mode INPUT14INPUT15 for ADC_SCANMASK */
#define _ADC_SCANMASK_SCANINPUTEN_INPUT15 0x00008000UL /**< Mode INPUT15 for ADC_SCANMASK */
-#define _ADC_SCANMASK_SCANINPUTEN_INPUT16INPUT17 0x00010000UL /**< Mode INPUT16INPUT17 for ADC_SCANMASK */
+#define _ADC_SCANMASK_SCANINPUTEN_INPUT15INPUT15NEGSEL 0x00008000UL /**< Mode INPUT15INPUT15NEGSEL for ADC_SCANMASK */
#define _ADC_SCANMASK_SCANINPUTEN_INPUT16 0x00010000UL /**< Mode INPUT16 for ADC_SCANMASK */
-#define _ADC_SCANMASK_SCANINPUTEN_INPUT17INPUT18 0x00020000UL /**< Mode INPUT17INPUT18 for ADC_SCANMASK */
+#define _ADC_SCANMASK_SCANINPUTEN_INPUT16INPUT17 0x00010000UL /**< Mode INPUT16INPUT17 for ADC_SCANMASK */
#define _ADC_SCANMASK_SCANINPUTEN_INPUT17 0x00020000UL /**< Mode INPUT17 for ADC_SCANMASK */
+#define _ADC_SCANMASK_SCANINPUTEN_INPUT17INPUT18 0x00020000UL /**< Mode INPUT17INPUT18 for ADC_SCANMASK */
#define _ADC_SCANMASK_SCANINPUTEN_INPUT18INPUT19 0x00040000UL /**< Mode INPUT18INPUT19 for ADC_SCANMASK */
#define _ADC_SCANMASK_SCANINPUTEN_INPUT18 0x00040000UL /**< Mode INPUT18 for ADC_SCANMASK */
#define _ADC_SCANMASK_SCANINPUTEN_INPUT19 0x00080000UL /**< Mode INPUT19 for ADC_SCANMASK */
#define _ADC_SCANMASK_SCANINPUTEN_INPUT19INPUT20 0x00080000UL /**< Mode INPUT19INPUT20 for ADC_SCANMASK */
#define _ADC_SCANMASK_SCANINPUTEN_INPUT20INPUT21 0x00100000UL /**< Mode INPUT20INPUT21 for ADC_SCANMASK */
#define _ADC_SCANMASK_SCANINPUTEN_INPUT20 0x00100000UL /**< Mode INPUT20 for ADC_SCANMASK */
-#define _ADC_SCANMASK_SCANINPUTEN_INPUT21 0x00200000UL /**< Mode INPUT21 for ADC_SCANMASK */
#define _ADC_SCANMASK_SCANINPUTEN_INPUT21INPUT22 0x00200000UL /**< Mode INPUT21INPUT22 for ADC_SCANMASK */
+#define _ADC_SCANMASK_SCANINPUTEN_INPUT21 0x00200000UL /**< Mode INPUT21 for ADC_SCANMASK */
#define _ADC_SCANMASK_SCANINPUTEN_INPUT22INPUT23 0x00400000UL /**< Mode INPUT22INPUT23 for ADC_SCANMASK */
#define _ADC_SCANMASK_SCANINPUTEN_INPUT22 0x00400000UL /**< Mode INPUT22 for ADC_SCANMASK */
-#define _ADC_SCANMASK_SCANINPUTEN_INPUT23INPUT16 0x00800000UL /**< Mode INPUT23INPUT16 for ADC_SCANMASK */
#define _ADC_SCANMASK_SCANINPUTEN_INPUT23 0x00800000UL /**< Mode INPUT23 for ADC_SCANMASK */
-#define _ADC_SCANMASK_SCANINPUTEN_INPUT24 0x01000000UL /**< Mode INPUT24 for ADC_SCANMASK */
+#define _ADC_SCANMASK_SCANINPUTEN_INPUT23INPUT16 0x00800000UL /**< Mode INPUT23INPUT16 for ADC_SCANMASK */
#define _ADC_SCANMASK_SCANINPUTEN_INPUT24INPUT25 0x01000000UL /**< Mode INPUT24INPUT25 for ADC_SCANMASK */
-#define _ADC_SCANMASK_SCANINPUTEN_INPUT25INPUT26 0x02000000UL /**< Mode INPUT25INPUT26 for ADC_SCANMASK */
+#define _ADC_SCANMASK_SCANINPUTEN_INPUT24 0x01000000UL /**< Mode INPUT24 for ADC_SCANMASK */
#define _ADC_SCANMASK_SCANINPUTEN_INPUT25 0x02000000UL /**< Mode INPUT25 for ADC_SCANMASK */
-#define _ADC_SCANMASK_SCANINPUTEN_INPUT26 0x04000000UL /**< Mode INPUT26 for ADC_SCANMASK */
+#define _ADC_SCANMASK_SCANINPUTEN_INPUT25INPUT26 0x02000000UL /**< Mode INPUT25INPUT26 for ADC_SCANMASK */
#define _ADC_SCANMASK_SCANINPUTEN_INPUT26INPUT27 0x04000000UL /**< Mode INPUT26INPUT27 for ADC_SCANMASK */
-#define _ADC_SCANMASK_SCANINPUTEN_INPUT27INPUT28 0x08000000UL /**< Mode INPUT27INPUT28 for ADC_SCANMASK */
+#define _ADC_SCANMASK_SCANINPUTEN_INPUT26 0x04000000UL /**< Mode INPUT26 for ADC_SCANMASK */
#define _ADC_SCANMASK_SCANINPUTEN_INPUT27 0x08000000UL /**< Mode INPUT27 for ADC_SCANMASK */
-#define _ADC_SCANMASK_SCANINPUTEN_INPUT28INPUT29 0x10000000UL /**< Mode INPUT28INPUT29 for ADC_SCANMASK */
+#define _ADC_SCANMASK_SCANINPUTEN_INPUT27INPUT28 0x08000000UL /**< Mode INPUT27INPUT28 for ADC_SCANMASK */
#define _ADC_SCANMASK_SCANINPUTEN_INPUT28 0x10000000UL /**< Mode INPUT28 for ADC_SCANMASK */
+#define _ADC_SCANMASK_SCANINPUTEN_INPUT28INPUT29 0x10000000UL /**< Mode INPUT28INPUT29 for ADC_SCANMASK */
#define _ADC_SCANMASK_SCANINPUTEN_INPUT29 0x20000000UL /**< Mode INPUT29 for ADC_SCANMASK */
#define _ADC_SCANMASK_SCANINPUTEN_INPUT29INPUT30 0x20000000UL /**< Mode INPUT29INPUT30 for ADC_SCANMASK */
-#define _ADC_SCANMASK_SCANINPUTEN_INPUT30 0x40000000UL /**< Mode INPUT30 for ADC_SCANMASK */
#define _ADC_SCANMASK_SCANINPUTEN_INPUT30INPUT31 0x40000000UL /**< Mode INPUT30INPUT31 for ADC_SCANMASK */
+#define _ADC_SCANMASK_SCANINPUTEN_INPUT30 0x40000000UL /**< Mode INPUT30 for ADC_SCANMASK */
#define _ADC_SCANMASK_SCANINPUTEN_INPUT31INPUT24 0x80000000UL /**< Mode INPUT31INPUT24 for ADC_SCANMASK */
#define _ADC_SCANMASK_SCANINPUTEN_INPUT31 0x80000000UL /**< Mode INPUT31 for ADC_SCANMASK */
#define ADC_SCANMASK_SCANINPUTEN_DEFAULT (_ADC_SCANMASK_SCANINPUTEN_DEFAULT << 0) /**< Shifted mode DEFAULT for ADC_SCANMASK */
-#define ADC_SCANMASK_SCANINPUTEN_INPUT0INPUT0NEGSEL (_ADC_SCANMASK_SCANINPUTEN_INPUT0INPUT0NEGSEL << 0) /**< Shifted mode INPUT0INPUT0NEGSEL for ADC_SCANMASK */
#define ADC_SCANMASK_SCANINPUTEN_INPUT0 (_ADC_SCANMASK_SCANINPUTEN_INPUT0 << 0) /**< Shifted mode INPUT0 for ADC_SCANMASK */
-#define ADC_SCANMASK_SCANINPUTEN_INPUT1 (_ADC_SCANMASK_SCANINPUTEN_INPUT1 << 0) /**< Shifted mode INPUT1 for ADC_SCANMASK */
+#define ADC_SCANMASK_SCANINPUTEN_INPUT0INPUT0NEGSEL (_ADC_SCANMASK_SCANINPUTEN_INPUT0INPUT0NEGSEL << 0) /**< Shifted mode INPUT0INPUT0NEGSEL for ADC_SCANMASK */
#define ADC_SCANMASK_SCANINPUTEN_INPUT1INPUT2 (_ADC_SCANMASK_SCANINPUTEN_INPUT1INPUT2 << 0) /**< Shifted mode INPUT1INPUT2 for ADC_SCANMASK */
+#define ADC_SCANMASK_SCANINPUTEN_INPUT1 (_ADC_SCANMASK_SCANINPUTEN_INPUT1 << 0) /**< Shifted mode INPUT1 for ADC_SCANMASK */
#define ADC_SCANMASK_SCANINPUTEN_INPUT2 (_ADC_SCANMASK_SCANINPUTEN_INPUT2 << 0) /**< Shifted mode INPUT2 for ADC_SCANMASK */
#define ADC_SCANMASK_SCANINPUTEN_INPUT2INPUT2NEGSEL (_ADC_SCANMASK_SCANINPUTEN_INPUT2INPUT2NEGSEL << 0) /**< Shifted mode INPUT2INPUT2NEGSEL for ADC_SCANMASK */
-#define ADC_SCANMASK_SCANINPUTEN_INPUT3 (_ADC_SCANMASK_SCANINPUTEN_INPUT3 << 0) /**< Shifted mode INPUT3 for ADC_SCANMASK */
#define ADC_SCANMASK_SCANINPUTEN_INPUT3INPUT4 (_ADC_SCANMASK_SCANINPUTEN_INPUT3INPUT4 << 0) /**< Shifted mode INPUT3INPUT4 for ADC_SCANMASK */
-#define ADC_SCANMASK_SCANINPUTEN_INPUT4 (_ADC_SCANMASK_SCANINPUTEN_INPUT4 << 0) /**< Shifted mode INPUT4 for ADC_SCANMASK */
+#define ADC_SCANMASK_SCANINPUTEN_INPUT3 (_ADC_SCANMASK_SCANINPUTEN_INPUT3 << 0) /**< Shifted mode INPUT3 for ADC_SCANMASK */
#define ADC_SCANMASK_SCANINPUTEN_INPUT4INPUT4NEGSEL (_ADC_SCANMASK_SCANINPUTEN_INPUT4INPUT4NEGSEL << 0) /**< Shifted mode INPUT4INPUT4NEGSEL for ADC_SCANMASK */
+#define ADC_SCANMASK_SCANINPUTEN_INPUT4 (_ADC_SCANMASK_SCANINPUTEN_INPUT4 << 0) /**< Shifted mode INPUT4 for ADC_SCANMASK */
#define ADC_SCANMASK_SCANINPUTEN_INPUT5INPUT6 (_ADC_SCANMASK_SCANINPUTEN_INPUT5INPUT6 << 0) /**< Shifted mode INPUT5INPUT6 for ADC_SCANMASK */
#define ADC_SCANMASK_SCANINPUTEN_INPUT5 (_ADC_SCANMASK_SCANINPUTEN_INPUT5 << 0) /**< Shifted mode INPUT5 for ADC_SCANMASK */
-#define ADC_SCANMASK_SCANINPUTEN_INPUT6INPUT6NEGSEL (_ADC_SCANMASK_SCANINPUTEN_INPUT6INPUT6NEGSEL << 0) /**< Shifted mode INPUT6INPUT6NEGSEL for ADC_SCANMASK */
#define ADC_SCANMASK_SCANINPUTEN_INPUT6 (_ADC_SCANMASK_SCANINPUTEN_INPUT6 << 0) /**< Shifted mode INPUT6 for ADC_SCANMASK */
-#define ADC_SCANMASK_SCANINPUTEN_INPUT7 (_ADC_SCANMASK_SCANINPUTEN_INPUT7 << 0) /**< Shifted mode INPUT7 for ADC_SCANMASK */
+#define ADC_SCANMASK_SCANINPUTEN_INPUT6INPUT6NEGSEL (_ADC_SCANMASK_SCANINPUTEN_INPUT6INPUT6NEGSEL << 0) /**< Shifted mode INPUT6INPUT6NEGSEL for ADC_SCANMASK */
#define ADC_SCANMASK_SCANINPUTEN_INPUT7INPUT0 (_ADC_SCANMASK_SCANINPUTEN_INPUT7INPUT0 << 0) /**< Shifted mode INPUT7INPUT0 for ADC_SCANMASK */
-#define ADC_SCANMASK_SCANINPUTEN_INPUT8INPUT9 (_ADC_SCANMASK_SCANINPUTEN_INPUT8INPUT9 << 0) /**< Shifted mode INPUT8INPUT9 for ADC_SCANMASK */
+#define ADC_SCANMASK_SCANINPUTEN_INPUT7 (_ADC_SCANMASK_SCANINPUTEN_INPUT7 << 0) /**< Shifted mode INPUT7 for ADC_SCANMASK */
#define ADC_SCANMASK_SCANINPUTEN_INPUT8 (_ADC_SCANMASK_SCANINPUTEN_INPUT8 << 0) /**< Shifted mode INPUT8 for ADC_SCANMASK */
-#define ADC_SCANMASK_SCANINPUTEN_INPUT9 (_ADC_SCANMASK_SCANINPUTEN_INPUT9 << 0) /**< Shifted mode INPUT9 for ADC_SCANMASK */
+#define ADC_SCANMASK_SCANINPUTEN_INPUT8INPUT9 (_ADC_SCANMASK_SCANINPUTEN_INPUT8INPUT9 << 0) /**< Shifted mode INPUT8INPUT9 for ADC_SCANMASK */
#define ADC_SCANMASK_SCANINPUTEN_INPUT9INPUT9NEGSEL (_ADC_SCANMASK_SCANINPUTEN_INPUT9INPUT9NEGSEL << 0) /**< Shifted mode INPUT9INPUT9NEGSEL for ADC_SCANMASK */
-#define ADC_SCANMASK_SCANINPUTEN_INPUT10INPUT11 (_ADC_SCANMASK_SCANINPUTEN_INPUT10INPUT11 << 0) /**< Shifted mode INPUT10INPUT11 for ADC_SCANMASK */
+#define ADC_SCANMASK_SCANINPUTEN_INPUT9 (_ADC_SCANMASK_SCANINPUTEN_INPUT9 << 0) /**< Shifted mode INPUT9 for ADC_SCANMASK */
#define ADC_SCANMASK_SCANINPUTEN_INPUT10 (_ADC_SCANMASK_SCANINPUTEN_INPUT10 << 0) /**< Shifted mode INPUT10 for ADC_SCANMASK */
-#define ADC_SCANMASK_SCANINPUTEN_INPUT11INPUT11NEGSEL (_ADC_SCANMASK_SCANINPUTEN_INPUT11INPUT11NEGSEL << 0) /**< Shifted mode INPUT11INPUT11NEGSEL for ADC_SCANMASK */
+#define ADC_SCANMASK_SCANINPUTEN_INPUT10INPUT11 (_ADC_SCANMASK_SCANINPUTEN_INPUT10INPUT11 << 0) /**< Shifted mode INPUT10INPUT11 for ADC_SCANMASK */
#define ADC_SCANMASK_SCANINPUTEN_INPUT11 (_ADC_SCANMASK_SCANINPUTEN_INPUT11 << 0) /**< Shifted mode INPUT11 for ADC_SCANMASK */
-#define ADC_SCANMASK_SCANINPUTEN_INPUT12INPUT13 (_ADC_SCANMASK_SCANINPUTEN_INPUT12INPUT13 << 0) /**< Shifted mode INPUT12INPUT13 for ADC_SCANMASK */
+#define ADC_SCANMASK_SCANINPUTEN_INPUT11INPUT11NEGSEL (_ADC_SCANMASK_SCANINPUTEN_INPUT11INPUT11NEGSEL << 0) /**< Shifted mode INPUT11INPUT11NEGSEL for ADC_SCANMASK */
#define ADC_SCANMASK_SCANINPUTEN_INPUT12 (_ADC_SCANMASK_SCANINPUTEN_INPUT12 << 0) /**< Shifted mode INPUT12 for ADC_SCANMASK */
-#define ADC_SCANMASK_SCANINPUTEN_INPUT13INPUT13NEGSEL (_ADC_SCANMASK_SCANINPUTEN_INPUT13INPUT13NEGSEL << 0) /**< Shifted mode INPUT13INPUT13NEGSEL for ADC_SCANMASK */
+#define ADC_SCANMASK_SCANINPUTEN_INPUT12INPUT13 (_ADC_SCANMASK_SCANINPUTEN_INPUT12INPUT13 << 0) /**< Shifted mode INPUT12INPUT13 for ADC_SCANMASK */
#define ADC_SCANMASK_SCANINPUTEN_INPUT13 (_ADC_SCANMASK_SCANINPUTEN_INPUT13 << 0) /**< Shifted mode INPUT13 for ADC_SCANMASK */
-#define ADC_SCANMASK_SCANINPUTEN_INPUT14INPUT15 (_ADC_SCANMASK_SCANINPUTEN_INPUT14INPUT15 << 0) /**< Shifted mode INPUT14INPUT15 for ADC_SCANMASK */
+#define ADC_SCANMASK_SCANINPUTEN_INPUT13INPUT13NEGSEL (_ADC_SCANMASK_SCANINPUTEN_INPUT13INPUT13NEGSEL << 0) /**< Shifted mode INPUT13INPUT13NEGSEL for ADC_SCANMASK */
#define ADC_SCANMASK_SCANINPUTEN_INPUT14 (_ADC_SCANMASK_SCANINPUTEN_INPUT14 << 0) /**< Shifted mode INPUT14 for ADC_SCANMASK */
-#define ADC_SCANMASK_SCANINPUTEN_INPUT15INPUT15NEGSEL (_ADC_SCANMASK_SCANINPUTEN_INPUT15INPUT15NEGSEL << 0) /**< Shifted mode INPUT15INPUT15NEGSEL for ADC_SCANMASK */
+#define ADC_SCANMASK_SCANINPUTEN_INPUT14INPUT15 (_ADC_SCANMASK_SCANINPUTEN_INPUT14INPUT15 << 0) /**< Shifted mode INPUT14INPUT15 for ADC_SCANMASK */
#define ADC_SCANMASK_SCANINPUTEN_INPUT15 (_ADC_SCANMASK_SCANINPUTEN_INPUT15 << 0) /**< Shifted mode INPUT15 for ADC_SCANMASK */
-#define ADC_SCANMASK_SCANINPUTEN_INPUT16INPUT17 (_ADC_SCANMASK_SCANINPUTEN_INPUT16INPUT17 << 0) /**< Shifted mode INPUT16INPUT17 for ADC_SCANMASK */
+#define ADC_SCANMASK_SCANINPUTEN_INPUT15INPUT15NEGSEL (_ADC_SCANMASK_SCANINPUTEN_INPUT15INPUT15NEGSEL << 0) /**< Shifted mode INPUT15INPUT15NEGSEL for ADC_SCANMASK */
#define ADC_SCANMASK_SCANINPUTEN_INPUT16 (_ADC_SCANMASK_SCANINPUTEN_INPUT16 << 0) /**< Shifted mode INPUT16 for ADC_SCANMASK */
-#define ADC_SCANMASK_SCANINPUTEN_INPUT17INPUT18 (_ADC_SCANMASK_SCANINPUTEN_INPUT17INPUT18 << 0) /**< Shifted mode INPUT17INPUT18 for ADC_SCANMASK */
+#define ADC_SCANMASK_SCANINPUTEN_INPUT16INPUT17 (_ADC_SCANMASK_SCANINPUTEN_INPUT16INPUT17 << 0) /**< Shifted mode INPUT16INPUT17 for ADC_SCANMASK */
#define ADC_SCANMASK_SCANINPUTEN_INPUT17 (_ADC_SCANMASK_SCANINPUTEN_INPUT17 << 0) /**< Shifted mode INPUT17 for ADC_SCANMASK */
+#define ADC_SCANMASK_SCANINPUTEN_INPUT17INPUT18 (_ADC_SCANMASK_SCANINPUTEN_INPUT17INPUT18 << 0) /**< Shifted mode INPUT17INPUT18 for ADC_SCANMASK */
#define ADC_SCANMASK_SCANINPUTEN_INPUT18INPUT19 (_ADC_SCANMASK_SCANINPUTEN_INPUT18INPUT19 << 0) /**< Shifted mode INPUT18INPUT19 for ADC_SCANMASK */
#define ADC_SCANMASK_SCANINPUTEN_INPUT18 (_ADC_SCANMASK_SCANINPUTEN_INPUT18 << 0) /**< Shifted mode INPUT18 for ADC_SCANMASK */
#define ADC_SCANMASK_SCANINPUTEN_INPUT19 (_ADC_SCANMASK_SCANINPUTEN_INPUT19 << 0) /**< Shifted mode INPUT19 for ADC_SCANMASK */
#define ADC_SCANMASK_SCANINPUTEN_INPUT19INPUT20 (_ADC_SCANMASK_SCANINPUTEN_INPUT19INPUT20 << 0) /**< Shifted mode INPUT19INPUT20 for ADC_SCANMASK */
#define ADC_SCANMASK_SCANINPUTEN_INPUT20INPUT21 (_ADC_SCANMASK_SCANINPUTEN_INPUT20INPUT21 << 0) /**< Shifted mode INPUT20INPUT21 for ADC_SCANMASK */
#define ADC_SCANMASK_SCANINPUTEN_INPUT20 (_ADC_SCANMASK_SCANINPUTEN_INPUT20 << 0) /**< Shifted mode INPUT20 for ADC_SCANMASK */
-#define ADC_SCANMASK_SCANINPUTEN_INPUT21 (_ADC_SCANMASK_SCANINPUTEN_INPUT21 << 0) /**< Shifted mode INPUT21 for ADC_SCANMASK */
#define ADC_SCANMASK_SCANINPUTEN_INPUT21INPUT22 (_ADC_SCANMASK_SCANINPUTEN_INPUT21INPUT22 << 0) /**< Shifted mode INPUT21INPUT22 for ADC_SCANMASK */
+#define ADC_SCANMASK_SCANINPUTEN_INPUT21 (_ADC_SCANMASK_SCANINPUTEN_INPUT21 << 0) /**< Shifted mode INPUT21 for ADC_SCANMASK */
#define ADC_SCANMASK_SCANINPUTEN_INPUT22INPUT23 (_ADC_SCANMASK_SCANINPUTEN_INPUT22INPUT23 << 0) /**< Shifted mode INPUT22INPUT23 for ADC_SCANMASK */
#define ADC_SCANMASK_SCANINPUTEN_INPUT22 (_ADC_SCANMASK_SCANINPUTEN_INPUT22 << 0) /**< Shifted mode INPUT22 for ADC_SCANMASK */
-#define ADC_SCANMASK_SCANINPUTEN_INPUT23INPUT16 (_ADC_SCANMASK_SCANINPUTEN_INPUT23INPUT16 << 0) /**< Shifted mode INPUT23INPUT16 for ADC_SCANMASK */
#define ADC_SCANMASK_SCANINPUTEN_INPUT23 (_ADC_SCANMASK_SCANINPUTEN_INPUT23 << 0) /**< Shifted mode INPUT23 for ADC_SCANMASK */
-#define ADC_SCANMASK_SCANINPUTEN_INPUT24 (_ADC_SCANMASK_SCANINPUTEN_INPUT24 << 0) /**< Shifted mode INPUT24 for ADC_SCANMASK */
+#define ADC_SCANMASK_SCANINPUTEN_INPUT23INPUT16 (_ADC_SCANMASK_SCANINPUTEN_INPUT23INPUT16 << 0) /**< Shifted mode INPUT23INPUT16 for ADC_SCANMASK */
#define ADC_SCANMASK_SCANINPUTEN_INPUT24INPUT25 (_ADC_SCANMASK_SCANINPUTEN_INPUT24INPUT25 << 0) /**< Shifted mode INPUT24INPUT25 for ADC_SCANMASK */
-#define ADC_SCANMASK_SCANINPUTEN_INPUT25INPUT26 (_ADC_SCANMASK_SCANINPUTEN_INPUT25INPUT26 << 0) /**< Shifted mode INPUT25INPUT26 for ADC_SCANMASK */
+#define ADC_SCANMASK_SCANINPUTEN_INPUT24 (_ADC_SCANMASK_SCANINPUTEN_INPUT24 << 0) /**< Shifted mode INPUT24 for ADC_SCANMASK */
#define ADC_SCANMASK_SCANINPUTEN_INPUT25 (_ADC_SCANMASK_SCANINPUTEN_INPUT25 << 0) /**< Shifted mode INPUT25 for ADC_SCANMASK */
-#define ADC_SCANMASK_SCANINPUTEN_INPUT26 (_ADC_SCANMASK_SCANINPUTEN_INPUT26 << 0) /**< Shifted mode INPUT26 for ADC_SCANMASK */
+#define ADC_SCANMASK_SCANINPUTEN_INPUT25INPUT26 (_ADC_SCANMASK_SCANINPUTEN_INPUT25INPUT26 << 0) /**< Shifted mode INPUT25INPUT26 for ADC_SCANMASK */
#define ADC_SCANMASK_SCANINPUTEN_INPUT26INPUT27 (_ADC_SCANMASK_SCANINPUTEN_INPUT26INPUT27 << 0) /**< Shifted mode INPUT26INPUT27 for ADC_SCANMASK */
-#define ADC_SCANMASK_SCANINPUTEN_INPUT27INPUT28 (_ADC_SCANMASK_SCANINPUTEN_INPUT27INPUT28 << 0) /**< Shifted mode INPUT27INPUT28 for ADC_SCANMASK */
+#define ADC_SCANMASK_SCANINPUTEN_INPUT26 (_ADC_SCANMASK_SCANINPUTEN_INPUT26 << 0) /**< Shifted mode INPUT26 for ADC_SCANMASK */
#define ADC_SCANMASK_SCANINPUTEN_INPUT27 (_ADC_SCANMASK_SCANINPUTEN_INPUT27 << 0) /**< Shifted mode INPUT27 for ADC_SCANMASK */
-#define ADC_SCANMASK_SCANINPUTEN_INPUT28INPUT29 (_ADC_SCANMASK_SCANINPUTEN_INPUT28INPUT29 << 0) /**< Shifted mode INPUT28INPUT29 for ADC_SCANMASK */
+#define ADC_SCANMASK_SCANINPUTEN_INPUT27INPUT28 (_ADC_SCANMASK_SCANINPUTEN_INPUT27INPUT28 << 0) /**< Shifted mode INPUT27INPUT28 for ADC_SCANMASK */
#define ADC_SCANMASK_SCANINPUTEN_INPUT28 (_ADC_SCANMASK_SCANINPUTEN_INPUT28 << 0) /**< Shifted mode INPUT28 for ADC_SCANMASK */
+#define ADC_SCANMASK_SCANINPUTEN_INPUT28INPUT29 (_ADC_SCANMASK_SCANINPUTEN_INPUT28INPUT29 << 0) /**< Shifted mode INPUT28INPUT29 for ADC_SCANMASK */
#define ADC_SCANMASK_SCANINPUTEN_INPUT29 (_ADC_SCANMASK_SCANINPUTEN_INPUT29 << 0) /**< Shifted mode INPUT29 for ADC_SCANMASK */
#define ADC_SCANMASK_SCANINPUTEN_INPUT29INPUT30 (_ADC_SCANMASK_SCANINPUTEN_INPUT29INPUT30 << 0) /**< Shifted mode INPUT29INPUT30 for ADC_SCANMASK */
-#define ADC_SCANMASK_SCANINPUTEN_INPUT30 (_ADC_SCANMASK_SCANINPUTEN_INPUT30 << 0) /**< Shifted mode INPUT30 for ADC_SCANMASK */
#define ADC_SCANMASK_SCANINPUTEN_INPUT30INPUT31 (_ADC_SCANMASK_SCANINPUTEN_INPUT30INPUT31 << 0) /**< Shifted mode INPUT30INPUT31 for ADC_SCANMASK */
+#define ADC_SCANMASK_SCANINPUTEN_INPUT30 (_ADC_SCANMASK_SCANINPUTEN_INPUT30 << 0) /**< Shifted mode INPUT30 for ADC_SCANMASK */
#define ADC_SCANMASK_SCANINPUTEN_INPUT31INPUT24 (_ADC_SCANMASK_SCANINPUTEN_INPUT31INPUT24 << 0) /**< Shifted mode INPUT31INPUT24 for ADC_SCANMASK */
#define ADC_SCANMASK_SCANINPUTEN_INPUT31 (_ADC_SCANMASK_SCANINPUTEN_INPUT31 << 0) /**< Shifted mode INPUT31 for ADC_SCANMASK */
diff --git a/cpu/efm32/families/efm32pg12b/include/vendor/efm32pg12b_af_pins.h b/cpu/efm32/families/efm32pg12b/include/vendor/efm32pg12b_af_pins.h
index 98f58eed71..1bd1ea53a1 100644
--- a/cpu/efm32/families/efm32pg12b/include/vendor/efm32pg12b_af_pins.h
+++ b/cpu/efm32/families/efm32pg12b/include/vendor/efm32pg12b_af_pins.h
@@ -1,10 +1,9 @@
/***************************************************************************//**
* @file
* @brief EFM32PG12B_AF_PINS register and bit field definitions
- * @version 5.8.3
*******************************************************************************
* # License
- * Copyright 2019 Silicon Laboratories Inc. www.silabs.com
+ * Copyright 2020 Silicon Laboratories Inc. www.silabs.com
*******************************************************************************
*
* SPDX-License-Identifier: Zlib
diff --git a/cpu/efm32/families/efm32pg12b/include/vendor/efm32pg12b_af_ports.h b/cpu/efm32/families/efm32pg12b/include/vendor/efm32pg12b_af_ports.h
index 26e7c0ef88..f3928f044b 100644
--- a/cpu/efm32/families/efm32pg12b/include/vendor/efm32pg12b_af_ports.h
+++ b/cpu/efm32/families/efm32pg12b/include/vendor/efm32pg12b_af_ports.h
@@ -1,10 +1,9 @@
/***************************************************************************//**
* @file
* @brief EFM32PG12B_AF_PORTS register and bit field definitions
- * @version 5.8.3
*******************************************************************************
* # License
- * Copyright 2019 Silicon Laboratories Inc. www.silabs.com
+ * Copyright 2020 Silicon Laboratories Inc. www.silabs.com
*******************************************************************************
*
* SPDX-License-Identifier: Zlib
diff --git a/cpu/efm32/families/efm32pg12b/include/vendor/efm32pg12b_cmu.h b/cpu/efm32/families/efm32pg12b/include/vendor/efm32pg12b_cmu.h
index b7ba43c26c..d7d3b2d35c 100644
--- a/cpu/efm32/families/efm32pg12b/include/vendor/efm32pg12b_cmu.h
+++ b/cpu/efm32/families/efm32pg12b/include/vendor/efm32pg12b_cmu.h
@@ -1,10 +1,9 @@
/***************************************************************************//**
* @file
* @brief EFM32PG12B_CMU register and bit field definitions
- * @version 5.8.3
*******************************************************************************
* # License
- * Copyright 2019 Silicon Laboratories Inc. www.silabs.com
+ * Copyright 2020 Silicon Laboratories Inc. www.silabs.com
*******************************************************************************
*
* SPDX-License-Identifier: Zlib
@@ -2018,13 +2017,13 @@ typedef struct {
#define _CMU_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for CMU_LOCKKEY */
#define _CMU_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for CMU_LOCKKEY */
#define _CMU_LOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LOCK */
-#define _CMU_LOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for CMU_LOCK */
#define _CMU_LOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for CMU_LOCK */
+#define _CMU_LOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for CMU_LOCK */
#define _CMU_LOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for CMU_LOCK */
#define _CMU_LOCK_LOCKKEY_UNLOCK 0x0000580EUL /**< Mode UNLOCK for CMU_LOCK */
#define CMU_LOCK_LOCKKEY_DEFAULT (_CMU_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LOCK */
-#define CMU_LOCK_LOCKKEY_LOCK (_CMU_LOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for CMU_LOCK */
#define CMU_LOCK_LOCKKEY_UNLOCKED (_CMU_LOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for CMU_LOCK */
+#define CMU_LOCK_LOCKKEY_LOCK (_CMU_LOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for CMU_LOCK */
#define CMU_LOCK_LOCKKEY_LOCKED (_CMU_LOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for CMU_LOCK */
#define CMU_LOCK_LOCKKEY_UNLOCK (_CMU_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for CMU_LOCK */
diff --git a/cpu/efm32/families/efm32pg12b/include/vendor/efm32pg12b_cryotimer.h b/cpu/efm32/families/efm32pg12b/include/vendor/efm32pg12b_cryotimer.h
index 0a73c46a41..6840884f97 100644
--- a/cpu/efm32/families/efm32pg12b/include/vendor/efm32pg12b_cryotimer.h
+++ b/cpu/efm32/families/efm32pg12b/include/vendor/efm32pg12b_cryotimer.h
@@ -1,10 +1,9 @@
/***************************************************************************//**
* @file
* @brief EFM32PG12B_CRYOTIMER register and bit field definitions
- * @version 5.8.3
*******************************************************************************
* # License
- * Copyright 2019 Silicon Laboratories Inc. www.silabs.com
+ * Copyright 2020 Silicon Laboratories Inc. www.silabs.com
*******************************************************************************
*
* SPDX-License-Identifier: Zlib
diff --git a/cpu/efm32/families/efm32pg12b/include/vendor/efm32pg12b_crypto.h b/cpu/efm32/families/efm32pg12b/include/vendor/efm32pg12b_crypto.h
index 655ad14b6a..40d7f2d9cd 100644
--- a/cpu/efm32/families/efm32pg12b/include/vendor/efm32pg12b_crypto.h
+++ b/cpu/efm32/families/efm32pg12b/include/vendor/efm32pg12b_crypto.h
@@ -1,10 +1,9 @@
/***************************************************************************//**
* @file
* @brief EFM32PG12B_CRYPTO register and bit field definitions
- * @version 5.8.3
*******************************************************************************
* # License
- * Copyright 2019 Silicon Laboratories Inc. www.silabs.com
+ * Copyright 2020 Silicon Laboratories Inc. www.silabs.com
*******************************************************************************
*
* SPDX-License-Identifier: Zlib
diff --git a/cpu/efm32/families/efm32pg12b/include/vendor/efm32pg12b_csen.h b/cpu/efm32/families/efm32pg12b/include/vendor/efm32pg12b_csen.h
index 77f22c9d24..dc8fd37cb6 100644
--- a/cpu/efm32/families/efm32pg12b/include/vendor/efm32pg12b_csen.h
+++ b/cpu/efm32/families/efm32pg12b/include/vendor/efm32pg12b_csen.h
@@ -1,10 +1,9 @@
/***************************************************************************//**
* @file
* @brief EFM32PG12B_CSEN register and bit field definitions
- * @version 5.8.3
*******************************************************************************
* # License
- * Copyright 2019 Silicon Laboratories Inc. www.silabs.com
+ * Copyright 2020 Silicon Laboratories Inc. www.silabs.com
*******************************************************************************
*
* SPDX-License-Identifier: Zlib
diff --git a/cpu/efm32/families/efm32pg12b/include/vendor/efm32pg12b_devinfo.h b/cpu/efm32/families/efm32pg12b/include/vendor/efm32pg12b_devinfo.h
index 644b2fa8fd..ff8a701269 100644
--- a/cpu/efm32/families/efm32pg12b/include/vendor/efm32pg12b_devinfo.h
+++ b/cpu/efm32/families/efm32pg12b/include/vendor/efm32pg12b_devinfo.h
@@ -1,10 +1,9 @@
/***************************************************************************//**
* @file
* @brief EFM32PG12B_DEVINFO register and bit field definitions
- * @version 5.8.3
*******************************************************************************
* # License
- * Copyright 2019 Silicon Laboratories Inc. www.silabs.com
+ * Copyright 2020 Silicon Laboratories Inc. www.silabs.com
*******************************************************************************
*
* SPDX-License-Identifier: Zlib
@@ -245,6 +244,8 @@ typedef struct {
#define _DEVINFO_PART_DEVICE_FAMILY_EFR32BG13B 0x0000002CUL /**< Mode EFR32BG13B for DEVINFO_PART */
#define _DEVINFO_PART_DEVICE_FAMILY_EFR32BG13V 0x0000002DUL /**< Mode EFR32BG13V for DEVINFO_PART */
#define _DEVINFO_PART_DEVICE_FAMILY_EFR32ZG13P 0x0000002EUL /**< Mode EFR32ZG13P for DEVINFO_PART */
+#define _DEVINFO_PART_DEVICE_FAMILY_EFR32ZG13L 0x0000002FUL /**< Mode EFR32ZG13L for DEVINFO_PART */
+#define _DEVINFO_PART_DEVICE_FAMILY_EFR32ZG13S 0x00000030UL /**< Mode EFR32ZG13S for DEVINFO_PART */
#define _DEVINFO_PART_DEVICE_FAMILY_EFR32FG13P 0x00000031UL /**< Mode EFR32FG13P for DEVINFO_PART */
#define _DEVINFO_PART_DEVICE_FAMILY_EFR32FG13B 0x00000032UL /**< Mode EFR32FG13B for DEVINFO_PART */
#define _DEVINFO_PART_DEVICE_FAMILY_EFR32FG13V 0x00000033UL /**< Mode EFR32FG13V for DEVINFO_PART */
@@ -262,16 +263,16 @@ typedef struct {
#define _DEVINFO_PART_DEVICE_FAMILY_G 0x00000047UL /**< Mode G for DEVINFO_PART */
#define _DEVINFO_PART_DEVICE_FAMILY_EFM32GG 0x00000048UL /**< Mode EFM32GG for DEVINFO_PART */
#define _DEVINFO_PART_DEVICE_FAMILY_GG 0x00000048UL /**< Mode GG for DEVINFO_PART */
-#define _DEVINFO_PART_DEVICE_FAMILY_TG 0x00000049UL /**< Mode TG for DEVINFO_PART */
#define _DEVINFO_PART_DEVICE_FAMILY_EFM32TG 0x00000049UL /**< Mode EFM32TG for DEVINFO_PART */
+#define _DEVINFO_PART_DEVICE_FAMILY_TG 0x00000049UL /**< Mode TG for DEVINFO_PART */
#define _DEVINFO_PART_DEVICE_FAMILY_EFM32LG 0x0000004AUL /**< Mode EFM32LG for DEVINFO_PART */
#define _DEVINFO_PART_DEVICE_FAMILY_LG 0x0000004AUL /**< Mode LG for DEVINFO_PART */
-#define _DEVINFO_PART_DEVICE_FAMILY_EFM32WG 0x0000004BUL /**< Mode EFM32WG for DEVINFO_PART */
#define _DEVINFO_PART_DEVICE_FAMILY_WG 0x0000004BUL /**< Mode WG for DEVINFO_PART */
+#define _DEVINFO_PART_DEVICE_FAMILY_EFM32WG 0x0000004BUL /**< Mode EFM32WG for DEVINFO_PART */
#define _DEVINFO_PART_DEVICE_FAMILY_ZG 0x0000004CUL /**< Mode ZG for DEVINFO_PART */
#define _DEVINFO_PART_DEVICE_FAMILY_EFM32ZG 0x0000004CUL /**< Mode EFM32ZG for DEVINFO_PART */
-#define _DEVINFO_PART_DEVICE_FAMILY_HG 0x0000004DUL /**< Mode HG for DEVINFO_PART */
#define _DEVINFO_PART_DEVICE_FAMILY_EFM32HG 0x0000004DUL /**< Mode EFM32HG for DEVINFO_PART */
+#define _DEVINFO_PART_DEVICE_FAMILY_HG 0x0000004DUL /**< Mode HG for DEVINFO_PART */
#define _DEVINFO_PART_DEVICE_FAMILY_EFM32PG1B 0x00000051UL /**< Mode EFM32PG1B for DEVINFO_PART */
#define _DEVINFO_PART_DEVICE_FAMILY_EFM32JG1B 0x00000053UL /**< Mode EFM32JG1B for DEVINFO_PART */
#define _DEVINFO_PART_DEVICE_FAMILY_EFM32PG12B 0x00000055UL /**< Mode EFM32PG12B for DEVINFO_PART */
@@ -307,6 +308,8 @@ typedef struct {
#define DEVINFO_PART_DEVICE_FAMILY_EFR32BG13B (_DEVINFO_PART_DEVICE_FAMILY_EFR32BG13B << 16) /**< Shifted mode EFR32BG13B for DEVINFO_PART */
#define DEVINFO_PART_DEVICE_FAMILY_EFR32BG13V (_DEVINFO_PART_DEVICE_FAMILY_EFR32BG13V << 16) /**< Shifted mode EFR32BG13V for DEVINFO_PART */
#define DEVINFO_PART_DEVICE_FAMILY_EFR32ZG13P (_DEVINFO_PART_DEVICE_FAMILY_EFR32ZG13P << 16) /**< Shifted mode EFR32ZG13P for DEVINFO_PART */
+#define DEVINFO_PART_DEVICE_FAMILY_EFR32ZG13L (_DEVINFO_PART_DEVICE_FAMILY_EFR32ZG13L << 16) /**< Shifted mode EFR32ZG13L for DEVINFO_PART */
+#define DEVINFO_PART_DEVICE_FAMILY_EFR32ZG13S (_DEVINFO_PART_DEVICE_FAMILY_EFR32ZG13S << 16) /**< Shifted mode EFR32ZG13S for DEVINFO_PART */
#define DEVINFO_PART_DEVICE_FAMILY_EFR32FG13P (_DEVINFO_PART_DEVICE_FAMILY_EFR32FG13P << 16) /**< Shifted mode EFR32FG13P for DEVINFO_PART */
#define DEVINFO_PART_DEVICE_FAMILY_EFR32FG13B (_DEVINFO_PART_DEVICE_FAMILY_EFR32FG13B << 16) /**< Shifted mode EFR32FG13B for DEVINFO_PART */
#define DEVINFO_PART_DEVICE_FAMILY_EFR32FG13V (_DEVINFO_PART_DEVICE_FAMILY_EFR32FG13V << 16) /**< Shifted mode EFR32FG13V for DEVINFO_PART */
@@ -324,16 +327,16 @@ typedef struct {
#define DEVINFO_PART_DEVICE_FAMILY_G (_DEVINFO_PART_DEVICE_FAMILY_G << 16) /**< Shifted mode G for DEVINFO_PART */
#define DEVINFO_PART_DEVICE_FAMILY_EFM32GG (_DEVINFO_PART_DEVICE_FAMILY_EFM32GG << 16) /**< Shifted mode EFM32GG for DEVINFO_PART */
#define DEVINFO_PART_DEVICE_FAMILY_GG (_DEVINFO_PART_DEVICE_FAMILY_GG << 16) /**< Shifted mode GG for DEVINFO_PART */
-#define DEVINFO_PART_DEVICE_FAMILY_TG (_DEVINFO_PART_DEVICE_FAMILY_TG << 16) /**< Shifted mode TG for DEVINFO_PART */
#define DEVINFO_PART_DEVICE_FAMILY_EFM32TG (_DEVINFO_PART_DEVICE_FAMILY_EFM32TG << 16) /**< Shifted mode EFM32TG for DEVINFO_PART */
+#define DEVINFO_PART_DEVICE_FAMILY_TG (_DEVINFO_PART_DEVICE_FAMILY_TG << 16) /**< Shifted mode TG for DEVINFO_PART */
#define DEVINFO_PART_DEVICE_FAMILY_EFM32LG (_DEVINFO_PART_DEVICE_FAMILY_EFM32LG << 16) /**< Shifted mode EFM32LG for DEVINFO_PART */
#define DEVINFO_PART_DEVICE_FAMILY_LG (_DEVINFO_PART_DEVICE_FAMILY_LG << 16) /**< Shifted mode LG for DEVINFO_PART */
-#define DEVINFO_PART_DEVICE_FAMILY_EFM32WG (_DEVINFO_PART_DEVICE_FAMILY_EFM32WG << 16) /**< Shifted mode EFM32WG for DEVINFO_PART */
#define DEVINFO_PART_DEVICE_FAMILY_WG (_DEVINFO_PART_DEVICE_FAMILY_WG << 16) /**< Shifted mode WG for DEVINFO_PART */
+#define DEVINFO_PART_DEVICE_FAMILY_EFM32WG (_DEVINFO_PART_DEVICE_FAMILY_EFM32WG << 16) /**< Shifted mode EFM32WG for DEVINFO_PART */
#define DEVINFO_PART_DEVICE_FAMILY_ZG (_DEVINFO_PART_DEVICE_FAMILY_ZG << 16) /**< Shifted mode ZG for DEVINFO_PART */
#define DEVINFO_PART_DEVICE_FAMILY_EFM32ZG (_DEVINFO_PART_DEVICE_FAMILY_EFM32ZG << 16) /**< Shifted mode EFM32ZG for DEVINFO_PART */
-#define DEVINFO_PART_DEVICE_FAMILY_HG (_DEVINFO_PART_DEVICE_FAMILY_HG << 16) /**< Shifted mode HG for DEVINFO_PART */
#define DEVINFO_PART_DEVICE_FAMILY_EFM32HG (_DEVINFO_PART_DEVICE_FAMILY_EFM32HG << 16) /**< Shifted mode EFM32HG for DEVINFO_PART */
+#define DEVINFO_PART_DEVICE_FAMILY_HG (_DEVINFO_PART_DEVICE_FAMILY_HG << 16) /**< Shifted mode HG for DEVINFO_PART */
#define DEVINFO_PART_DEVICE_FAMILY_EFM32PG1B (_DEVINFO_PART_DEVICE_FAMILY_EFM32PG1B << 16) /**< Shifted mode EFM32PG1B for DEVINFO_PART */
#define DEVINFO_PART_DEVICE_FAMILY_EFM32JG1B (_DEVINFO_PART_DEVICE_FAMILY_EFM32JG1B << 16) /**< Shifted mode EFM32JG1B for DEVINFO_PART */
#define DEVINFO_PART_DEVICE_FAMILY_EFM32PG12B (_DEVINFO_PART_DEVICE_FAMILY_EFM32PG12B << 16) /**< Shifted mode EFM32PG12B for DEVINFO_PART */
diff --git a/cpu/efm32/families/efm32pg12b/include/vendor/efm32pg12b_dma_descriptor.h b/cpu/efm32/families/efm32pg12b/include/vendor/efm32pg12b_dma_descriptor.h
index 4dbb8fe194..d39015fd57 100644
--- a/cpu/efm32/families/efm32pg12b/include/vendor/efm32pg12b_dma_descriptor.h
+++ b/cpu/efm32/families/efm32pg12b/include/vendor/efm32pg12b_dma_descriptor.h
@@ -1,10 +1,9 @@
/***************************************************************************//**
* @file
* @brief EFM32PG12B_DMA_DESCRIPTOR register and bit field definitions
- * @version 5.8.3
*******************************************************************************
* # License
- * Copyright 2019 Silicon Laboratories Inc. www.silabs.com
+ * Copyright 2020 Silicon Laboratories Inc. www.silabs.com
*******************************************************************************
*
* SPDX-License-Identifier: Zlib
diff --git a/cpu/efm32/families/efm32pg12b/include/vendor/efm32pg12b_dmareq.h b/cpu/efm32/families/efm32pg12b/include/vendor/efm32pg12b_dmareq.h
index 4c90eef020..c28204020c 100644
--- a/cpu/efm32/families/efm32pg12b/include/vendor/efm32pg12b_dmareq.h
+++ b/cpu/efm32/families/efm32pg12b/include/vendor/efm32pg12b_dmareq.h
@@ -1,10 +1,9 @@
/***************************************************************************//**
* @file
* @brief EFM32PG12B_DMAREQ register and bit field definitions
- * @version 5.8.3
*******************************************************************************
* # License
- * Copyright 2019 Silicon Laboratories Inc. www.silabs.com
+ * Copyright 2020 Silicon Laboratories Inc. www.silabs.com
*******************************************************************************
*
* SPDX-License-Identifier: Zlib
diff --git a/cpu/efm32/families/efm32pg12b/include/vendor/efm32pg12b_emu.h b/cpu/efm32/families/efm32pg12b/include/vendor/efm32pg12b_emu.h
index 5bda130578..0a29059a78 100644
--- a/cpu/efm32/families/efm32pg12b/include/vendor/efm32pg12b_emu.h
+++ b/cpu/efm32/families/efm32pg12b/include/vendor/efm32pg12b_emu.h
@@ -1,10 +1,9 @@
/***************************************************************************//**
* @file
* @brief EFM32PG12B_EMU register and bit field definitions
- * @version 5.8.3
*******************************************************************************
* # License
- * Copyright 2019 Silicon Laboratories Inc. www.silabs.com
+ * Copyright 2020 Silicon Laboratories Inc. www.silabs.com
*******************************************************************************
*
* SPDX-License-Identifier: Zlib
@@ -226,13 +225,13 @@ typedef struct {
#define _EMU_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for EMU_LOCKKEY */
#define _EMU_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for EMU_LOCKKEY */
#define _EMU_LOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_LOCK */
-#define _EMU_LOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for EMU_LOCK */
#define _EMU_LOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for EMU_LOCK */
+#define _EMU_LOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for EMU_LOCK */
#define _EMU_LOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for EMU_LOCK */
#define _EMU_LOCK_LOCKKEY_UNLOCK 0x0000ADE8UL /**< Mode UNLOCK for EMU_LOCK */
#define EMU_LOCK_LOCKKEY_DEFAULT (_EMU_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_LOCK */
-#define EMU_LOCK_LOCKKEY_LOCK (_EMU_LOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for EMU_LOCK */
#define EMU_LOCK_LOCKKEY_UNLOCKED (_EMU_LOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for EMU_LOCK */
+#define EMU_LOCK_LOCKKEY_LOCK (_EMU_LOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for EMU_LOCK */
#define EMU_LOCK_LOCKKEY_LOCKED (_EMU_LOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for EMU_LOCK */
#define EMU_LOCK_LOCKKEY_UNLOCK (_EMU_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for EMU_LOCK */
@@ -762,13 +761,13 @@ typedef struct {
#define _EMU_PWRLOCK_LOCKKEY_SHIFT 0 /**< Shift value for EMU_LOCKKEY */
#define _EMU_PWRLOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for EMU_LOCKKEY */
#define _EMU_PWRLOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_PWRLOCK */
-#define _EMU_PWRLOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for EMU_PWRLOCK */
#define _EMU_PWRLOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for EMU_PWRLOCK */
+#define _EMU_PWRLOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for EMU_PWRLOCK */
#define _EMU_PWRLOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for EMU_PWRLOCK */
#define _EMU_PWRLOCK_LOCKKEY_UNLOCK 0x0000ADE8UL /**< Mode UNLOCK for EMU_PWRLOCK */
#define EMU_PWRLOCK_LOCKKEY_DEFAULT (_EMU_PWRLOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_PWRLOCK */
-#define EMU_PWRLOCK_LOCKKEY_LOCK (_EMU_PWRLOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for EMU_PWRLOCK */
#define EMU_PWRLOCK_LOCKKEY_UNLOCKED (_EMU_PWRLOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for EMU_PWRLOCK */
+#define EMU_PWRLOCK_LOCKKEY_LOCK (_EMU_PWRLOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for EMU_PWRLOCK */
#define EMU_PWRLOCK_LOCKKEY_LOCKED (_EMU_PWRLOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for EMU_PWRLOCK */
#define EMU_PWRLOCK_LOCKKEY_UNLOCK (_EMU_PWRLOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for EMU_PWRLOCK */
diff --git a/cpu/efm32/families/efm32pg12b/include/vendor/efm32pg12b_etm.h b/cpu/efm32/families/efm32pg12b/include/vendor/efm32pg12b_etm.h
index ff63788a4b..1407014880 100644
--- a/cpu/efm32/families/efm32pg12b/include/vendor/efm32pg12b_etm.h
+++ b/cpu/efm32/families/efm32pg12b/include/vendor/efm32pg12b_etm.h
@@ -1,10 +1,9 @@
/***************************************************************************//**
* @file
* @brief EFM32PG12B_ETM register and bit field definitions
- * @version 5.8.3
*******************************************************************************
* # License
- * Copyright 2019 Silicon Laboratories Inc. www.silabs.com
+ * Copyright 2020 Silicon Laboratories Inc. www.silabs.com
*******************************************************************************
*
* SPDX-License-Identifier: Zlib
diff --git a/cpu/efm32/families/efm32pg12b/include/vendor/efm32pg12b_fpueh.h b/cpu/efm32/families/efm32pg12b/include/vendor/efm32pg12b_fpueh.h
index 7e384a7742..2d2d88b81d 100644
--- a/cpu/efm32/families/efm32pg12b/include/vendor/efm32pg12b_fpueh.h
+++ b/cpu/efm32/families/efm32pg12b/include/vendor/efm32pg12b_fpueh.h
@@ -1,10 +1,9 @@
/***************************************************************************//**
* @file
* @brief EFM32PG12B_FPUEH register and bit field definitions
- * @version 5.8.3
*******************************************************************************
* # License
- * Copyright 2019 Silicon Laboratories Inc. www.silabs.com
+ * Copyright 2020 Silicon Laboratories Inc. www.silabs.com
*******************************************************************************
*
* SPDX-License-Identifier: Zlib
diff --git a/cpu/efm32/families/efm32pg12b/include/vendor/efm32pg12b_gpcrc.h b/cpu/efm32/families/efm32pg12b/include/vendor/efm32pg12b_gpcrc.h
index 29e08600d2..41d256e486 100644
--- a/cpu/efm32/families/efm32pg12b/include/vendor/efm32pg12b_gpcrc.h
+++ b/cpu/efm32/families/efm32pg12b/include/vendor/efm32pg12b_gpcrc.h
@@ -1,10 +1,9 @@
/***************************************************************************//**
* @file
* @brief EFM32PG12B_GPCRC register and bit field definitions
- * @version 5.8.3
*******************************************************************************
* # License
- * Copyright 2019 Silicon Laboratories Inc. www.silabs.com
+ * Copyright 2020 Silicon Laboratories Inc. www.silabs.com
*******************************************************************************
*
* SPDX-License-Identifier: Zlib
diff --git a/cpu/efm32/families/efm32pg12b/include/vendor/efm32pg12b_gpio.h b/cpu/efm32/families/efm32pg12b/include/vendor/efm32pg12b_gpio.h
index 5828b3b723..57b85794aa 100644
--- a/cpu/efm32/families/efm32pg12b/include/vendor/efm32pg12b_gpio.h
+++ b/cpu/efm32/families/efm32pg12b/include/vendor/efm32pg12b_gpio.h
@@ -1,10 +1,9 @@
/***************************************************************************//**
* @file
* @brief EFM32PG12B_GPIO register and bit field definitions
- * @version 5.8.3
*******************************************************************************
* # License
- * Copyright 2019 Silicon Laboratories Inc. www.silabs.com
+ * Copyright 2020 Silicon Laboratories Inc. www.silabs.com
*******************************************************************************
*
* SPDX-License-Identifier: Zlib
@@ -1536,13 +1535,13 @@ typedef struct {
#define _GPIO_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for GPIO_LOCKKEY */
#define _GPIO_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for GPIO_LOCKKEY */
#define _GPIO_LOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_LOCK */
-#define _GPIO_LOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for GPIO_LOCK */
#define _GPIO_LOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for GPIO_LOCK */
+#define _GPIO_LOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for GPIO_LOCK */
#define _GPIO_LOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for GPIO_LOCK */
#define _GPIO_LOCK_LOCKKEY_UNLOCK 0x0000A534UL /**< Mode UNLOCK for GPIO_LOCK */
#define GPIO_LOCK_LOCKKEY_DEFAULT (_GPIO_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_LOCK */
-#define GPIO_LOCK_LOCKKEY_LOCK (_GPIO_LOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for GPIO_LOCK */
#define GPIO_LOCK_LOCKKEY_UNLOCKED (_GPIO_LOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for GPIO_LOCK */
+#define GPIO_LOCK_LOCKKEY_LOCK (_GPIO_LOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for GPIO_LOCK */
#define GPIO_LOCK_LOCKKEY_LOCKED (_GPIO_LOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for GPIO_LOCK */
#define GPIO_LOCK_LOCKKEY_UNLOCK (_GPIO_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for GPIO_LOCK */
diff --git a/cpu/efm32/families/efm32pg12b/include/vendor/efm32pg12b_gpio_p.h b/cpu/efm32/families/efm32pg12b/include/vendor/efm32pg12b_gpio_p.h
index 74ae321ac7..61e9a44f15 100644
--- a/cpu/efm32/families/efm32pg12b/include/vendor/efm32pg12b_gpio_p.h
+++ b/cpu/efm32/families/efm32pg12b/include/vendor/efm32pg12b_gpio_p.h
@@ -1,10 +1,9 @@
/***************************************************************************//**
* @file
* @brief EFM32PG12B_GPIO_P register and bit field definitions
- * @version 5.8.3
*******************************************************************************
* # License
- * Copyright 2019 Silicon Laboratories Inc. www.silabs.com
+ * Copyright 2020 Silicon Laboratories Inc. www.silabs.com
*******************************************************************************
*
* SPDX-License-Identifier: Zlib
diff --git a/cpu/efm32/families/efm32pg12b/include/vendor/efm32pg12b_i2c.h b/cpu/efm32/families/efm32pg12b/include/vendor/efm32pg12b_i2c.h
index 796be1544b..93cdf710e3 100644
--- a/cpu/efm32/families/efm32pg12b/include/vendor/efm32pg12b_i2c.h
+++ b/cpu/efm32/families/efm32pg12b/include/vendor/efm32pg12b_i2c.h
@@ -1,10 +1,9 @@
/***************************************************************************//**
* @file
* @brief EFM32PG12B_I2C register and bit field definitions
- * @version 5.8.3
*******************************************************************************
* # License
- * Copyright 2019 Silicon Laboratories Inc. www.silabs.com
+ * Copyright 2020 Silicon Laboratories Inc. www.silabs.com
*******************************************************************************
*
* SPDX-License-Identifier: Zlib
diff --git a/cpu/efm32/families/efm32pg12b/include/vendor/efm32pg12b_idac.h b/cpu/efm32/families/efm32pg12b/include/vendor/efm32pg12b_idac.h
index ae727657b6..d0db33ddef 100644
--- a/cpu/efm32/families/efm32pg12b/include/vendor/efm32pg12b_idac.h
+++ b/cpu/efm32/families/efm32pg12b/include/vendor/efm32pg12b_idac.h
@@ -1,10 +1,9 @@
/***************************************************************************//**
* @file
* @brief EFM32PG12B_IDAC register and bit field definitions
- * @version 5.8.3
*******************************************************************************
* # License
- * Copyright 2019 Silicon Laboratories Inc. www.silabs.com
+ * Copyright 2020 Silicon Laboratories Inc. www.silabs.com
*******************************************************************************
*
* SPDX-License-Identifier: Zlib
diff --git a/cpu/efm32/families/efm32pg12b/include/vendor/efm32pg12b_ldma.h b/cpu/efm32/families/efm32pg12b/include/vendor/efm32pg12b_ldma.h
index 32d7ff7007..4ba7f390be 100644
--- a/cpu/efm32/families/efm32pg12b/include/vendor/efm32pg12b_ldma.h
+++ b/cpu/efm32/families/efm32pg12b/include/vendor/efm32pg12b_ldma.h
@@ -1,10 +1,9 @@
/***************************************************************************//**
* @file
* @brief EFM32PG12B_LDMA register and bit field definitions
- * @version 5.8.3
*******************************************************************************
* # License
- * Copyright 2019 Silicon Laboratories Inc. www.silabs.com
+ * Copyright 2020 Silicon Laboratories Inc. www.silabs.com
*******************************************************************************
*
* SPDX-License-Identifier: Zlib
diff --git a/cpu/efm32/families/efm32pg12b/include/vendor/efm32pg12b_ldma_ch.h b/cpu/efm32/families/efm32pg12b/include/vendor/efm32pg12b_ldma_ch.h
index 81e2c28f38..d0baf6af49 100644
--- a/cpu/efm32/families/efm32pg12b/include/vendor/efm32pg12b_ldma_ch.h
+++ b/cpu/efm32/families/efm32pg12b/include/vendor/efm32pg12b_ldma_ch.h
@@ -1,10 +1,9 @@
/***************************************************************************//**
* @file
* @brief EFM32PG12B_LDMA_CH register and bit field definitions
- * @version 5.8.3
*******************************************************************************
* # License
- * Copyright 2019 Silicon Laboratories Inc. www.silabs.com
+ * Copyright 2020 Silicon Laboratories Inc. www.silabs.com
*******************************************************************************
*
* SPDX-License-Identifier: Zlib
diff --git a/cpu/efm32/families/efm32pg12b/include/vendor/efm32pg12b_lesense.h b/cpu/efm32/families/efm32pg12b/include/vendor/efm32pg12b_lesense.h
index e7b26c1a83..a809b7a560 100644
--- a/cpu/efm32/families/efm32pg12b/include/vendor/efm32pg12b_lesense.h
+++ b/cpu/efm32/families/efm32pg12b/include/vendor/efm32pg12b_lesense.h
@@ -1,10 +1,9 @@
/***************************************************************************//**
* @file
* @brief EFM32PG12B_LESENSE register and bit field definitions
- * @version 5.8.3
*******************************************************************************
* # License
- * Copyright 2019 Silicon Laboratories Inc. www.silabs.com
+ * Copyright 2020 Silicon Laboratories Inc. www.silabs.com
*******************************************************************************
*
* SPDX-License-Identifier: Zlib
@@ -1657,27 +1656,27 @@ typedef struct {
#define _LESENSE_ST_TCONFA_PRSACT_MASK 0x70000UL /**< Bit mask for LESENSE_PRSACT */
#define _LESENSE_ST_TCONFA_PRSACT_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_ST_TCONFA */
#define _LESENSE_ST_TCONFA_PRSACT_NONE 0x00000000UL /**< Mode NONE for LESENSE_ST_TCONFA */
-#define _LESENSE_ST_TCONFA_PRSACT_UP 0x00000001UL /**< Mode UP for LESENSE_ST_TCONFA */
#define _LESENSE_ST_TCONFA_PRSACT_PRS0 0x00000001UL /**< Mode PRS0 for LESENSE_ST_TCONFA */
-#define _LESENSE_ST_TCONFA_PRSACT_PRS1 0x00000002UL /**< Mode PRS1 for LESENSE_ST_TCONFA */
+#define _LESENSE_ST_TCONFA_PRSACT_UP 0x00000001UL /**< Mode UP for LESENSE_ST_TCONFA */
#define _LESENSE_ST_TCONFA_PRSACT_DOWN 0x00000002UL /**< Mode DOWN for LESENSE_ST_TCONFA */
+#define _LESENSE_ST_TCONFA_PRSACT_PRS1 0x00000002UL /**< Mode PRS1 for LESENSE_ST_TCONFA */
#define _LESENSE_ST_TCONFA_PRSACT_PRS01 0x00000003UL /**< Mode PRS01 for LESENSE_ST_TCONFA */
#define _LESENSE_ST_TCONFA_PRSACT_PRS2 0x00000004UL /**< Mode PRS2 for LESENSE_ST_TCONFA */
-#define _LESENSE_ST_TCONFA_PRSACT_PRS02 0x00000005UL /**< Mode PRS02 for LESENSE_ST_TCONFA */
#define _LESENSE_ST_TCONFA_PRSACT_UPANDPRS2 0x00000005UL /**< Mode UPANDPRS2 for LESENSE_ST_TCONFA */
+#define _LESENSE_ST_TCONFA_PRSACT_PRS02 0x00000005UL /**< Mode PRS02 for LESENSE_ST_TCONFA */
#define _LESENSE_ST_TCONFA_PRSACT_PRS12 0x00000006UL /**< Mode PRS12 for LESENSE_ST_TCONFA */
#define _LESENSE_ST_TCONFA_PRSACT_DOWNANDPRS2 0x00000006UL /**< Mode DOWNANDPRS2 for LESENSE_ST_TCONFA */
#define _LESENSE_ST_TCONFA_PRSACT_PRS012 0x00000007UL /**< Mode PRS012 for LESENSE_ST_TCONFA */
#define LESENSE_ST_TCONFA_PRSACT_DEFAULT (_LESENSE_ST_TCONFA_PRSACT_DEFAULT << 16) /**< Shifted mode DEFAULT for LESENSE_ST_TCONFA */
#define LESENSE_ST_TCONFA_PRSACT_NONE (_LESENSE_ST_TCONFA_PRSACT_NONE << 16) /**< Shifted mode NONE for LESENSE_ST_TCONFA */
-#define LESENSE_ST_TCONFA_PRSACT_UP (_LESENSE_ST_TCONFA_PRSACT_UP << 16) /**< Shifted mode UP for LESENSE_ST_TCONFA */
#define LESENSE_ST_TCONFA_PRSACT_PRS0 (_LESENSE_ST_TCONFA_PRSACT_PRS0 << 16) /**< Shifted mode PRS0 for LESENSE_ST_TCONFA */
-#define LESENSE_ST_TCONFA_PRSACT_PRS1 (_LESENSE_ST_TCONFA_PRSACT_PRS1 << 16) /**< Shifted mode PRS1 for LESENSE_ST_TCONFA */
+#define LESENSE_ST_TCONFA_PRSACT_UP (_LESENSE_ST_TCONFA_PRSACT_UP << 16) /**< Shifted mode UP for LESENSE_ST_TCONFA */
#define LESENSE_ST_TCONFA_PRSACT_DOWN (_LESENSE_ST_TCONFA_PRSACT_DOWN << 16) /**< Shifted mode DOWN for LESENSE_ST_TCONFA */
+#define LESENSE_ST_TCONFA_PRSACT_PRS1 (_LESENSE_ST_TCONFA_PRSACT_PRS1 << 16) /**< Shifted mode PRS1 for LESENSE_ST_TCONFA */
#define LESENSE_ST_TCONFA_PRSACT_PRS01 (_LESENSE_ST_TCONFA_PRSACT_PRS01 << 16) /**< Shifted mode PRS01 for LESENSE_ST_TCONFA */
#define LESENSE_ST_TCONFA_PRSACT_PRS2 (_LESENSE_ST_TCONFA_PRSACT_PRS2 << 16) /**< Shifted mode PRS2 for LESENSE_ST_TCONFA */
-#define LESENSE_ST_TCONFA_PRSACT_PRS02 (_LESENSE_ST_TCONFA_PRSACT_PRS02 << 16) /**< Shifted mode PRS02 for LESENSE_ST_TCONFA */
#define LESENSE_ST_TCONFA_PRSACT_UPANDPRS2 (_LESENSE_ST_TCONFA_PRSACT_UPANDPRS2 << 16) /**< Shifted mode UPANDPRS2 for LESENSE_ST_TCONFA */
+#define LESENSE_ST_TCONFA_PRSACT_PRS02 (_LESENSE_ST_TCONFA_PRSACT_PRS02 << 16) /**< Shifted mode PRS02 for LESENSE_ST_TCONFA */
#define LESENSE_ST_TCONFA_PRSACT_PRS12 (_LESENSE_ST_TCONFA_PRSACT_PRS12 << 16) /**< Shifted mode PRS12 for LESENSE_ST_TCONFA */
#define LESENSE_ST_TCONFA_PRSACT_DOWNANDPRS2 (_LESENSE_ST_TCONFA_PRSACT_DOWNANDPRS2 << 16) /**< Shifted mode DOWNANDPRS2 for LESENSE_ST_TCONFA */
#define LESENSE_ST_TCONFA_PRSACT_PRS012 (_LESENSE_ST_TCONFA_PRSACT_PRS012 << 16) /**< Shifted mode PRS012 for LESENSE_ST_TCONFA */
@@ -1706,27 +1705,27 @@ typedef struct {
#define _LESENSE_ST_TCONFB_PRSACT_MASK 0x70000UL /**< Bit mask for LESENSE_PRSACT */
#define _LESENSE_ST_TCONFB_PRSACT_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_ST_TCONFB */
#define _LESENSE_ST_TCONFB_PRSACT_NONE 0x00000000UL /**< Mode NONE for LESENSE_ST_TCONFB */
-#define _LESENSE_ST_TCONFB_PRSACT_UP 0x00000001UL /**< Mode UP for LESENSE_ST_TCONFB */
#define _LESENSE_ST_TCONFB_PRSACT_PRS0 0x00000001UL /**< Mode PRS0 for LESENSE_ST_TCONFB */
-#define _LESENSE_ST_TCONFB_PRSACT_PRS1 0x00000002UL /**< Mode PRS1 for LESENSE_ST_TCONFB */
+#define _LESENSE_ST_TCONFB_PRSACT_UP 0x00000001UL /**< Mode UP for LESENSE_ST_TCONFB */
#define _LESENSE_ST_TCONFB_PRSACT_DOWN 0x00000002UL /**< Mode DOWN for LESENSE_ST_TCONFB */
+#define _LESENSE_ST_TCONFB_PRSACT_PRS1 0x00000002UL /**< Mode PRS1 for LESENSE_ST_TCONFB */
#define _LESENSE_ST_TCONFB_PRSACT_PRS01 0x00000003UL /**< Mode PRS01 for LESENSE_ST_TCONFB */
#define _LESENSE_ST_TCONFB_PRSACT_PRS2 0x00000004UL /**< Mode PRS2 for LESENSE_ST_TCONFB */
-#define _LESENSE_ST_TCONFB_PRSACT_PRS02 0x00000005UL /**< Mode PRS02 for LESENSE_ST_TCONFB */
#define _LESENSE_ST_TCONFB_PRSACT_UPANDPRS2 0x00000005UL /**< Mode UPANDPRS2 for LESENSE_ST_TCONFB */
+#define _LESENSE_ST_TCONFB_PRSACT_PRS02 0x00000005UL /**< Mode PRS02 for LESENSE_ST_TCONFB */
#define _LESENSE_ST_TCONFB_PRSACT_PRS12 0x00000006UL /**< Mode PRS12 for LESENSE_ST_TCONFB */
#define _LESENSE_ST_TCONFB_PRSACT_DOWNANDPRS2 0x00000006UL /**< Mode DOWNANDPRS2 for LESENSE_ST_TCONFB */
#define _LESENSE_ST_TCONFB_PRSACT_PRS012 0x00000007UL /**< Mode PRS012 for LESENSE_ST_TCONFB */
#define LESENSE_ST_TCONFB_PRSACT_DEFAULT (_LESENSE_ST_TCONFB_PRSACT_DEFAULT << 16) /**< Shifted mode DEFAULT for LESENSE_ST_TCONFB */
#define LESENSE_ST_TCONFB_PRSACT_NONE (_LESENSE_ST_TCONFB_PRSACT_NONE << 16) /**< Shifted mode NONE for LESENSE_ST_TCONFB */
-#define LESENSE_ST_TCONFB_PRSACT_UP (_LESENSE_ST_TCONFB_PRSACT_UP << 16) /**< Shifted mode UP for LESENSE_ST_TCONFB */
#define LESENSE_ST_TCONFB_PRSACT_PRS0 (_LESENSE_ST_TCONFB_PRSACT_PRS0 << 16) /**< Shifted mode PRS0 for LESENSE_ST_TCONFB */
-#define LESENSE_ST_TCONFB_PRSACT_PRS1 (_LESENSE_ST_TCONFB_PRSACT_PRS1 << 16) /**< Shifted mode PRS1 for LESENSE_ST_TCONFB */
+#define LESENSE_ST_TCONFB_PRSACT_UP (_LESENSE_ST_TCONFB_PRSACT_UP << 16) /**< Shifted mode UP for LESENSE_ST_TCONFB */
#define LESENSE_ST_TCONFB_PRSACT_DOWN (_LESENSE_ST_TCONFB_PRSACT_DOWN << 16) /**< Shifted mode DOWN for LESENSE_ST_TCONFB */
+#define LESENSE_ST_TCONFB_PRSACT_PRS1 (_LESENSE_ST_TCONFB_PRSACT_PRS1 << 16) /**< Shifted mode PRS1 for LESENSE_ST_TCONFB */
#define LESENSE_ST_TCONFB_PRSACT_PRS01 (_LESENSE_ST_TCONFB_PRSACT_PRS01 << 16) /**< Shifted mode PRS01 for LESENSE_ST_TCONFB */
#define LESENSE_ST_TCONFB_PRSACT_PRS2 (_LESENSE_ST_TCONFB_PRSACT_PRS2 << 16) /**< Shifted mode PRS2 for LESENSE_ST_TCONFB */
-#define LESENSE_ST_TCONFB_PRSACT_PRS02 (_LESENSE_ST_TCONFB_PRSACT_PRS02 << 16) /**< Shifted mode PRS02 for LESENSE_ST_TCONFB */
#define LESENSE_ST_TCONFB_PRSACT_UPANDPRS2 (_LESENSE_ST_TCONFB_PRSACT_UPANDPRS2 << 16) /**< Shifted mode UPANDPRS2 for LESENSE_ST_TCONFB */
+#define LESENSE_ST_TCONFB_PRSACT_PRS02 (_LESENSE_ST_TCONFB_PRSACT_PRS02 << 16) /**< Shifted mode PRS02 for LESENSE_ST_TCONFB */
#define LESENSE_ST_TCONFB_PRSACT_PRS12 (_LESENSE_ST_TCONFB_PRSACT_PRS12 << 16) /**< Shifted mode PRS12 for LESENSE_ST_TCONFB */
#define LESENSE_ST_TCONFB_PRSACT_DOWNANDPRS2 (_LESENSE_ST_TCONFB_PRSACT_DOWNANDPRS2 << 16) /**< Shifted mode DOWNANDPRS2 for LESENSE_ST_TCONFB */
#define LESENSE_ST_TCONFB_PRSACT_PRS012 (_LESENSE_ST_TCONFB_PRSACT_PRS012 << 16) /**< Shifted mode PRS012 for LESENSE_ST_TCONFB */
diff --git a/cpu/efm32/families/efm32pg12b/include/vendor/efm32pg12b_lesense_buf.h b/cpu/efm32/families/efm32pg12b/include/vendor/efm32pg12b_lesense_buf.h
index d618b6d502..77994ec94f 100644
--- a/cpu/efm32/families/efm32pg12b/include/vendor/efm32pg12b_lesense_buf.h
+++ b/cpu/efm32/families/efm32pg12b/include/vendor/efm32pg12b_lesense_buf.h
@@ -1,10 +1,9 @@
/***************************************************************************//**
* @file
* @brief EFM32PG12B_LESENSE_BUF register and bit field definitions
- * @version 5.8.3
*******************************************************************************
* # License
- * Copyright 2019 Silicon Laboratories Inc. www.silabs.com
+ * Copyright 2020 Silicon Laboratories Inc. www.silabs.com
*******************************************************************************
*
* SPDX-License-Identifier: Zlib
diff --git a/cpu/efm32/families/efm32pg12b/include/vendor/efm32pg12b_lesense_ch.h b/cpu/efm32/families/efm32pg12b/include/vendor/efm32pg12b_lesense_ch.h
index 62efd790fb..3f14138598 100644
--- a/cpu/efm32/families/efm32pg12b/include/vendor/efm32pg12b_lesense_ch.h
+++ b/cpu/efm32/families/efm32pg12b/include/vendor/efm32pg12b_lesense_ch.h
@@ -1,10 +1,9 @@
/***************************************************************************//**
* @file
* @brief EFM32PG12B_LESENSE_CH register and bit field definitions
- * @version 5.8.3
*******************************************************************************
* # License
- * Copyright 2019 Silicon Laboratories Inc. www.silabs.com
+ * Copyright 2020 Silicon Laboratories Inc. www.silabs.com
*******************************************************************************
*
* SPDX-License-Identifier: Zlib
diff --git a/cpu/efm32/families/efm32pg12b/include/vendor/efm32pg12b_lesense_st.h b/cpu/efm32/families/efm32pg12b/include/vendor/efm32pg12b_lesense_st.h
index 6177f7af83..97b76969e0 100644
--- a/cpu/efm32/families/efm32pg12b/include/vendor/efm32pg12b_lesense_st.h
+++ b/cpu/efm32/families/efm32pg12b/include/vendor/efm32pg12b_lesense_st.h
@@ -1,10 +1,9 @@
/***************************************************************************//**
* @file
* @brief EFM32PG12B_LESENSE_ST register and bit field definitions
- * @version 5.8.3
*******************************************************************************
* # License
- * Copyright 2019 Silicon Laboratories Inc. www.silabs.com
+ * Copyright 2020 Silicon Laboratories Inc. www.silabs.com
*******************************************************************************
*
* SPDX-License-Identifier: Zlib
diff --git a/cpu/efm32/families/efm32pg12b/include/vendor/efm32pg12b_letimer.h b/cpu/efm32/families/efm32pg12b/include/vendor/efm32pg12b_letimer.h
index 84240ab314..eb1a4f3950 100644
--- a/cpu/efm32/families/efm32pg12b/include/vendor/efm32pg12b_letimer.h
+++ b/cpu/efm32/families/efm32pg12b/include/vendor/efm32pg12b_letimer.h
@@ -1,10 +1,9 @@
/***************************************************************************//**
* @file
* @brief EFM32PG12B_LETIMER register and bit field definitions
- * @version 5.8.3
*******************************************************************************
* # License
- * Copyright 2019 Silicon Laboratories Inc. www.silabs.com
+ * Copyright 2020 Silicon Laboratories Inc. www.silabs.com
*******************************************************************************
*
* SPDX-License-Identifier: Zlib
diff --git a/cpu/efm32/families/efm32pg12b/include/vendor/efm32pg12b_leuart.h b/cpu/efm32/families/efm32pg12b/include/vendor/efm32pg12b_leuart.h
index b4940c9c97..6fa838d96a 100644
--- a/cpu/efm32/families/efm32pg12b/include/vendor/efm32pg12b_leuart.h
+++ b/cpu/efm32/families/efm32pg12b/include/vendor/efm32pg12b_leuart.h
@@ -1,10 +1,9 @@
/***************************************************************************//**
* @file
* @brief EFM32PG12B_LEUART register and bit field definitions
- * @version 5.8.3
*******************************************************************************
* # License
- * Copyright 2019 Silicon Laboratories Inc. www.silabs.com
+ * Copyright 2020 Silicon Laboratories Inc. www.silabs.com
*******************************************************************************
*
* SPDX-License-Identifier: Zlib
diff --git a/cpu/efm32/families/efm32pg12b/include/vendor/efm32pg12b_msc.h b/cpu/efm32/families/efm32pg12b/include/vendor/efm32pg12b_msc.h
index e994dd58d0..d7b995a700 100644
--- a/cpu/efm32/families/efm32pg12b/include/vendor/efm32pg12b_msc.h
+++ b/cpu/efm32/families/efm32pg12b/include/vendor/efm32pg12b_msc.h
@@ -1,10 +1,9 @@
/***************************************************************************//**
* @file
* @brief EFM32PG12B_MSC register and bit field definitions
- * @version 5.8.3
*******************************************************************************
* # License
- * Copyright 2019 Silicon Laboratories Inc. www.silabs.com
+ * Copyright 2020 Silicon Laboratories Inc. www.silabs.com
*******************************************************************************
*
* SPDX-License-Identifier: Zlib
@@ -489,13 +488,13 @@ typedef struct {
#define _MSC_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for MSC_LOCKKEY */
#define _MSC_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for MSC_LOCKKEY */
#define _MSC_LOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_LOCK */
-#define _MSC_LOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for MSC_LOCK */
#define _MSC_LOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for MSC_LOCK */
+#define _MSC_LOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for MSC_LOCK */
#define _MSC_LOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for MSC_LOCK */
#define _MSC_LOCK_LOCKKEY_UNLOCK 0x00001B71UL /**< Mode UNLOCK for MSC_LOCK */
#define MSC_LOCK_LOCKKEY_DEFAULT (_MSC_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_LOCK */
-#define MSC_LOCK_LOCKKEY_LOCK (_MSC_LOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for MSC_LOCK */
#define MSC_LOCK_LOCKKEY_UNLOCKED (_MSC_LOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for MSC_LOCK */
+#define MSC_LOCK_LOCKKEY_LOCK (_MSC_LOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for MSC_LOCK */
#define MSC_LOCK_LOCKKEY_LOCKED (_MSC_LOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for MSC_LOCK */
#define MSC_LOCK_LOCKKEY_UNLOCK (_MSC_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for MSC_LOCK */
@@ -539,13 +538,13 @@ typedef struct {
#define _MSC_MASSLOCK_MASK 0x0000FFFFUL /**< Mask for MSC_MASSLOCK */
#define _MSC_MASSLOCK_LOCKKEY_SHIFT 0 /**< Shift value for MSC_LOCKKEY */
#define _MSC_MASSLOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for MSC_LOCKKEY */
-#define _MSC_MASSLOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for MSC_MASSLOCK */
#define _MSC_MASSLOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for MSC_MASSLOCK */
+#define _MSC_MASSLOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for MSC_MASSLOCK */
#define _MSC_MASSLOCK_LOCKKEY_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_MASSLOCK */
#define _MSC_MASSLOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for MSC_MASSLOCK */
#define _MSC_MASSLOCK_LOCKKEY_UNLOCK 0x0000631AUL /**< Mode UNLOCK for MSC_MASSLOCK */
-#define MSC_MASSLOCK_LOCKKEY_LOCK (_MSC_MASSLOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for MSC_MASSLOCK */
#define MSC_MASSLOCK_LOCKKEY_UNLOCKED (_MSC_MASSLOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for MSC_MASSLOCK */
+#define MSC_MASSLOCK_LOCKKEY_LOCK (_MSC_MASSLOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for MSC_MASSLOCK */
#define MSC_MASSLOCK_LOCKKEY_DEFAULT (_MSC_MASSLOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_MASSLOCK */
#define MSC_MASSLOCK_LOCKKEY_LOCKED (_MSC_MASSLOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for MSC_MASSLOCK */
#define MSC_MASSLOCK_LOCKKEY_UNLOCK (_MSC_MASSLOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for MSC_MASSLOCK */
@@ -586,13 +585,13 @@ typedef struct {
#define _MSC_BANKSWITCHLOCK_MASK 0x0000FFFFUL /**< Mask for MSC_BANKSWITCHLOCK */
#define _MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_SHIFT 0 /**< Shift value for MSC_BANKSWITCHLOCKKEY */
#define _MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_MASK 0xFFFFUL /**< Bit mask for MSC_BANKSWITCHLOCKKEY */
-#define _MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for MSC_BANKSWITCHLOCK */
#define _MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for MSC_BANKSWITCHLOCK */
+#define _MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for MSC_BANKSWITCHLOCK */
#define _MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_BANKSWITCHLOCK */
#define _MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for MSC_BANKSWITCHLOCK */
#define _MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_UNLOCK 0x00007C2BUL /**< Mode UNLOCK for MSC_BANKSWITCHLOCK */
-#define MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_LOCK (_MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_LOCK << 0) /**< Shifted mode LOCK for MSC_BANKSWITCHLOCK */
#define MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_UNLOCKED (_MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for MSC_BANKSWITCHLOCK */
+#define MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_LOCK (_MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_LOCK << 0) /**< Shifted mode LOCK for MSC_BANKSWITCHLOCK */
#define MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_DEFAULT (_MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_BANKSWITCHLOCK */
#define MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_LOCKED (_MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for MSC_BANKSWITCHLOCK */
#define MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_UNLOCK (_MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for MSC_BANKSWITCHLOCK */
diff --git a/cpu/efm32/families/efm32pg12b/include/vendor/efm32pg12b_pcnt.h b/cpu/efm32/families/efm32pg12b/include/vendor/efm32pg12b_pcnt.h
index 61809ec546..17ec7ba821 100644
--- a/cpu/efm32/families/efm32pg12b/include/vendor/efm32pg12b_pcnt.h
+++ b/cpu/efm32/families/efm32pg12b/include/vendor/efm32pg12b_pcnt.h
@@ -1,10 +1,9 @@
/***************************************************************************//**
* @file
* @brief EFM32PG12B_PCNT register and bit field definitions
- * @version 5.8.3
*******************************************************************************
* # License
- * Copyright 2019 Silicon Laboratories Inc. www.silabs.com
+ * Copyright 2020 Silicon Laboratories Inc. www.silabs.com
*******************************************************************************
*
* SPDX-License-Identifier: Zlib
diff --git a/cpu/efm32/families/efm32pg12b/include/vendor/efm32pg12b_prs.h b/cpu/efm32/families/efm32pg12b/include/vendor/efm32pg12b_prs.h
index 4c91043c6b..3207b4a7e4 100644
--- a/cpu/efm32/families/efm32pg12b/include/vendor/efm32pg12b_prs.h
+++ b/cpu/efm32/families/efm32pg12b/include/vendor/efm32pg12b_prs.h
@@ -1,10 +1,9 @@
/***************************************************************************//**
* @file
* @brief EFM32PG12B_PRS register and bit field definitions
- * @version 5.8.3
*******************************************************************************
* # License
- * Copyright 2019 Silicon Laboratories Inc. www.silabs.com
+ * Copyright 2020 Silicon Laboratories Inc. www.silabs.com
*******************************************************************************
*
* SPDX-License-Identifier: Zlib
diff --git a/cpu/efm32/families/efm32pg12b/include/vendor/efm32pg12b_prs_ch.h b/cpu/efm32/families/efm32pg12b/include/vendor/efm32pg12b_prs_ch.h
index a89a3cc780..aedf871a6e 100644
--- a/cpu/efm32/families/efm32pg12b/include/vendor/efm32pg12b_prs_ch.h
+++ b/cpu/efm32/families/efm32pg12b/include/vendor/efm32pg12b_prs_ch.h
@@ -1,10 +1,9 @@
/***************************************************************************//**
* @file
* @brief EFM32PG12B_PRS_CH register and bit field definitions
- * @version 5.8.3
*******************************************************************************
* # License
- * Copyright 2019 Silicon Laboratories Inc. www.silabs.com
+ * Copyright 2020 Silicon Laboratories Inc. www.silabs.com
*******************************************************************************
*
* SPDX-License-Identifier: Zlib
diff --git a/cpu/efm32/families/efm32pg12b/include/vendor/efm32pg12b_prs_signals.h b/cpu/efm32/families/efm32pg12b/include/vendor/efm32pg12b_prs_signals.h
index dce6e98322..69605754a1 100644
--- a/cpu/efm32/families/efm32pg12b/include/vendor/efm32pg12b_prs_signals.h
+++ b/cpu/efm32/families/efm32pg12b/include/vendor/efm32pg12b_prs_signals.h
@@ -1,10 +1,9 @@
/***************************************************************************//**
* @file
* @brief EFM32PG12B_PRS_SIGNALS register and bit field definitions
- * @version 5.8.3
*******************************************************************************
* # License
- * Copyright 2019 Silicon Laboratories Inc. www.silabs.com
+ * Copyright 2020 Silicon Laboratories Inc. www.silabs.com
*******************************************************************************
*
* SPDX-License-Identifier: Zlib
diff --git a/cpu/efm32/families/efm32pg12b/include/vendor/efm32pg12b_rmu.h b/cpu/efm32/families/efm32pg12b/include/vendor/efm32pg12b_rmu.h
index 3b8b4df279..5ff649191a 100644
--- a/cpu/efm32/families/efm32pg12b/include/vendor/efm32pg12b_rmu.h
+++ b/cpu/efm32/families/efm32pg12b/include/vendor/efm32pg12b_rmu.h
@@ -1,10 +1,9 @@
/***************************************************************************//**
* @file
* @brief EFM32PG12B_RMU register and bit field definitions
- * @version 5.8.3
*******************************************************************************
* # License
- * Copyright 2019 Silicon Laboratories Inc. www.silabs.com
+ * Copyright 2020 Silicon Laboratories Inc. www.silabs.com
*******************************************************************************
*
* SPDX-License-Identifier: Zlib
@@ -189,13 +188,13 @@ typedef struct {
#define _RMU_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for RMU_LOCKKEY */
#define _RMU_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for RMU_LOCKKEY */
#define _RMU_LOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for RMU_LOCK */
-#define _RMU_LOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for RMU_LOCK */
#define _RMU_LOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for RMU_LOCK */
+#define _RMU_LOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for RMU_LOCK */
#define _RMU_LOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for RMU_LOCK */
#define _RMU_LOCK_LOCKKEY_UNLOCK 0x0000E084UL /**< Mode UNLOCK for RMU_LOCK */
#define RMU_LOCK_LOCKKEY_DEFAULT (_RMU_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for RMU_LOCK */
-#define RMU_LOCK_LOCKKEY_LOCK (_RMU_LOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for RMU_LOCK */
#define RMU_LOCK_LOCKKEY_UNLOCKED (_RMU_LOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for RMU_LOCK */
+#define RMU_LOCK_LOCKKEY_LOCK (_RMU_LOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for RMU_LOCK */
#define RMU_LOCK_LOCKKEY_LOCKED (_RMU_LOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for RMU_LOCK */
#define RMU_LOCK_LOCKKEY_UNLOCK (_RMU_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for RMU_LOCK */
diff --git a/cpu/efm32/families/efm32pg12b/include/vendor/efm32pg12b_romtable.h b/cpu/efm32/families/efm32pg12b/include/vendor/efm32pg12b_romtable.h
index e6e7cddc2e..5e61f725cd 100644
--- a/cpu/efm32/families/efm32pg12b/include/vendor/efm32pg12b_romtable.h
+++ b/cpu/efm32/families/efm32pg12b/include/vendor/efm32pg12b_romtable.h
@@ -1,10 +1,9 @@
/***************************************************************************//**
* @file
* @brief EFM32PG12B_ROMTABLE register and bit field definitions
- * @version 5.8.3
*******************************************************************************
* # License
- * Copyright 2019 Silicon Laboratories Inc. www.silabs.com
+ * Copyright 2020 Silicon Laboratories Inc. www.silabs.com
*******************************************************************************
*
* SPDX-License-Identifier: Zlib
diff --git a/cpu/efm32/families/efm32pg12b/include/vendor/efm32pg12b_rtcc.h b/cpu/efm32/families/efm32pg12b/include/vendor/efm32pg12b_rtcc.h
index d3e8e137fb..8591af09a2 100644
--- a/cpu/efm32/families/efm32pg12b/include/vendor/efm32pg12b_rtcc.h
+++ b/cpu/efm32/families/efm32pg12b/include/vendor/efm32pg12b_rtcc.h
@@ -1,10 +1,9 @@
/***************************************************************************//**
* @file
* @brief EFM32PG12B_RTCC register and bit field definitions
- * @version 5.8.3
*******************************************************************************
* # License
- * Copyright 2019 Silicon Laboratories Inc. www.silabs.com
+ * Copyright 2020 Silicon Laboratories Inc. www.silabs.com
*******************************************************************************
*
* SPDX-License-Identifier: Zlib
@@ -531,13 +530,13 @@ typedef struct {
#define _RTCC_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for RTCC_LOCKKEY */
#define _RTCC_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for RTCC_LOCKKEY */
#define _RTCC_LOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_LOCK */
-#define _RTCC_LOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for RTCC_LOCK */
#define _RTCC_LOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for RTCC_LOCK */
+#define _RTCC_LOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for RTCC_LOCK */
#define _RTCC_LOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for RTCC_LOCK */
#define _RTCC_LOCK_LOCKKEY_UNLOCK 0x0000AEE8UL /**< Mode UNLOCK for RTCC_LOCK */
#define RTCC_LOCK_LOCKKEY_DEFAULT (_RTCC_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for RTCC_LOCK */
-#define RTCC_LOCK_LOCKKEY_LOCK (_RTCC_LOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for RTCC_LOCK */
#define RTCC_LOCK_LOCKKEY_UNLOCKED (_RTCC_LOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for RTCC_LOCK */
+#define RTCC_LOCK_LOCKKEY_LOCK (_RTCC_LOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for RTCC_LOCK */
#define RTCC_LOCK_LOCKKEY_LOCKED (_RTCC_LOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for RTCC_LOCK */
#define RTCC_LOCK_LOCKKEY_UNLOCK (_RTCC_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for RTCC_LOCK */
diff --git a/cpu/efm32/families/efm32pg12b/include/vendor/efm32pg12b_rtcc_cc.h b/cpu/efm32/families/efm32pg12b/include/vendor/efm32pg12b_rtcc_cc.h
index d1f50b5c33..5098047fff 100644
--- a/cpu/efm32/families/efm32pg12b/include/vendor/efm32pg12b_rtcc_cc.h
+++ b/cpu/efm32/families/efm32pg12b/include/vendor/efm32pg12b_rtcc_cc.h
@@ -1,10 +1,9 @@
/***************************************************************************//**
* @file
* @brief EFM32PG12B_RTCC_CC register and bit field definitions
- * @version 5.8.3
*******************************************************************************
* # License
- * Copyright 2019 Silicon Laboratories Inc. www.silabs.com
+ * Copyright 2020 Silicon Laboratories Inc. www.silabs.com
*******************************************************************************
*
* SPDX-License-Identifier: Zlib
diff --git a/cpu/efm32/families/efm32pg12b/include/vendor/efm32pg12b_rtcc_ret.h b/cpu/efm32/families/efm32pg12b/include/vendor/efm32pg12b_rtcc_ret.h
index e50afb6d92..f52b6ff687 100644
--- a/cpu/efm32/families/efm32pg12b/include/vendor/efm32pg12b_rtcc_ret.h
+++ b/cpu/efm32/families/efm32pg12b/include/vendor/efm32pg12b_rtcc_ret.h
@@ -1,10 +1,9 @@
/***************************************************************************//**
* @file
* @brief EFM32PG12B_RTCC_RET register and bit field definitions
- * @version 5.8.3
*******************************************************************************
* # License
- * Copyright 2019 Silicon Laboratories Inc. www.silabs.com
+ * Copyright 2020 Silicon Laboratories Inc. www.silabs.com
*******************************************************************************
*
* SPDX-License-Identifier: Zlib
diff --git a/cpu/efm32/families/efm32pg12b/include/vendor/efm32pg12b_smu.h b/cpu/efm32/families/efm32pg12b/include/vendor/efm32pg12b_smu.h
index d590949053..144e393d04 100644
--- a/cpu/efm32/families/efm32pg12b/include/vendor/efm32pg12b_smu.h
+++ b/cpu/efm32/families/efm32pg12b/include/vendor/efm32pg12b_smu.h
@@ -1,10 +1,9 @@
/***************************************************************************//**
* @file
* @brief EFM32PG12B_SMU register and bit field definitions
- * @version 5.8.3
*******************************************************************************
* # License
- * Copyright 2019 Silicon Laboratories Inc. www.silabs.com
+ * Copyright 2020 Silicon Laboratories Inc. www.silabs.com
*******************************************************************************
*
* SPDX-License-Identifier: Zlib
diff --git a/cpu/efm32/families/efm32pg12b/include/vendor/efm32pg12b_timer.h b/cpu/efm32/families/efm32pg12b/include/vendor/efm32pg12b_timer.h
index f00d1ec99c..7c5fd7c540 100644
--- a/cpu/efm32/families/efm32pg12b/include/vendor/efm32pg12b_timer.h
+++ b/cpu/efm32/families/efm32pg12b/include/vendor/efm32pg12b_timer.h
@@ -1,10 +1,9 @@
/***************************************************************************//**
* @file
* @brief EFM32PG12B_TIMER register and bit field definitions
- * @version 5.8.3
*******************************************************************************
* # License
- * Copyright 2019 Silicon Laboratories Inc. www.silabs.com
+ * Copyright 2020 Silicon Laboratories Inc. www.silabs.com
*******************************************************************************
*
* SPDX-License-Identifier: Zlib
@@ -586,13 +585,13 @@ typedef struct {
#define _TIMER_LOCK_TIMERLOCKKEY_SHIFT 0 /**< Shift value for TIMER_TIMERLOCKKEY */
#define _TIMER_LOCK_TIMERLOCKKEY_MASK 0xFFFFUL /**< Bit mask for TIMER_TIMERLOCKKEY */
#define _TIMER_LOCK_TIMERLOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_LOCK */
-#define _TIMER_LOCK_TIMERLOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for TIMER_LOCK */
#define _TIMER_LOCK_TIMERLOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for TIMER_LOCK */
+#define _TIMER_LOCK_TIMERLOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for TIMER_LOCK */
#define _TIMER_LOCK_TIMERLOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for TIMER_LOCK */
#define _TIMER_LOCK_TIMERLOCKKEY_UNLOCK 0x0000CE80UL /**< Mode UNLOCK for TIMER_LOCK */
#define TIMER_LOCK_TIMERLOCKKEY_DEFAULT (_TIMER_LOCK_TIMERLOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_LOCK */
-#define TIMER_LOCK_TIMERLOCKKEY_LOCK (_TIMER_LOCK_TIMERLOCKKEY_LOCK << 0) /**< Shifted mode LOCK for TIMER_LOCK */
#define TIMER_LOCK_TIMERLOCKKEY_UNLOCKED (_TIMER_LOCK_TIMERLOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for TIMER_LOCK */
+#define TIMER_LOCK_TIMERLOCKKEY_LOCK (_TIMER_LOCK_TIMERLOCKKEY_LOCK << 0) /**< Shifted mode LOCK for TIMER_LOCK */
#define TIMER_LOCK_TIMERLOCKKEY_LOCKED (_TIMER_LOCK_TIMERLOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for TIMER_LOCK */
#define TIMER_LOCK_TIMERLOCKKEY_UNLOCK (_TIMER_LOCK_TIMERLOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for TIMER_LOCK */
@@ -1573,13 +1572,13 @@ typedef struct {
#define _TIMER_DTLOCK_LOCKKEY_SHIFT 0 /**< Shift value for TIMER_LOCKKEY */
#define _TIMER_DTLOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for TIMER_LOCKKEY */
#define _TIMER_DTLOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTLOCK */
-#define _TIMER_DTLOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for TIMER_DTLOCK */
#define _TIMER_DTLOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for TIMER_DTLOCK */
+#define _TIMER_DTLOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for TIMER_DTLOCK */
#define _TIMER_DTLOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for TIMER_DTLOCK */
#define _TIMER_DTLOCK_LOCKKEY_UNLOCK 0x0000CE80UL /**< Mode UNLOCK for TIMER_DTLOCK */
#define TIMER_DTLOCK_LOCKKEY_DEFAULT (_TIMER_DTLOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_DTLOCK */
-#define TIMER_DTLOCK_LOCKKEY_LOCK (_TIMER_DTLOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for TIMER_DTLOCK */
#define TIMER_DTLOCK_LOCKKEY_UNLOCKED (_TIMER_DTLOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for TIMER_DTLOCK */
+#define TIMER_DTLOCK_LOCKKEY_LOCK (_TIMER_DTLOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for TIMER_DTLOCK */
#define TIMER_DTLOCK_LOCKKEY_LOCKED (_TIMER_DTLOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for TIMER_DTLOCK */
#define TIMER_DTLOCK_LOCKKEY_UNLOCK (_TIMER_DTLOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for TIMER_DTLOCK */
diff --git a/cpu/efm32/families/efm32pg12b/include/vendor/efm32pg12b_timer_cc.h b/cpu/efm32/families/efm32pg12b/include/vendor/efm32pg12b_timer_cc.h
index b10c048695..b76b0f8d6c 100644
--- a/cpu/efm32/families/efm32pg12b/include/vendor/efm32pg12b_timer_cc.h
+++ b/cpu/efm32/families/efm32pg12b/include/vendor/efm32pg12b_timer_cc.h
@@ -1,10 +1,9 @@
/***************************************************************************//**
* @file
* @brief EFM32PG12B_TIMER_CC register and bit field definitions
- * @version 5.8.3
*******************************************************************************
* # License
- * Copyright 2019 Silicon Laboratories Inc. www.silabs.com
+ * Copyright 2020 Silicon Laboratories Inc. www.silabs.com
*******************************************************************************
*
* SPDX-License-Identifier: Zlib
diff --git a/cpu/efm32/families/efm32pg12b/include/vendor/efm32pg12b_trng.h b/cpu/efm32/families/efm32pg12b/include/vendor/efm32pg12b_trng.h
index 98394911ff..5e85c17785 100644
--- a/cpu/efm32/families/efm32pg12b/include/vendor/efm32pg12b_trng.h
+++ b/cpu/efm32/families/efm32pg12b/include/vendor/efm32pg12b_trng.h
@@ -1,10 +1,9 @@
/***************************************************************************//**
* @file
* @brief EFM32PG12B_TRNG register and bit field definitions
- * @version 5.8.3
*******************************************************************************
* # License
- * Copyright 2019 Silicon Laboratories Inc. www.silabs.com
+ * Copyright 2020 Silicon Laboratories Inc. www.silabs.com
*******************************************************************************
*
* SPDX-License-Identifier: Zlib
diff --git a/cpu/efm32/families/efm32pg12b/include/vendor/efm32pg12b_usart.h b/cpu/efm32/families/efm32pg12b/include/vendor/efm32pg12b_usart.h
index 8ec6de9d97..c6094f241f 100644
--- a/cpu/efm32/families/efm32pg12b/include/vendor/efm32pg12b_usart.h
+++ b/cpu/efm32/families/efm32pg12b/include/vendor/efm32pg12b_usart.h
@@ -1,10 +1,9 @@
/***************************************************************************//**
* @file
* @brief EFM32PG12B_USART register and bit field definitions
- * @version 5.8.3
*******************************************************************************
* # License
- * Copyright 2019 Silicon Laboratories Inc. www.silabs.com
+ * Copyright 2020 Silicon Laboratories Inc. www.silabs.com
*******************************************************************************
*
* SPDX-License-Identifier: Zlib
diff --git a/cpu/efm32/families/efm32pg12b/include/vendor/efm32pg12b_vdac.h b/cpu/efm32/families/efm32pg12b/include/vendor/efm32pg12b_vdac.h
index 9ee9e867f7..389ec1f5d9 100644
--- a/cpu/efm32/families/efm32pg12b/include/vendor/efm32pg12b_vdac.h
+++ b/cpu/efm32/families/efm32pg12b/include/vendor/efm32pg12b_vdac.h
@@ -1,10 +1,9 @@
/***************************************************************************//**
* @file
* @brief EFM32PG12B_VDAC register and bit field definitions
- * @version 5.8.3
*******************************************************************************
* # License
- * Copyright 2019 Silicon Laboratories Inc. www.silabs.com
+ * Copyright 2020 Silicon Laboratories Inc. www.silabs.com
*******************************************************************************
*
* SPDX-License-Identifier: Zlib
diff --git a/cpu/efm32/families/efm32pg12b/include/vendor/efm32pg12b_vdac_opa.h b/cpu/efm32/families/efm32pg12b/include/vendor/efm32pg12b_vdac_opa.h
index ef29e50b31..d74734ecac 100644
--- a/cpu/efm32/families/efm32pg12b/include/vendor/efm32pg12b_vdac_opa.h
+++ b/cpu/efm32/families/efm32pg12b/include/vendor/efm32pg12b_vdac_opa.h
@@ -1,10 +1,9 @@
/***************************************************************************//**
* @file
* @brief EFM32PG12B_VDAC_OPA register and bit field definitions
- * @version 5.8.3
*******************************************************************************
* # License
- * Copyright 2019 Silicon Laboratories Inc. www.silabs.com
+ * Copyright 2020 Silicon Laboratories Inc. www.silabs.com
*******************************************************************************
*
* SPDX-License-Identifier: Zlib
diff --git a/cpu/efm32/families/efm32pg12b/include/vendor/efm32pg12b_wdog.h b/cpu/efm32/families/efm32pg12b/include/vendor/efm32pg12b_wdog.h
index 6942f200c4..d7fdd81bbd 100644
--- a/cpu/efm32/families/efm32pg12b/include/vendor/efm32pg12b_wdog.h
+++ b/cpu/efm32/families/efm32pg12b/include/vendor/efm32pg12b_wdog.h
@@ -1,10 +1,9 @@
/***************************************************************************//**
* @file
* @brief EFM32PG12B_WDOG register and bit field definitions
- * @version 5.8.3
*******************************************************************************
* # License
- * Copyright 2019 Silicon Laboratories Inc. www.silabs.com
+ * Copyright 2020 Silicon Laboratories Inc. www.silabs.com
*******************************************************************************
*
* SPDX-License-Identifier: Zlib
diff --git a/cpu/efm32/families/efm32pg12b/include/vendor/efm32pg12b_wdog_pch.h b/cpu/efm32/families/efm32pg12b/include/vendor/efm32pg12b_wdog_pch.h
index 833e8daf99..cd9d1b1d6f 100644
--- a/cpu/efm32/families/efm32pg12b/include/vendor/efm32pg12b_wdog_pch.h
+++ b/cpu/efm32/families/efm32pg12b/include/vendor/efm32pg12b_wdog_pch.h
@@ -1,10 +1,9 @@
/***************************************************************************//**
* @file
* @brief EFM32PG12B_WDOG_PCH register and bit field definitions
- * @version 5.8.3
*******************************************************************************
* # License
- * Copyright 2019 Silicon Laboratories Inc. www.silabs.com
+ * Copyright 2020 Silicon Laboratories Inc. www.silabs.com
*******************************************************************************
*
* SPDX-License-Identifier: Zlib
diff --git a/cpu/efm32/families/efm32pg12b/include/vendor/em_device.h b/cpu/efm32/families/efm32pg12b/include/vendor/em_device.h
index 76606cac3a..4b64e20ce6 100644
--- a/cpu/efm32/families/efm32pg12b/include/vendor/em_device.h
+++ b/cpu/efm32/families/efm32pg12b/include/vendor/em_device.h
@@ -11,10 +11,9 @@
* Add "#include "em_device.h" to your source files
* @endverbatim
*
- * @version 5.8.3
*******************************************************************************
* # License
- * Copyright 2019 Silicon Laboratories Inc. www.silabs.com
+ * Copyright 2020 Silicon Laboratories Inc. www.silabs.com
*******************************************************************************
*
* SPDX-License-Identifier: Zlib
diff --git a/cpu/efm32/families/efm32pg12b/include/vendor/system_efm32pg12b.h b/cpu/efm32/families/efm32pg12b/include/vendor/system_efm32pg12b.h
index 54e28e3599..e86bc079c1 100644
--- a/cpu/efm32/families/efm32pg12b/include/vendor/system_efm32pg12b.h
+++ b/cpu/efm32/families/efm32pg12b/include/vendor/system_efm32pg12b.h
@@ -1,10 +1,9 @@
/***************************************************************************//**
* @file
* @brief CMSIS Cortex-M3/M4 System Layer for EFM32 devices.
- * @version 5.8.3
*******************************************************************************
* # License
- * Copyright 2019 Silicon Laboratories Inc. www.silabs.com
+ * Copyright 2020 Silicon Laboratories Inc. www.silabs.com
*******************************************************************************
*
* SPDX-License-Identifier: Zlib
@@ -47,12 +46,29 @@ extern "C" {
* @{
******************************************************************************/
+/*******************************************************************************
+ ****************************** TYPEDEFS ***********************************
+ ******************************************************************************/
+
+/* Interrupt vectortable entry */
+typedef union {
+ void (*pFunc)(void);
+ void *topOfStack;
+} tVectorEntry;
+
/*******************************************************************************
************************** GLOBAL VARIABLES *******************************
******************************************************************************/
-extern uint32_t SystemCoreClock; /**< System Clock Frequency (Core Clock) */
-extern uint32_t SystemHfrcoFreq; /**< System HFRCO frequency */
+extern uint32_t SystemCoreClock; /**< System Clock Frequency (Core Clock) */
+extern uint32_t SystemHfrcoFreq; /**< System HFRCO frequency */
+
+#if defined(__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+#if defined(__ICCARM__) /* IAR requires the __vector_table symbol */
+#define __Vectors __vector_table
+#endif
+extern const tVectorEntry __Vectors[];
+#endif
/*******************************************************************************
***************************** PROTOTYPES **********************************
diff --git a/cpu/efm32/families/efm32pg12b/system.c b/cpu/efm32/families/efm32pg12b/system.c
index 0be22db05c..e60114ebfc 100644
--- a/cpu/efm32/families/efm32pg12b/system.c
+++ b/cpu/efm32/families/efm32pg12b/system.c
@@ -1,10 +1,9 @@
/***************************************************************************//**
* @file
* @brief CMSIS Cortex-M3/M4 System Layer for EFM32 devices.
- * @version 5.8.3
*******************************************************************************
* # License
- * Copyright 2019 Silicon Laboratories Inc. www.silabs.com
+ * Copyright 2020 Silicon Laboratories Inc. www.silabs.com
*******************************************************************************
*
* SPDX-License-Identifier: Zlib
@@ -117,13 +116,6 @@ uint32_t SystemHfrcoFreq = EFM32_HFRCO_STARTUP_FREQ;
************************** GLOBAL FUNCTIONS *******************************
******************************************************************************/
-#if defined(__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
-#if defined(__ICCARM__) /* IAR requires the __vector_table symbol */
-#define __Vectors __vector_table
-#endif
-extern uint32_t __Vectors;
-#endif
-
/***************************************************************************//**
* @brief
* Get the current core clock frequency.
@@ -215,6 +207,12 @@ uint32_t SystemHFClockGet(void)
#endif
break;
+#if defined(CMU_HFCLKSTATUS_SELECTED_HFRCODIV2)
+ case CMU_HFCLKSTATUS_SELECTED_HFRCODIV2:
+ ret = SystemHfrcoFreq / 2;
+ break;
+#endif
+
default: /* CMU_HFCLKSTATUS_SELECTED_HFRCO */
ret = SystemHfrcoFreq;
break;
@@ -303,6 +301,19 @@ void SystemInit(void)
#if defined(UNALIGNED_SUPPORT_DISABLE)
SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk;
#endif
+
+#if defined(_SILICON_LABS_32B_SERIES_1_CONFIG_1)
+ /****************************
+ * Fix for errata DCDC_E206
+ * Enable bypass switch as errata workaround. The bypass current limit will be
+ * disabled again in CHIP_Init() to avoid added current consumption. */
+
+ EMU->DCDCCLIMCTRL |= 1U << _EMU_DCDCCLIMCTRL_BYPLIMEN_SHIFT;
+ EMU->DCDCCTRL = (EMU->DCDCCTRL & ~_EMU_DCDCCTRL_DCDCMODE_MASK)
+ | EMU_DCDCCTRL_DCDCMODE_BYPASS;
+ *(volatile uint32_t *)(0x400E3074) &= ~(0x1UL << 0);
+ *(volatile uint32_t *)(0x400E3060) &= ~(0x1UL << 28);
+#endif
}
/***************************************************************************//**
diff --git a/cpu/efm32/families/efm32pg1b/include/vendor/efm32pg1b200f256gm48.h b/cpu/efm32/families/efm32pg1b/include/vendor/efm32pg1b200f256gm48.h
index b47d110f78..eaab259d6e 100644
--- a/cpu/efm32/families/efm32pg1b/include/vendor/efm32pg1b200f256gm48.h
+++ b/cpu/efm32/families/efm32pg1b/include/vendor/efm32pg1b200f256gm48.h
@@ -2,10 +2,9 @@
* @file
* @brief CMSIS Cortex-M Peripheral Access Layer Header File
* for EFM32PG1B200F256GM48
- * @version 5.8.3
*******************************************************************************
* # License
- * Copyright 2019 Silicon Laboratories Inc. www.silabs.com
+ * Copyright 2020 Silicon Laboratories Inc. www.silabs.com
*******************************************************************************
*
* SPDX-License-Identifier: Zlib
@@ -135,42 +134,42 @@ typedef enum IRQn{
#define PART_NUMBER "EFM32PG1B200F256GM48" /**< Part Number */
/** Memory Base addresses and limits */
-#define FLASH_MEM_BASE (0x00000000UL) /**< FLASH base address */
-#define FLASH_MEM_SIZE (0x10000000UL) /**< FLASH available address space */
-#define FLASH_MEM_END (0x0FFFFFFFUL) /**< FLASH end address */
-#define FLASH_MEM_BITS (0x0000001CUL) /**< FLASH used bits */
-#define RAM_CODE_MEM_BASE (0x10000000UL) /**< RAM_CODE base address */
-#define RAM_CODE_MEM_SIZE (0x7C00UL) /**< RAM_CODE available address space */
-#define RAM_CODE_MEM_END (0x10007BFFUL) /**< RAM_CODE end address */
-#define RAM_CODE_MEM_BITS (0x0000000FUL) /**< RAM_CODE used bits */
-#define PER_BITCLR_MEM_BASE (0x44000000UL) /**< PER_BITCLR base address */
-#define PER_BITCLR_MEM_SIZE (0xE8000UL) /**< PER_BITCLR available address space */
-#define PER_BITCLR_MEM_END (0x440E7FFFUL) /**< PER_BITCLR end address */
-#define PER_BITCLR_MEM_BITS (0x00000014UL) /**< PER_BITCLR used bits */
-#define CRYPTO_BITSET_MEM_BASE (0x460F0000UL) /**< CRYPTO_BITSET base address */
-#define CRYPTO_BITSET_MEM_SIZE (0x400UL) /**< CRYPTO_BITSET available address space */
-#define CRYPTO_BITSET_MEM_END (0x460F03FFUL) /**< CRYPTO_BITSET end address */
-#define CRYPTO_BITSET_MEM_BITS (0x0000000AUL) /**< CRYPTO_BITSET used bits */
#define CRYPTO_MEM_BASE (0x400F0000UL) /**< CRYPTO base address */
#define CRYPTO_MEM_SIZE (0x400UL) /**< CRYPTO available address space */
#define CRYPTO_MEM_END (0x400F03FFUL) /**< CRYPTO end address */
#define CRYPTO_MEM_BITS (0x0000000AUL) /**< CRYPTO used bits */
-#define CRYPTO_BITCLR_MEM_BASE (0x440F0000UL) /**< CRYPTO_BITCLR base address */
-#define CRYPTO_BITCLR_MEM_SIZE (0x400UL) /**< CRYPTO_BITCLR available address space */
-#define CRYPTO_BITCLR_MEM_END (0x440F03FFUL) /**< CRYPTO_BITCLR end address */
-#define CRYPTO_BITCLR_MEM_BITS (0x0000000AUL) /**< CRYPTO_BITCLR used bits */
-#define PER_BITSET_MEM_BASE (0x46000000UL) /**< PER_BITSET base address */
-#define PER_BITSET_MEM_SIZE (0xE8000UL) /**< PER_BITSET available address space */
-#define PER_BITSET_MEM_END (0x460E7FFFUL) /**< PER_BITSET end address */
-#define PER_BITSET_MEM_BITS (0x00000014UL) /**< PER_BITSET used bits */
-#define PER_MEM_BASE (0x40000000UL) /**< PER base address */
-#define PER_MEM_SIZE (0xE8000UL) /**< PER available address space */
-#define PER_MEM_END (0x400E7FFFUL) /**< PER end address */
-#define PER_MEM_BITS (0x00000014UL) /**< PER used bits */
#define RAM_MEM_BASE (0x20000000UL) /**< RAM base address */
#define RAM_MEM_SIZE (0x7C00UL) /**< RAM available address space */
#define RAM_MEM_END (0x20007BFFUL) /**< RAM end address */
#define RAM_MEM_BITS (0x0000000FUL) /**< RAM used bits */
+#define PER_BITSET_MEM_BASE (0x46000000UL) /**< PER_BITSET base address */
+#define PER_BITSET_MEM_SIZE (0xE8000UL) /**< PER_BITSET available address space */
+#define PER_BITSET_MEM_END (0x460E7FFFUL) /**< PER_BITSET end address */
+#define PER_BITSET_MEM_BITS (0x00000014UL) /**< PER_BITSET used bits */
+#define CRYPTO_BITSET_MEM_BASE (0x460F0000UL) /**< CRYPTO_BITSET base address */
+#define CRYPTO_BITSET_MEM_SIZE (0x400UL) /**< CRYPTO_BITSET available address space */
+#define CRYPTO_BITSET_MEM_END (0x460F03FFUL) /**< CRYPTO_BITSET end address */
+#define CRYPTO_BITSET_MEM_BITS (0x0000000AUL) /**< CRYPTO_BITSET used bits */
+#define PER_MEM_BASE (0x40000000UL) /**< PER base address */
+#define PER_MEM_SIZE (0xE8000UL) /**< PER available address space */
+#define PER_MEM_END (0x400E7FFFUL) /**< PER end address */
+#define PER_MEM_BITS (0x00000014UL) /**< PER used bits */
+#define CRYPTO_BITCLR_MEM_BASE (0x440F0000UL) /**< CRYPTO_BITCLR base address */
+#define CRYPTO_BITCLR_MEM_SIZE (0x400UL) /**< CRYPTO_BITCLR available address space */
+#define CRYPTO_BITCLR_MEM_END (0x440F03FFUL) /**< CRYPTO_BITCLR end address */
+#define CRYPTO_BITCLR_MEM_BITS (0x0000000AUL) /**< CRYPTO_BITCLR used bits */
+#define RAM_CODE_MEM_BASE (0x10000000UL) /**< RAM_CODE base address */
+#define RAM_CODE_MEM_SIZE (0x7C00UL) /**< RAM_CODE available address space */
+#define RAM_CODE_MEM_END (0x10007BFFUL) /**< RAM_CODE end address */
+#define RAM_CODE_MEM_BITS (0x0000000FUL) /**< RAM_CODE used bits */
+#define FLASH_MEM_BASE (0x00000000UL) /**< FLASH base address */
+#define FLASH_MEM_SIZE (0x10000000UL) /**< FLASH available address space */
+#define FLASH_MEM_END (0x0FFFFFFFUL) /**< FLASH end address */
+#define FLASH_MEM_BITS (0x0000001CUL) /**< FLASH used bits */
+#define PER_BITCLR_MEM_BASE (0x44000000UL) /**< PER_BITCLR base address */
+#define PER_BITCLR_MEM_SIZE (0xE8000UL) /**< PER_BITCLR available address space */
+#define PER_BITCLR_MEM_END (0x440E7FFFUL) /**< PER_BITCLR end address */
+#define PER_BITCLR_MEM_BITS (0x00000014UL) /**< PER_BITCLR used bits */
/** Bit banding area */
#define BITBAND_PER_BASE (0x42000000UL) /**< Peripheral Address Space bit-band area */
diff --git a/cpu/efm32/families/efm32pg1b/include/vendor/efm32pg1b_acmp.h b/cpu/efm32/families/efm32pg1b/include/vendor/efm32pg1b_acmp.h
index 7fcff6014d..7c8cc3d069 100644
--- a/cpu/efm32/families/efm32pg1b/include/vendor/efm32pg1b_acmp.h
+++ b/cpu/efm32/families/efm32pg1b/include/vendor/efm32pg1b_acmp.h
@@ -1,10 +1,9 @@
/***************************************************************************//**
* @file
* @brief EFM32PG1B_ACMP register and bit field definitions
- * @version 5.8.3
*******************************************************************************
* # License
- * Copyright 2019 Silicon Laboratories Inc. www.silabs.com
+ * Copyright 2020 Silicon Laboratories Inc. www.silabs.com
*******************************************************************************
*
* SPDX-License-Identifier: Zlib
@@ -324,6 +323,8 @@ typedef struct {
#define _ACMP_INPUTSEL_POSSEL_APORT4XCH11 0x0000008BUL /**< Mode APORT4XCH11 for ACMP_INPUTSEL */
#define _ACMP_INPUTSEL_POSSEL_APORT4YCH12 0x0000008CUL /**< Mode APORT4YCH12 for ACMP_INPUTSEL */
#define _ACMP_INPUTSEL_POSSEL_APORT4XCH13 0x0000008DUL /**< Mode APORT4XCH13 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_POSSEL_APORT4YCH14 0x0000008EUL /**< Mode APORT4YCH14 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_POSSEL_APORT4XCH15 0x0000008FUL /**< Mode APORT4XCH15 for ACMP_INPUTSEL */
#define _ACMP_INPUTSEL_POSSEL_APORT4YCH16 0x00000090UL /**< Mode APORT4YCH16 for ACMP_INPUTSEL */
#define _ACMP_INPUTSEL_POSSEL_APORT4XCH17 0x00000091UL /**< Mode APORT4XCH17 for ACMP_INPUTSEL */
#define _ACMP_INPUTSEL_POSSEL_APORT4YCH18 0x00000092UL /**< Mode APORT4YCH18 for ACMP_INPUTSEL */
@@ -339,8 +340,6 @@ typedef struct {
#define _ACMP_INPUTSEL_POSSEL_APORT4YCH28 0x0000009CUL /**< Mode APORT4YCH28 for ACMP_INPUTSEL */
#define _ACMP_INPUTSEL_POSSEL_APORT4XCH29 0x0000009DUL /**< Mode APORT4XCH29 for ACMP_INPUTSEL */
#define _ACMP_INPUTSEL_POSSEL_APORT4YCH30 0x0000009EUL /**< Mode APORT4YCH30 for ACMP_INPUTSEL */
-#define _ACMP_INPUTSEL_POSSEL_APORT4YCH14 0x0000009EUL /**< Mode APORT4YCH14 for ACMP_INPUTSEL */
-#define _ACMP_INPUTSEL_POSSEL_APORT4XCH15 0x0000009FUL /**< Mode APORT4XCH15 for ACMP_INPUTSEL */
#define _ACMP_INPUTSEL_POSSEL_APORT4XCH31 0x0000009FUL /**< Mode APORT4XCH31 for ACMP_INPUTSEL */
#define _ACMP_INPUTSEL_POSSEL_VLP 0x000000FBUL /**< Mode VLP for ACMP_INPUTSEL */
#define _ACMP_INPUTSEL_POSSEL_VBDIV 0x000000FCUL /**< Mode VBDIV for ACMP_INPUTSEL */
@@ -490,6 +489,8 @@ typedef struct {
#define ACMP_INPUTSEL_POSSEL_APORT4XCH11 (_ACMP_INPUTSEL_POSSEL_APORT4XCH11 << 0) /**< Shifted mode APORT4XCH11 for ACMP_INPUTSEL */
#define ACMP_INPUTSEL_POSSEL_APORT4YCH12 (_ACMP_INPUTSEL_POSSEL_APORT4YCH12 << 0) /**< Shifted mode APORT4YCH12 for ACMP_INPUTSEL */
#define ACMP_INPUTSEL_POSSEL_APORT4XCH13 (_ACMP_INPUTSEL_POSSEL_APORT4XCH13 << 0) /**< Shifted mode APORT4XCH13 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_POSSEL_APORT4YCH14 (_ACMP_INPUTSEL_POSSEL_APORT4YCH14 << 0) /**< Shifted mode APORT4YCH14 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_POSSEL_APORT4XCH15 (_ACMP_INPUTSEL_POSSEL_APORT4XCH15 << 0) /**< Shifted mode APORT4XCH15 for ACMP_INPUTSEL */
#define ACMP_INPUTSEL_POSSEL_APORT4YCH16 (_ACMP_INPUTSEL_POSSEL_APORT4YCH16 << 0) /**< Shifted mode APORT4YCH16 for ACMP_INPUTSEL */
#define ACMP_INPUTSEL_POSSEL_APORT4XCH17 (_ACMP_INPUTSEL_POSSEL_APORT4XCH17 << 0) /**< Shifted mode APORT4XCH17 for ACMP_INPUTSEL */
#define ACMP_INPUTSEL_POSSEL_APORT4YCH18 (_ACMP_INPUTSEL_POSSEL_APORT4YCH18 << 0) /**< Shifted mode APORT4YCH18 for ACMP_INPUTSEL */
@@ -505,8 +506,6 @@ typedef struct {
#define ACMP_INPUTSEL_POSSEL_APORT4YCH28 (_ACMP_INPUTSEL_POSSEL_APORT4YCH28 << 0) /**< Shifted mode APORT4YCH28 for ACMP_INPUTSEL */
#define ACMP_INPUTSEL_POSSEL_APORT4XCH29 (_ACMP_INPUTSEL_POSSEL_APORT4XCH29 << 0) /**< Shifted mode APORT4XCH29 for ACMP_INPUTSEL */
#define ACMP_INPUTSEL_POSSEL_APORT4YCH30 (_ACMP_INPUTSEL_POSSEL_APORT4YCH30 << 0) /**< Shifted mode APORT4YCH30 for ACMP_INPUTSEL */
-#define ACMP_INPUTSEL_POSSEL_APORT4YCH14 (_ACMP_INPUTSEL_POSSEL_APORT4YCH14 << 0) /**< Shifted mode APORT4YCH14 for ACMP_INPUTSEL */
-#define ACMP_INPUTSEL_POSSEL_APORT4XCH15 (_ACMP_INPUTSEL_POSSEL_APORT4XCH15 << 0) /**< Shifted mode APORT4XCH15 for ACMP_INPUTSEL */
#define ACMP_INPUTSEL_POSSEL_APORT4XCH31 (_ACMP_INPUTSEL_POSSEL_APORT4XCH31 << 0) /**< Shifted mode APORT4XCH31 for ACMP_INPUTSEL */
#define ACMP_INPUTSEL_POSSEL_VLP (_ACMP_INPUTSEL_POSSEL_VLP << 0) /**< Shifted mode VLP for ACMP_INPUTSEL */
#define ACMP_INPUTSEL_POSSEL_VBDIV (_ACMP_INPUTSEL_POSSEL_VBDIV << 0) /**< Shifted mode VBDIV for ACMP_INPUTSEL */
@@ -658,6 +657,8 @@ typedef struct {
#define _ACMP_INPUTSEL_NEGSEL_APORT4XCH11 0x0000008BUL /**< Mode APORT4XCH11 for ACMP_INPUTSEL */
#define _ACMP_INPUTSEL_NEGSEL_APORT4YCH12 0x0000008CUL /**< Mode APORT4YCH12 for ACMP_INPUTSEL */
#define _ACMP_INPUTSEL_NEGSEL_APORT4XCH13 0x0000008DUL /**< Mode APORT4XCH13 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_NEGSEL_APORT4YCH14 0x0000008EUL /**< Mode APORT4YCH14 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_NEGSEL_APORT4XCH15 0x0000008FUL /**< Mode APORT4XCH15 for ACMP_INPUTSEL */
#define _ACMP_INPUTSEL_NEGSEL_APORT4YCH16 0x00000090UL /**< Mode APORT4YCH16 for ACMP_INPUTSEL */
#define _ACMP_INPUTSEL_NEGSEL_APORT4XCH17 0x00000091UL /**< Mode APORT4XCH17 for ACMP_INPUTSEL */
#define _ACMP_INPUTSEL_NEGSEL_APORT4YCH18 0x00000092UL /**< Mode APORT4YCH18 for ACMP_INPUTSEL */
@@ -673,8 +674,6 @@ typedef struct {
#define _ACMP_INPUTSEL_NEGSEL_APORT4YCH28 0x0000009CUL /**< Mode APORT4YCH28 for ACMP_INPUTSEL */
#define _ACMP_INPUTSEL_NEGSEL_APORT4XCH29 0x0000009DUL /**< Mode APORT4XCH29 for ACMP_INPUTSEL */
#define _ACMP_INPUTSEL_NEGSEL_APORT4YCH30 0x0000009EUL /**< Mode APORT4YCH30 for ACMP_INPUTSEL */
-#define _ACMP_INPUTSEL_NEGSEL_APORT4YCH14 0x0000009EUL /**< Mode APORT4YCH14 for ACMP_INPUTSEL */
-#define _ACMP_INPUTSEL_NEGSEL_APORT4XCH15 0x0000009FUL /**< Mode APORT4XCH15 for ACMP_INPUTSEL */
#define _ACMP_INPUTSEL_NEGSEL_APORT4XCH31 0x0000009FUL /**< Mode APORT4XCH31 for ACMP_INPUTSEL */
#define _ACMP_INPUTSEL_NEGSEL_VLP 0x000000FBUL /**< Mode VLP for ACMP_INPUTSEL */
#define _ACMP_INPUTSEL_NEGSEL_VBDIV 0x000000FCUL /**< Mode VBDIV for ACMP_INPUTSEL */
@@ -824,6 +823,8 @@ typedef struct {
#define ACMP_INPUTSEL_NEGSEL_APORT4XCH11 (_ACMP_INPUTSEL_NEGSEL_APORT4XCH11 << 8) /**< Shifted mode APORT4XCH11 for ACMP_INPUTSEL */
#define ACMP_INPUTSEL_NEGSEL_APORT4YCH12 (_ACMP_INPUTSEL_NEGSEL_APORT4YCH12 << 8) /**< Shifted mode APORT4YCH12 for ACMP_INPUTSEL */
#define ACMP_INPUTSEL_NEGSEL_APORT4XCH13 (_ACMP_INPUTSEL_NEGSEL_APORT4XCH13 << 8) /**< Shifted mode APORT4XCH13 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_NEGSEL_APORT4YCH14 (_ACMP_INPUTSEL_NEGSEL_APORT4YCH14 << 8) /**< Shifted mode APORT4YCH14 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_NEGSEL_APORT4XCH15 (_ACMP_INPUTSEL_NEGSEL_APORT4XCH15 << 8) /**< Shifted mode APORT4XCH15 for ACMP_INPUTSEL */
#define ACMP_INPUTSEL_NEGSEL_APORT4YCH16 (_ACMP_INPUTSEL_NEGSEL_APORT4YCH16 << 8) /**< Shifted mode APORT4YCH16 for ACMP_INPUTSEL */
#define ACMP_INPUTSEL_NEGSEL_APORT4XCH17 (_ACMP_INPUTSEL_NEGSEL_APORT4XCH17 << 8) /**< Shifted mode APORT4XCH17 for ACMP_INPUTSEL */
#define ACMP_INPUTSEL_NEGSEL_APORT4YCH18 (_ACMP_INPUTSEL_NEGSEL_APORT4YCH18 << 8) /**< Shifted mode APORT4YCH18 for ACMP_INPUTSEL */
@@ -839,8 +840,6 @@ typedef struct {
#define ACMP_INPUTSEL_NEGSEL_APORT4YCH28 (_ACMP_INPUTSEL_NEGSEL_APORT4YCH28 << 8) /**< Shifted mode APORT4YCH28 for ACMP_INPUTSEL */
#define ACMP_INPUTSEL_NEGSEL_APORT4XCH29 (_ACMP_INPUTSEL_NEGSEL_APORT4XCH29 << 8) /**< Shifted mode APORT4XCH29 for ACMP_INPUTSEL */
#define ACMP_INPUTSEL_NEGSEL_APORT4YCH30 (_ACMP_INPUTSEL_NEGSEL_APORT4YCH30 << 8) /**< Shifted mode APORT4YCH30 for ACMP_INPUTSEL */
-#define ACMP_INPUTSEL_NEGSEL_APORT4YCH14 (_ACMP_INPUTSEL_NEGSEL_APORT4YCH14 << 8) /**< Shifted mode APORT4YCH14 for ACMP_INPUTSEL */
-#define ACMP_INPUTSEL_NEGSEL_APORT4XCH15 (_ACMP_INPUTSEL_NEGSEL_APORT4XCH15 << 8) /**< Shifted mode APORT4XCH15 for ACMP_INPUTSEL */
#define ACMP_INPUTSEL_NEGSEL_APORT4XCH31 (_ACMP_INPUTSEL_NEGSEL_APORT4XCH31 << 8) /**< Shifted mode APORT4XCH31 for ACMP_INPUTSEL */
#define ACMP_INPUTSEL_NEGSEL_VLP (_ACMP_INPUTSEL_NEGSEL_VLP << 8) /**< Shifted mode VLP for ACMP_INPUTSEL */
#define ACMP_INPUTSEL_NEGSEL_VBDIV (_ACMP_INPUTSEL_NEGSEL_VBDIV << 8) /**< Shifted mode VBDIV for ACMP_INPUTSEL */
diff --git a/cpu/efm32/families/efm32pg1b/include/vendor/efm32pg1b_adc.h b/cpu/efm32/families/efm32pg1b/include/vendor/efm32pg1b_adc.h
index e9abcfc606..9172114406 100644
--- a/cpu/efm32/families/efm32pg1b/include/vendor/efm32pg1b_adc.h
+++ b/cpu/efm32/families/efm32pg1b/include/vendor/efm32pg1b_adc.h
@@ -1,10 +1,9 @@
/***************************************************************************//**
* @file
* @brief EFM32PG1B_ADC register and bit field definitions
- * @version 5.8.3
*******************************************************************************
* # License
- * Copyright 2019 Silicon Laboratories Inc. www.silabs.com
+ * Copyright 2020 Silicon Laboratories Inc. www.silabs.com
*******************************************************************************
*
* SPDX-License-Identifier: Zlib
@@ -1323,133 +1322,133 @@ typedef struct {
#define _ADC_SCANMASK_SCANINPUTEN_SHIFT 0 /**< Shift value for ADC_SCANINPUTEN */
#define _ADC_SCANMASK_SCANINPUTEN_MASK 0xFFFFFFFFUL /**< Bit mask for ADC_SCANINPUTEN */
#define _ADC_SCANMASK_SCANINPUTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SCANMASK */
-#define _ADC_SCANMASK_SCANINPUTEN_INPUT0INPUT0NEGSEL 0x00000001UL /**< Mode INPUT0INPUT0NEGSEL for ADC_SCANMASK */
#define _ADC_SCANMASK_SCANINPUTEN_INPUT0 0x00000001UL /**< Mode INPUT0 for ADC_SCANMASK */
-#define _ADC_SCANMASK_SCANINPUTEN_INPUT1 0x00000002UL /**< Mode INPUT1 for ADC_SCANMASK */
+#define _ADC_SCANMASK_SCANINPUTEN_INPUT0INPUT0NEGSEL 0x00000001UL /**< Mode INPUT0INPUT0NEGSEL for ADC_SCANMASK */
#define _ADC_SCANMASK_SCANINPUTEN_INPUT1INPUT2 0x00000002UL /**< Mode INPUT1INPUT2 for ADC_SCANMASK */
+#define _ADC_SCANMASK_SCANINPUTEN_INPUT1 0x00000002UL /**< Mode INPUT1 for ADC_SCANMASK */
#define _ADC_SCANMASK_SCANINPUTEN_INPUT2 0x00000004UL /**< Mode INPUT2 for ADC_SCANMASK */
#define _ADC_SCANMASK_SCANINPUTEN_INPUT2INPUT2NEGSEL 0x00000004UL /**< Mode INPUT2INPUT2NEGSEL for ADC_SCANMASK */
-#define _ADC_SCANMASK_SCANINPUTEN_INPUT3 0x00000008UL /**< Mode INPUT3 for ADC_SCANMASK */
#define _ADC_SCANMASK_SCANINPUTEN_INPUT3INPUT4 0x00000008UL /**< Mode INPUT3INPUT4 for ADC_SCANMASK */
-#define _ADC_SCANMASK_SCANINPUTEN_INPUT4 0x00000010UL /**< Mode INPUT4 for ADC_SCANMASK */
+#define _ADC_SCANMASK_SCANINPUTEN_INPUT3 0x00000008UL /**< Mode INPUT3 for ADC_SCANMASK */
#define _ADC_SCANMASK_SCANINPUTEN_INPUT4INPUT4NEGSEL 0x00000010UL /**< Mode INPUT4INPUT4NEGSEL for ADC_SCANMASK */
+#define _ADC_SCANMASK_SCANINPUTEN_INPUT4 0x00000010UL /**< Mode INPUT4 for ADC_SCANMASK */
#define _ADC_SCANMASK_SCANINPUTEN_INPUT5INPUT6 0x00000020UL /**< Mode INPUT5INPUT6 for ADC_SCANMASK */
#define _ADC_SCANMASK_SCANINPUTEN_INPUT5 0x00000020UL /**< Mode INPUT5 for ADC_SCANMASK */
-#define _ADC_SCANMASK_SCANINPUTEN_INPUT6INPUT6NEGSEL 0x00000040UL /**< Mode INPUT6INPUT6NEGSEL for ADC_SCANMASK */
#define _ADC_SCANMASK_SCANINPUTEN_INPUT6 0x00000040UL /**< Mode INPUT6 for ADC_SCANMASK */
-#define _ADC_SCANMASK_SCANINPUTEN_INPUT7 0x00000080UL /**< Mode INPUT7 for ADC_SCANMASK */
+#define _ADC_SCANMASK_SCANINPUTEN_INPUT6INPUT6NEGSEL 0x00000040UL /**< Mode INPUT6INPUT6NEGSEL for ADC_SCANMASK */
#define _ADC_SCANMASK_SCANINPUTEN_INPUT7INPUT0 0x00000080UL /**< Mode INPUT7INPUT0 for ADC_SCANMASK */
-#define _ADC_SCANMASK_SCANINPUTEN_INPUT8INPUT9 0x00000100UL /**< Mode INPUT8INPUT9 for ADC_SCANMASK */
+#define _ADC_SCANMASK_SCANINPUTEN_INPUT7 0x00000080UL /**< Mode INPUT7 for ADC_SCANMASK */
#define _ADC_SCANMASK_SCANINPUTEN_INPUT8 0x00000100UL /**< Mode INPUT8 for ADC_SCANMASK */
-#define _ADC_SCANMASK_SCANINPUTEN_INPUT9 0x00000200UL /**< Mode INPUT9 for ADC_SCANMASK */
+#define _ADC_SCANMASK_SCANINPUTEN_INPUT8INPUT9 0x00000100UL /**< Mode INPUT8INPUT9 for ADC_SCANMASK */
#define _ADC_SCANMASK_SCANINPUTEN_INPUT9INPUT9NEGSEL 0x00000200UL /**< Mode INPUT9INPUT9NEGSEL for ADC_SCANMASK */
-#define _ADC_SCANMASK_SCANINPUTEN_INPUT10INPUT11 0x00000400UL /**< Mode INPUT10INPUT11 for ADC_SCANMASK */
+#define _ADC_SCANMASK_SCANINPUTEN_INPUT9 0x00000200UL /**< Mode INPUT9 for ADC_SCANMASK */
#define _ADC_SCANMASK_SCANINPUTEN_INPUT10 0x00000400UL /**< Mode INPUT10 for ADC_SCANMASK */
-#define _ADC_SCANMASK_SCANINPUTEN_INPUT11INPUT11NEGSEL 0x00000800UL /**< Mode INPUT11INPUT11NEGSEL for ADC_SCANMASK */
+#define _ADC_SCANMASK_SCANINPUTEN_INPUT10INPUT11 0x00000400UL /**< Mode INPUT10INPUT11 for ADC_SCANMASK */
#define _ADC_SCANMASK_SCANINPUTEN_INPUT11 0x00000800UL /**< Mode INPUT11 for ADC_SCANMASK */
-#define _ADC_SCANMASK_SCANINPUTEN_INPUT12INPUT13 0x00001000UL /**< Mode INPUT12INPUT13 for ADC_SCANMASK */
+#define _ADC_SCANMASK_SCANINPUTEN_INPUT11INPUT11NEGSEL 0x00000800UL /**< Mode INPUT11INPUT11NEGSEL for ADC_SCANMASK */
#define _ADC_SCANMASK_SCANINPUTEN_INPUT12 0x00001000UL /**< Mode INPUT12 for ADC_SCANMASK */
-#define _ADC_SCANMASK_SCANINPUTEN_INPUT13INPUT13NEGSEL 0x00002000UL /**< Mode INPUT13INPUT13NEGSEL for ADC_SCANMASK */
+#define _ADC_SCANMASK_SCANINPUTEN_INPUT12INPUT13 0x00001000UL /**< Mode INPUT12INPUT13 for ADC_SCANMASK */
#define _ADC_SCANMASK_SCANINPUTEN_INPUT13 0x00002000UL /**< Mode INPUT13 for ADC_SCANMASK */
-#define _ADC_SCANMASK_SCANINPUTEN_INPUT14INPUT15 0x00004000UL /**< Mode INPUT14INPUT15 for ADC_SCANMASK */
+#define _ADC_SCANMASK_SCANINPUTEN_INPUT13INPUT13NEGSEL 0x00002000UL /**< Mode INPUT13INPUT13NEGSEL for ADC_SCANMASK */
#define _ADC_SCANMASK_SCANINPUTEN_INPUT14 0x00004000UL /**< Mode INPUT14 for ADC_SCANMASK */
-#define _ADC_SCANMASK_SCANINPUTEN_INPUT15INPUT15NEGSEL 0x00008000UL /**< Mode INPUT15INPUT15NEGSEL for ADC_SCANMASK */
+#define _ADC_SCANMASK_SCANINPUTEN_INPUT14INPUT15 0x00004000UL /**< Mode INPUT14INPUT15 for ADC_SCANMASK */
#define _ADC_SCANMASK_SCANINPUTEN_INPUT15 0x00008000UL /**< Mode INPUT15 for ADC_SCANMASK */
-#define _ADC_SCANMASK_SCANINPUTEN_INPUT16INPUT17 0x00010000UL /**< Mode INPUT16INPUT17 for ADC_SCANMASK */
+#define _ADC_SCANMASK_SCANINPUTEN_INPUT15INPUT15NEGSEL 0x00008000UL /**< Mode INPUT15INPUT15NEGSEL for ADC_SCANMASK */
#define _ADC_SCANMASK_SCANINPUTEN_INPUT16 0x00010000UL /**< Mode INPUT16 for ADC_SCANMASK */
-#define _ADC_SCANMASK_SCANINPUTEN_INPUT17INPUT18 0x00020000UL /**< Mode INPUT17INPUT18 for ADC_SCANMASK */
+#define _ADC_SCANMASK_SCANINPUTEN_INPUT16INPUT17 0x00010000UL /**< Mode INPUT16INPUT17 for ADC_SCANMASK */
#define _ADC_SCANMASK_SCANINPUTEN_INPUT17 0x00020000UL /**< Mode INPUT17 for ADC_SCANMASK */
+#define _ADC_SCANMASK_SCANINPUTEN_INPUT17INPUT18 0x00020000UL /**< Mode INPUT17INPUT18 for ADC_SCANMASK */
#define _ADC_SCANMASK_SCANINPUTEN_INPUT18INPUT19 0x00040000UL /**< Mode INPUT18INPUT19 for ADC_SCANMASK */
#define _ADC_SCANMASK_SCANINPUTEN_INPUT18 0x00040000UL /**< Mode INPUT18 for ADC_SCANMASK */
#define _ADC_SCANMASK_SCANINPUTEN_INPUT19 0x00080000UL /**< Mode INPUT19 for ADC_SCANMASK */
#define _ADC_SCANMASK_SCANINPUTEN_INPUT19INPUT20 0x00080000UL /**< Mode INPUT19INPUT20 for ADC_SCANMASK */
#define _ADC_SCANMASK_SCANINPUTEN_INPUT20INPUT21 0x00100000UL /**< Mode INPUT20INPUT21 for ADC_SCANMASK */
#define _ADC_SCANMASK_SCANINPUTEN_INPUT20 0x00100000UL /**< Mode INPUT20 for ADC_SCANMASK */
-#define _ADC_SCANMASK_SCANINPUTEN_INPUT21 0x00200000UL /**< Mode INPUT21 for ADC_SCANMASK */
#define _ADC_SCANMASK_SCANINPUTEN_INPUT21INPUT22 0x00200000UL /**< Mode INPUT21INPUT22 for ADC_SCANMASK */
+#define _ADC_SCANMASK_SCANINPUTEN_INPUT21 0x00200000UL /**< Mode INPUT21 for ADC_SCANMASK */
#define _ADC_SCANMASK_SCANINPUTEN_INPUT22INPUT23 0x00400000UL /**< Mode INPUT22INPUT23 for ADC_SCANMASK */
#define _ADC_SCANMASK_SCANINPUTEN_INPUT22 0x00400000UL /**< Mode INPUT22 for ADC_SCANMASK */
-#define _ADC_SCANMASK_SCANINPUTEN_INPUT23INPUT16 0x00800000UL /**< Mode INPUT23INPUT16 for ADC_SCANMASK */
#define _ADC_SCANMASK_SCANINPUTEN_INPUT23 0x00800000UL /**< Mode INPUT23 for ADC_SCANMASK */
-#define _ADC_SCANMASK_SCANINPUTEN_INPUT24 0x01000000UL /**< Mode INPUT24 for ADC_SCANMASK */
+#define _ADC_SCANMASK_SCANINPUTEN_INPUT23INPUT16 0x00800000UL /**< Mode INPUT23INPUT16 for ADC_SCANMASK */
#define _ADC_SCANMASK_SCANINPUTEN_INPUT24INPUT25 0x01000000UL /**< Mode INPUT24INPUT25 for ADC_SCANMASK */
-#define _ADC_SCANMASK_SCANINPUTEN_INPUT25INPUT26 0x02000000UL /**< Mode INPUT25INPUT26 for ADC_SCANMASK */
+#define _ADC_SCANMASK_SCANINPUTEN_INPUT24 0x01000000UL /**< Mode INPUT24 for ADC_SCANMASK */
#define _ADC_SCANMASK_SCANINPUTEN_INPUT25 0x02000000UL /**< Mode INPUT25 for ADC_SCANMASK */
-#define _ADC_SCANMASK_SCANINPUTEN_INPUT26 0x04000000UL /**< Mode INPUT26 for ADC_SCANMASK */
+#define _ADC_SCANMASK_SCANINPUTEN_INPUT25INPUT26 0x02000000UL /**< Mode INPUT25INPUT26 for ADC_SCANMASK */
#define _ADC_SCANMASK_SCANINPUTEN_INPUT26INPUT27 0x04000000UL /**< Mode INPUT26INPUT27 for ADC_SCANMASK */
-#define _ADC_SCANMASK_SCANINPUTEN_INPUT27INPUT28 0x08000000UL /**< Mode INPUT27INPUT28 for ADC_SCANMASK */
+#define _ADC_SCANMASK_SCANINPUTEN_INPUT26 0x04000000UL /**< Mode INPUT26 for ADC_SCANMASK */
#define _ADC_SCANMASK_SCANINPUTEN_INPUT27 0x08000000UL /**< Mode INPUT27 for ADC_SCANMASK */
-#define _ADC_SCANMASK_SCANINPUTEN_INPUT28INPUT29 0x10000000UL /**< Mode INPUT28INPUT29 for ADC_SCANMASK */
+#define _ADC_SCANMASK_SCANINPUTEN_INPUT27INPUT28 0x08000000UL /**< Mode INPUT27INPUT28 for ADC_SCANMASK */
#define _ADC_SCANMASK_SCANINPUTEN_INPUT28 0x10000000UL /**< Mode INPUT28 for ADC_SCANMASK */
+#define _ADC_SCANMASK_SCANINPUTEN_INPUT28INPUT29 0x10000000UL /**< Mode INPUT28INPUT29 for ADC_SCANMASK */
#define _ADC_SCANMASK_SCANINPUTEN_INPUT29 0x20000000UL /**< Mode INPUT29 for ADC_SCANMASK */
#define _ADC_SCANMASK_SCANINPUTEN_INPUT29INPUT30 0x20000000UL /**< Mode INPUT29INPUT30 for ADC_SCANMASK */
-#define _ADC_SCANMASK_SCANINPUTEN_INPUT30 0x40000000UL /**< Mode INPUT30 for ADC_SCANMASK */
#define _ADC_SCANMASK_SCANINPUTEN_INPUT30INPUT31 0x40000000UL /**< Mode INPUT30INPUT31 for ADC_SCANMASK */
+#define _ADC_SCANMASK_SCANINPUTEN_INPUT30 0x40000000UL /**< Mode INPUT30 for ADC_SCANMASK */
#define _ADC_SCANMASK_SCANINPUTEN_INPUT31INPUT24 0x80000000UL /**< Mode INPUT31INPUT24 for ADC_SCANMASK */
#define _ADC_SCANMASK_SCANINPUTEN_INPUT31 0x80000000UL /**< Mode INPUT31 for ADC_SCANMASK */
#define ADC_SCANMASK_SCANINPUTEN_DEFAULT (_ADC_SCANMASK_SCANINPUTEN_DEFAULT << 0) /**< Shifted mode DEFAULT for ADC_SCANMASK */
-#define ADC_SCANMASK_SCANINPUTEN_INPUT0INPUT0NEGSEL (_ADC_SCANMASK_SCANINPUTEN_INPUT0INPUT0NEGSEL << 0) /**< Shifted mode INPUT0INPUT0NEGSEL for ADC_SCANMASK */
#define ADC_SCANMASK_SCANINPUTEN_INPUT0 (_ADC_SCANMASK_SCANINPUTEN_INPUT0 << 0) /**< Shifted mode INPUT0 for ADC_SCANMASK */
-#define ADC_SCANMASK_SCANINPUTEN_INPUT1 (_ADC_SCANMASK_SCANINPUTEN_INPUT1 << 0) /**< Shifted mode INPUT1 for ADC_SCANMASK */
+#define ADC_SCANMASK_SCANINPUTEN_INPUT0INPUT0NEGSEL (_ADC_SCANMASK_SCANINPUTEN_INPUT0INPUT0NEGSEL << 0) /**< Shifted mode INPUT0INPUT0NEGSEL for ADC_SCANMASK */
#define ADC_SCANMASK_SCANINPUTEN_INPUT1INPUT2 (_ADC_SCANMASK_SCANINPUTEN_INPUT1INPUT2 << 0) /**< Shifted mode INPUT1INPUT2 for ADC_SCANMASK */
+#define ADC_SCANMASK_SCANINPUTEN_INPUT1 (_ADC_SCANMASK_SCANINPUTEN_INPUT1 << 0) /**< Shifted mode INPUT1 for ADC_SCANMASK */
#define ADC_SCANMASK_SCANINPUTEN_INPUT2 (_ADC_SCANMASK_SCANINPUTEN_INPUT2 << 0) /**< Shifted mode INPUT2 for ADC_SCANMASK */
#define ADC_SCANMASK_SCANINPUTEN_INPUT2INPUT2NEGSEL (_ADC_SCANMASK_SCANINPUTEN_INPUT2INPUT2NEGSEL << 0) /**< Shifted mode INPUT2INPUT2NEGSEL for ADC_SCANMASK */
-#define ADC_SCANMASK_SCANINPUTEN_INPUT3 (_ADC_SCANMASK_SCANINPUTEN_INPUT3 << 0) /**< Shifted mode INPUT3 for ADC_SCANMASK */
#define ADC_SCANMASK_SCANINPUTEN_INPUT3INPUT4 (_ADC_SCANMASK_SCANINPUTEN_INPUT3INPUT4 << 0) /**< Shifted mode INPUT3INPUT4 for ADC_SCANMASK */
-#define ADC_SCANMASK_SCANINPUTEN_INPUT4 (_ADC_SCANMASK_SCANINPUTEN_INPUT4 << 0) /**< Shifted mode INPUT4 for ADC_SCANMASK */
+#define ADC_SCANMASK_SCANINPUTEN_INPUT3 (_ADC_SCANMASK_SCANINPUTEN_INPUT3 << 0) /**< Shifted mode INPUT3 for ADC_SCANMASK */
#define ADC_SCANMASK_SCANINPUTEN_INPUT4INPUT4NEGSEL (_ADC_SCANMASK_SCANINPUTEN_INPUT4INPUT4NEGSEL << 0) /**< Shifted mode INPUT4INPUT4NEGSEL for ADC_SCANMASK */
+#define ADC_SCANMASK_SCANINPUTEN_INPUT4 (_ADC_SCANMASK_SCANINPUTEN_INPUT4 << 0) /**< Shifted mode INPUT4 for ADC_SCANMASK */
#define ADC_SCANMASK_SCANINPUTEN_INPUT5INPUT6 (_ADC_SCANMASK_SCANINPUTEN_INPUT5INPUT6 << 0) /**< Shifted mode INPUT5INPUT6 for ADC_SCANMASK */
#define ADC_SCANMASK_SCANINPUTEN_INPUT5 (_ADC_SCANMASK_SCANINPUTEN_INPUT5 << 0) /**< Shifted mode INPUT5 for ADC_SCANMASK */
-#define ADC_SCANMASK_SCANINPUTEN_INPUT6INPUT6NEGSEL (_ADC_SCANMASK_SCANINPUTEN_INPUT6INPUT6NEGSEL << 0) /**< Shifted mode INPUT6INPUT6NEGSEL for ADC_SCANMASK */
#define ADC_SCANMASK_SCANINPUTEN_INPUT6 (_ADC_SCANMASK_SCANINPUTEN_INPUT6 << 0) /**< Shifted mode INPUT6 for ADC_SCANMASK */
-#define ADC_SCANMASK_SCANINPUTEN_INPUT7 (_ADC_SCANMASK_SCANINPUTEN_INPUT7 << 0) /**< Shifted mode INPUT7 for ADC_SCANMASK */
+#define ADC_SCANMASK_SCANINPUTEN_INPUT6INPUT6NEGSEL (_ADC_SCANMASK_SCANINPUTEN_INPUT6INPUT6NEGSEL << 0) /**< Shifted mode INPUT6INPUT6NEGSEL for ADC_SCANMASK */
#define ADC_SCANMASK_SCANINPUTEN_INPUT7INPUT0 (_ADC_SCANMASK_SCANINPUTEN_INPUT7INPUT0 << 0) /**< Shifted mode INPUT7INPUT0 for ADC_SCANMASK */
-#define ADC_SCANMASK_SCANINPUTEN_INPUT8INPUT9 (_ADC_SCANMASK_SCANINPUTEN_INPUT8INPUT9 << 0) /**< Shifted mode INPUT8INPUT9 for ADC_SCANMASK */
+#define ADC_SCANMASK_SCANINPUTEN_INPUT7 (_ADC_SCANMASK_SCANINPUTEN_INPUT7 << 0) /**< Shifted mode INPUT7 for ADC_SCANMASK */
#define ADC_SCANMASK_SCANINPUTEN_INPUT8 (_ADC_SCANMASK_SCANINPUTEN_INPUT8 << 0) /**< Shifted mode INPUT8 for ADC_SCANMASK */
-#define ADC_SCANMASK_SCANINPUTEN_INPUT9 (_ADC_SCANMASK_SCANINPUTEN_INPUT9 << 0) /**< Shifted mode INPUT9 for ADC_SCANMASK */
+#define ADC_SCANMASK_SCANINPUTEN_INPUT8INPUT9 (_ADC_SCANMASK_SCANINPUTEN_INPUT8INPUT9 << 0) /**< Shifted mode INPUT8INPUT9 for ADC_SCANMASK */
#define ADC_SCANMASK_SCANINPUTEN_INPUT9INPUT9NEGSEL (_ADC_SCANMASK_SCANINPUTEN_INPUT9INPUT9NEGSEL << 0) /**< Shifted mode INPUT9INPUT9NEGSEL for ADC_SCANMASK */
-#define ADC_SCANMASK_SCANINPUTEN_INPUT10INPUT11 (_ADC_SCANMASK_SCANINPUTEN_INPUT10INPUT11 << 0) /**< Shifted mode INPUT10INPUT11 for ADC_SCANMASK */
+#define ADC_SCANMASK_SCANINPUTEN_INPUT9 (_ADC_SCANMASK_SCANINPUTEN_INPUT9 << 0) /**< Shifted mode INPUT9 for ADC_SCANMASK */
#define ADC_SCANMASK_SCANINPUTEN_INPUT10 (_ADC_SCANMASK_SCANINPUTEN_INPUT10 << 0) /**< Shifted mode INPUT10 for ADC_SCANMASK */
-#define ADC_SCANMASK_SCANINPUTEN_INPUT11INPUT11NEGSEL (_ADC_SCANMASK_SCANINPUTEN_INPUT11INPUT11NEGSEL << 0) /**< Shifted mode INPUT11INPUT11NEGSEL for ADC_SCANMASK */
+#define ADC_SCANMASK_SCANINPUTEN_INPUT10INPUT11 (_ADC_SCANMASK_SCANINPUTEN_INPUT10INPUT11 << 0) /**< Shifted mode INPUT10INPUT11 for ADC_SCANMASK */
#define ADC_SCANMASK_SCANINPUTEN_INPUT11 (_ADC_SCANMASK_SCANINPUTEN_INPUT11 << 0) /**< Shifted mode INPUT11 for ADC_SCANMASK */
-#define ADC_SCANMASK_SCANINPUTEN_INPUT12INPUT13 (_ADC_SCANMASK_SCANINPUTEN_INPUT12INPUT13 << 0) /**< Shifted mode INPUT12INPUT13 for ADC_SCANMASK */
+#define ADC_SCANMASK_SCANINPUTEN_INPUT11INPUT11NEGSEL (_ADC_SCANMASK_SCANINPUTEN_INPUT11INPUT11NEGSEL << 0) /**< Shifted mode INPUT11INPUT11NEGSEL for ADC_SCANMASK */
#define ADC_SCANMASK_SCANINPUTEN_INPUT12 (_ADC_SCANMASK_SCANINPUTEN_INPUT12 << 0) /**< Shifted mode INPUT12 for ADC_SCANMASK */
-#define ADC_SCANMASK_SCANINPUTEN_INPUT13INPUT13NEGSEL (_ADC_SCANMASK_SCANINPUTEN_INPUT13INPUT13NEGSEL << 0) /**< Shifted mode INPUT13INPUT13NEGSEL for ADC_SCANMASK */
+#define ADC_SCANMASK_SCANINPUTEN_INPUT12INPUT13 (_ADC_SCANMASK_SCANINPUTEN_INPUT12INPUT13 << 0) /**< Shifted mode INPUT12INPUT13 for ADC_SCANMASK */
#define ADC_SCANMASK_SCANINPUTEN_INPUT13 (_ADC_SCANMASK_SCANINPUTEN_INPUT13 << 0) /**< Shifted mode INPUT13 for ADC_SCANMASK */
-#define ADC_SCANMASK_SCANINPUTEN_INPUT14INPUT15 (_ADC_SCANMASK_SCANINPUTEN_INPUT14INPUT15 << 0) /**< Shifted mode INPUT14INPUT15 for ADC_SCANMASK */
+#define ADC_SCANMASK_SCANINPUTEN_INPUT13INPUT13NEGSEL (_ADC_SCANMASK_SCANINPUTEN_INPUT13INPUT13NEGSEL << 0) /**< Shifted mode INPUT13INPUT13NEGSEL for ADC_SCANMASK */
#define ADC_SCANMASK_SCANINPUTEN_INPUT14 (_ADC_SCANMASK_SCANINPUTEN_INPUT14 << 0) /**< Shifted mode INPUT14 for ADC_SCANMASK */
-#define ADC_SCANMASK_SCANINPUTEN_INPUT15INPUT15NEGSEL (_ADC_SCANMASK_SCANINPUTEN_INPUT15INPUT15NEGSEL << 0) /**< Shifted mode INPUT15INPUT15NEGSEL for ADC_SCANMASK */
+#define ADC_SCANMASK_SCANINPUTEN_INPUT14INPUT15 (_ADC_SCANMASK_SCANINPUTEN_INPUT14INPUT15 << 0) /**< Shifted mode INPUT14INPUT15 for ADC_SCANMASK */
#define ADC_SCANMASK_SCANINPUTEN_INPUT15 (_ADC_SCANMASK_SCANINPUTEN_INPUT15 << 0) /**< Shifted mode INPUT15 for ADC_SCANMASK */
-#define ADC_SCANMASK_SCANINPUTEN_INPUT16INPUT17 (_ADC_SCANMASK_SCANINPUTEN_INPUT16INPUT17 << 0) /**< Shifted mode INPUT16INPUT17 for ADC_SCANMASK */
+#define ADC_SCANMASK_SCANINPUTEN_INPUT15INPUT15NEGSEL (_ADC_SCANMASK_SCANINPUTEN_INPUT15INPUT15NEGSEL << 0) /**< Shifted mode INPUT15INPUT15NEGSEL for ADC_SCANMASK */
#define ADC_SCANMASK_SCANINPUTEN_INPUT16 (_ADC_SCANMASK_SCANINPUTEN_INPUT16 << 0) /**< Shifted mode INPUT16 for ADC_SCANMASK */
-#define ADC_SCANMASK_SCANINPUTEN_INPUT17INPUT18 (_ADC_SCANMASK_SCANINPUTEN_INPUT17INPUT18 << 0) /**< Shifted mode INPUT17INPUT18 for ADC_SCANMASK */
+#define ADC_SCANMASK_SCANINPUTEN_INPUT16INPUT17 (_ADC_SCANMASK_SCANINPUTEN_INPUT16INPUT17 << 0) /**< Shifted mode INPUT16INPUT17 for ADC_SCANMASK */
#define ADC_SCANMASK_SCANINPUTEN_INPUT17 (_ADC_SCANMASK_SCANINPUTEN_INPUT17 << 0) /**< Shifted mode INPUT17 for ADC_SCANMASK */
+#define ADC_SCANMASK_SCANINPUTEN_INPUT17INPUT18 (_ADC_SCANMASK_SCANINPUTEN_INPUT17INPUT18 << 0) /**< Shifted mode INPUT17INPUT18 for ADC_SCANMASK */
#define ADC_SCANMASK_SCANINPUTEN_INPUT18INPUT19 (_ADC_SCANMASK_SCANINPUTEN_INPUT18INPUT19 << 0) /**< Shifted mode INPUT18INPUT19 for ADC_SCANMASK */
#define ADC_SCANMASK_SCANINPUTEN_INPUT18 (_ADC_SCANMASK_SCANINPUTEN_INPUT18 << 0) /**< Shifted mode INPUT18 for ADC_SCANMASK */
#define ADC_SCANMASK_SCANINPUTEN_INPUT19 (_ADC_SCANMASK_SCANINPUTEN_INPUT19 << 0) /**< Shifted mode INPUT19 for ADC_SCANMASK */
#define ADC_SCANMASK_SCANINPUTEN_INPUT19INPUT20 (_ADC_SCANMASK_SCANINPUTEN_INPUT19INPUT20 << 0) /**< Shifted mode INPUT19INPUT20 for ADC_SCANMASK */
#define ADC_SCANMASK_SCANINPUTEN_INPUT20INPUT21 (_ADC_SCANMASK_SCANINPUTEN_INPUT20INPUT21 << 0) /**< Shifted mode INPUT20INPUT21 for ADC_SCANMASK */
#define ADC_SCANMASK_SCANINPUTEN_INPUT20 (_ADC_SCANMASK_SCANINPUTEN_INPUT20 << 0) /**< Shifted mode INPUT20 for ADC_SCANMASK */
-#define ADC_SCANMASK_SCANINPUTEN_INPUT21 (_ADC_SCANMASK_SCANINPUTEN_INPUT21 << 0) /**< Shifted mode INPUT21 for ADC_SCANMASK */
#define ADC_SCANMASK_SCANINPUTEN_INPUT21INPUT22 (_ADC_SCANMASK_SCANINPUTEN_INPUT21INPUT22 << 0) /**< Shifted mode INPUT21INPUT22 for ADC_SCANMASK */
+#define ADC_SCANMASK_SCANINPUTEN_INPUT21 (_ADC_SCANMASK_SCANINPUTEN_INPUT21 << 0) /**< Shifted mode INPUT21 for ADC_SCANMASK */
#define ADC_SCANMASK_SCANINPUTEN_INPUT22INPUT23 (_ADC_SCANMASK_SCANINPUTEN_INPUT22INPUT23 << 0) /**< Shifted mode INPUT22INPUT23 for ADC_SCANMASK */
#define ADC_SCANMASK_SCANINPUTEN_INPUT22 (_ADC_SCANMASK_SCANINPUTEN_INPUT22 << 0) /**< Shifted mode INPUT22 for ADC_SCANMASK */
-#define ADC_SCANMASK_SCANINPUTEN_INPUT23INPUT16 (_ADC_SCANMASK_SCANINPUTEN_INPUT23INPUT16 << 0) /**< Shifted mode INPUT23INPUT16 for ADC_SCANMASK */
#define ADC_SCANMASK_SCANINPUTEN_INPUT23 (_ADC_SCANMASK_SCANINPUTEN_INPUT23 << 0) /**< Shifted mode INPUT23 for ADC_SCANMASK */
-#define ADC_SCANMASK_SCANINPUTEN_INPUT24 (_ADC_SCANMASK_SCANINPUTEN_INPUT24 << 0) /**< Shifted mode INPUT24 for ADC_SCANMASK */
+#define ADC_SCANMASK_SCANINPUTEN_INPUT23INPUT16 (_ADC_SCANMASK_SCANINPUTEN_INPUT23INPUT16 << 0) /**< Shifted mode INPUT23INPUT16 for ADC_SCANMASK */
#define ADC_SCANMASK_SCANINPUTEN_INPUT24INPUT25 (_ADC_SCANMASK_SCANINPUTEN_INPUT24INPUT25 << 0) /**< Shifted mode INPUT24INPUT25 for ADC_SCANMASK */
-#define ADC_SCANMASK_SCANINPUTEN_INPUT25INPUT26 (_ADC_SCANMASK_SCANINPUTEN_INPUT25INPUT26 << 0) /**< Shifted mode INPUT25INPUT26 for ADC_SCANMASK */
+#define ADC_SCANMASK_SCANINPUTEN_INPUT24 (_ADC_SCANMASK_SCANINPUTEN_INPUT24 << 0) /**< Shifted mode INPUT24 for ADC_SCANMASK */
#define ADC_SCANMASK_SCANINPUTEN_INPUT25 (_ADC_SCANMASK_SCANINPUTEN_INPUT25 << 0) /**< Shifted mode INPUT25 for ADC_SCANMASK */
-#define ADC_SCANMASK_SCANINPUTEN_INPUT26 (_ADC_SCANMASK_SCANINPUTEN_INPUT26 << 0) /**< Shifted mode INPUT26 for ADC_SCANMASK */
+#define ADC_SCANMASK_SCANINPUTEN_INPUT25INPUT26 (_ADC_SCANMASK_SCANINPUTEN_INPUT25INPUT26 << 0) /**< Shifted mode INPUT25INPUT26 for ADC_SCANMASK */
#define ADC_SCANMASK_SCANINPUTEN_INPUT26INPUT27 (_ADC_SCANMASK_SCANINPUTEN_INPUT26INPUT27 << 0) /**< Shifted mode INPUT26INPUT27 for ADC_SCANMASK */
-#define ADC_SCANMASK_SCANINPUTEN_INPUT27INPUT28 (_ADC_SCANMASK_SCANINPUTEN_INPUT27INPUT28 << 0) /**< Shifted mode INPUT27INPUT28 for ADC_SCANMASK */
+#define ADC_SCANMASK_SCANINPUTEN_INPUT26 (_ADC_SCANMASK_SCANINPUTEN_INPUT26 << 0) /**< Shifted mode INPUT26 for ADC_SCANMASK */
#define ADC_SCANMASK_SCANINPUTEN_INPUT27 (_ADC_SCANMASK_SCANINPUTEN_INPUT27 << 0) /**< Shifted mode INPUT27 for ADC_SCANMASK */
-#define ADC_SCANMASK_SCANINPUTEN_INPUT28INPUT29 (_ADC_SCANMASK_SCANINPUTEN_INPUT28INPUT29 << 0) /**< Shifted mode INPUT28INPUT29 for ADC_SCANMASK */
+#define ADC_SCANMASK_SCANINPUTEN_INPUT27INPUT28 (_ADC_SCANMASK_SCANINPUTEN_INPUT27INPUT28 << 0) /**< Shifted mode INPUT27INPUT28 for ADC_SCANMASK */
#define ADC_SCANMASK_SCANINPUTEN_INPUT28 (_ADC_SCANMASK_SCANINPUTEN_INPUT28 << 0) /**< Shifted mode INPUT28 for ADC_SCANMASK */
+#define ADC_SCANMASK_SCANINPUTEN_INPUT28INPUT29 (_ADC_SCANMASK_SCANINPUTEN_INPUT28INPUT29 << 0) /**< Shifted mode INPUT28INPUT29 for ADC_SCANMASK */
#define ADC_SCANMASK_SCANINPUTEN_INPUT29 (_ADC_SCANMASK_SCANINPUTEN_INPUT29 << 0) /**< Shifted mode INPUT29 for ADC_SCANMASK */
#define ADC_SCANMASK_SCANINPUTEN_INPUT29INPUT30 (_ADC_SCANMASK_SCANINPUTEN_INPUT29INPUT30 << 0) /**< Shifted mode INPUT29INPUT30 for ADC_SCANMASK */
-#define ADC_SCANMASK_SCANINPUTEN_INPUT30 (_ADC_SCANMASK_SCANINPUTEN_INPUT30 << 0) /**< Shifted mode INPUT30 for ADC_SCANMASK */
#define ADC_SCANMASK_SCANINPUTEN_INPUT30INPUT31 (_ADC_SCANMASK_SCANINPUTEN_INPUT30INPUT31 << 0) /**< Shifted mode INPUT30INPUT31 for ADC_SCANMASK */
+#define ADC_SCANMASK_SCANINPUTEN_INPUT30 (_ADC_SCANMASK_SCANINPUTEN_INPUT30 << 0) /**< Shifted mode INPUT30 for ADC_SCANMASK */
#define ADC_SCANMASK_SCANINPUTEN_INPUT31INPUT24 (_ADC_SCANMASK_SCANINPUTEN_INPUT31INPUT24 << 0) /**< Shifted mode INPUT31INPUT24 for ADC_SCANMASK */
#define ADC_SCANMASK_SCANINPUTEN_INPUT31 (_ADC_SCANMASK_SCANINPUTEN_INPUT31 << 0) /**< Shifted mode INPUT31 for ADC_SCANMASK */
diff --git a/cpu/efm32/families/efm32pg1b/include/vendor/efm32pg1b_af_pins.h b/cpu/efm32/families/efm32pg1b/include/vendor/efm32pg1b_af_pins.h
index abb30d40d5..9fa64fe2ca 100644
--- a/cpu/efm32/families/efm32pg1b/include/vendor/efm32pg1b_af_pins.h
+++ b/cpu/efm32/families/efm32pg1b/include/vendor/efm32pg1b_af_pins.h
@@ -1,10 +1,9 @@
/***************************************************************************//**
* @file
* @brief EFM32PG1B_AF_PINS register and bit field definitions
- * @version 5.8.3
*******************************************************************************
* # License
- * Copyright 2019 Silicon Laboratories Inc. www.silabs.com
+ * Copyright 2020 Silicon Laboratories Inc. www.silabs.com
*******************************************************************************
*
* SPDX-License-Identifier: Zlib
diff --git a/cpu/efm32/families/efm32pg1b/include/vendor/efm32pg1b_af_ports.h b/cpu/efm32/families/efm32pg1b/include/vendor/efm32pg1b_af_ports.h
index 3064fa3425..00e9c018cf 100644
--- a/cpu/efm32/families/efm32pg1b/include/vendor/efm32pg1b_af_ports.h
+++ b/cpu/efm32/families/efm32pg1b/include/vendor/efm32pg1b_af_ports.h
@@ -1,10 +1,9 @@
/***************************************************************************//**
* @file
* @brief EFM32PG1B_AF_PORTS register and bit field definitions
- * @version 5.8.3
*******************************************************************************
* # License
- * Copyright 2019 Silicon Laboratories Inc. www.silabs.com
+ * Copyright 2020 Silicon Laboratories Inc. www.silabs.com
*******************************************************************************
*
* SPDX-License-Identifier: Zlib
diff --git a/cpu/efm32/families/efm32pg1b/include/vendor/efm32pg1b_cmu.h b/cpu/efm32/families/efm32pg1b/include/vendor/efm32pg1b_cmu.h
index e0e84395a2..1c9bf5a377 100644
--- a/cpu/efm32/families/efm32pg1b/include/vendor/efm32pg1b_cmu.h
+++ b/cpu/efm32/families/efm32pg1b/include/vendor/efm32pg1b_cmu.h
@@ -1,10 +1,9 @@
/***************************************************************************//**
* @file
* @brief EFM32PG1B_CMU register and bit field definitions
- * @version 5.8.3
*******************************************************************************
* # License
- * Copyright 2019 Silicon Laboratories Inc. www.silabs.com
+ * Copyright 2020 Silicon Laboratories Inc. www.silabs.com
*******************************************************************************
*
* SPDX-License-Identifier: Zlib
@@ -1774,13 +1773,13 @@ typedef struct {
#define _CMU_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for CMU_LOCKKEY */
#define _CMU_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for CMU_LOCKKEY */
#define _CMU_LOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LOCK */
-#define _CMU_LOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for CMU_LOCK */
#define _CMU_LOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for CMU_LOCK */
+#define _CMU_LOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for CMU_LOCK */
#define _CMU_LOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for CMU_LOCK */
#define _CMU_LOCK_LOCKKEY_UNLOCK 0x0000580EUL /**< Mode UNLOCK for CMU_LOCK */
#define CMU_LOCK_LOCKKEY_DEFAULT (_CMU_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LOCK */
-#define CMU_LOCK_LOCKKEY_LOCK (_CMU_LOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for CMU_LOCK */
#define CMU_LOCK_LOCKKEY_UNLOCKED (_CMU_LOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for CMU_LOCK */
+#define CMU_LOCK_LOCKKEY_LOCK (_CMU_LOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for CMU_LOCK */
#define CMU_LOCK_LOCKKEY_LOCKED (_CMU_LOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for CMU_LOCK */
#define CMU_LOCK_LOCKKEY_UNLOCK (_CMU_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for CMU_LOCK */
diff --git a/cpu/efm32/families/efm32pg1b/include/vendor/efm32pg1b_cryotimer.h b/cpu/efm32/families/efm32pg1b/include/vendor/efm32pg1b_cryotimer.h
index 0853538028..e996fa20d6 100644
--- a/cpu/efm32/families/efm32pg1b/include/vendor/efm32pg1b_cryotimer.h
+++ b/cpu/efm32/families/efm32pg1b/include/vendor/efm32pg1b_cryotimer.h
@@ -1,10 +1,9 @@
/***************************************************************************//**
* @file
* @brief EFM32PG1B_CRYOTIMER register and bit field definitions
- * @version 5.8.3
*******************************************************************************
* # License
- * Copyright 2019 Silicon Laboratories Inc. www.silabs.com
+ * Copyright 2020 Silicon Laboratories Inc. www.silabs.com
*******************************************************************************
*
* SPDX-License-Identifier: Zlib
diff --git a/cpu/efm32/families/efm32pg1b/include/vendor/efm32pg1b_crypto.h b/cpu/efm32/families/efm32pg1b/include/vendor/efm32pg1b_crypto.h
index 7c3620879e..f0573a04f6 100644
--- a/cpu/efm32/families/efm32pg1b/include/vendor/efm32pg1b_crypto.h
+++ b/cpu/efm32/families/efm32pg1b/include/vendor/efm32pg1b_crypto.h
@@ -1,10 +1,9 @@
/***************************************************************************//**
* @file
* @brief EFM32PG1B_CRYPTO register and bit field definitions
- * @version 5.8.3
*******************************************************************************
* # License
- * Copyright 2019 Silicon Laboratories Inc. www.silabs.com
+ * Copyright 2020 Silicon Laboratories Inc. www.silabs.com
*******************************************************************************
*
* SPDX-License-Identifier: Zlib
diff --git a/cpu/efm32/families/efm32pg1b/include/vendor/efm32pg1b_devinfo.h b/cpu/efm32/families/efm32pg1b/include/vendor/efm32pg1b_devinfo.h
index b57d79517c..aab4212274 100644
--- a/cpu/efm32/families/efm32pg1b/include/vendor/efm32pg1b_devinfo.h
+++ b/cpu/efm32/families/efm32pg1b/include/vendor/efm32pg1b_devinfo.h
@@ -1,10 +1,9 @@
/***************************************************************************//**
* @file
* @brief EFM32PG1B_DEVINFO register and bit field definitions
- * @version 5.8.3
*******************************************************************************
* # License
- * Copyright 2019 Silicon Laboratories Inc. www.silabs.com
+ * Copyright 2020 Silicon Laboratories Inc. www.silabs.com
*******************************************************************************
*
* SPDX-License-Identifier: Zlib
@@ -214,6 +213,8 @@ typedef struct {
#define _DEVINFO_PART_DEVICE_FAMILY_EFR32BG13B 0x0000002CUL /**< Mode EFR32BG13B for DEVINFO_PART */
#define _DEVINFO_PART_DEVICE_FAMILY_EFR32BG13V 0x0000002DUL /**< Mode EFR32BG13V for DEVINFO_PART */
#define _DEVINFO_PART_DEVICE_FAMILY_EFR32ZG13P 0x0000002EUL /**< Mode EFR32ZG13P for DEVINFO_PART */
+#define _DEVINFO_PART_DEVICE_FAMILY_EFR32ZG13L 0x0000002FUL /**< Mode EFR32ZG13L for DEVINFO_PART */
+#define _DEVINFO_PART_DEVICE_FAMILY_EFR32ZG13S 0x00000030UL /**< Mode EFR32ZG13S for DEVINFO_PART */
#define _DEVINFO_PART_DEVICE_FAMILY_EFR32FG13P 0x00000031UL /**< Mode EFR32FG13P for DEVINFO_PART */
#define _DEVINFO_PART_DEVICE_FAMILY_EFR32FG13B 0x00000032UL /**< Mode EFR32FG13B for DEVINFO_PART */
#define _DEVINFO_PART_DEVICE_FAMILY_EFR32FG13V 0x00000033UL /**< Mode EFR32FG13V for DEVINFO_PART */
@@ -231,16 +232,16 @@ typedef struct {
#define _DEVINFO_PART_DEVICE_FAMILY_G 0x00000047UL /**< Mode G for DEVINFO_PART */
#define _DEVINFO_PART_DEVICE_FAMILY_EFM32GG 0x00000048UL /**< Mode EFM32GG for DEVINFO_PART */
#define _DEVINFO_PART_DEVICE_FAMILY_GG 0x00000048UL /**< Mode GG for DEVINFO_PART */
-#define _DEVINFO_PART_DEVICE_FAMILY_TG 0x00000049UL /**< Mode TG for DEVINFO_PART */
#define _DEVINFO_PART_DEVICE_FAMILY_EFM32TG 0x00000049UL /**< Mode EFM32TG for DEVINFO_PART */
+#define _DEVINFO_PART_DEVICE_FAMILY_TG 0x00000049UL /**< Mode TG for DEVINFO_PART */
#define _DEVINFO_PART_DEVICE_FAMILY_EFM32LG 0x0000004AUL /**< Mode EFM32LG for DEVINFO_PART */
#define _DEVINFO_PART_DEVICE_FAMILY_LG 0x0000004AUL /**< Mode LG for DEVINFO_PART */
-#define _DEVINFO_PART_DEVICE_FAMILY_EFM32WG 0x0000004BUL /**< Mode EFM32WG for DEVINFO_PART */
#define _DEVINFO_PART_DEVICE_FAMILY_WG 0x0000004BUL /**< Mode WG for DEVINFO_PART */
+#define _DEVINFO_PART_DEVICE_FAMILY_EFM32WG 0x0000004BUL /**< Mode EFM32WG for DEVINFO_PART */
#define _DEVINFO_PART_DEVICE_FAMILY_ZG 0x0000004CUL /**< Mode ZG for DEVINFO_PART */
#define _DEVINFO_PART_DEVICE_FAMILY_EFM32ZG 0x0000004CUL /**< Mode EFM32ZG for DEVINFO_PART */
-#define _DEVINFO_PART_DEVICE_FAMILY_HG 0x0000004DUL /**< Mode HG for DEVINFO_PART */
#define _DEVINFO_PART_DEVICE_FAMILY_EFM32HG 0x0000004DUL /**< Mode EFM32HG for DEVINFO_PART */
+#define _DEVINFO_PART_DEVICE_FAMILY_HG 0x0000004DUL /**< Mode HG for DEVINFO_PART */
#define _DEVINFO_PART_DEVICE_FAMILY_EFM32PG1B 0x00000051UL /**< Mode EFM32PG1B for DEVINFO_PART */
#define _DEVINFO_PART_DEVICE_FAMILY_EFM32JG1B 0x00000053UL /**< Mode EFM32JG1B for DEVINFO_PART */
#define _DEVINFO_PART_DEVICE_FAMILY_EFM32PG12B 0x00000055UL /**< Mode EFM32PG12B for DEVINFO_PART */
@@ -276,6 +277,8 @@ typedef struct {
#define DEVINFO_PART_DEVICE_FAMILY_EFR32BG13B (_DEVINFO_PART_DEVICE_FAMILY_EFR32BG13B << 16) /**< Shifted mode EFR32BG13B for DEVINFO_PART */
#define DEVINFO_PART_DEVICE_FAMILY_EFR32BG13V (_DEVINFO_PART_DEVICE_FAMILY_EFR32BG13V << 16) /**< Shifted mode EFR32BG13V for DEVINFO_PART */
#define DEVINFO_PART_DEVICE_FAMILY_EFR32ZG13P (_DEVINFO_PART_DEVICE_FAMILY_EFR32ZG13P << 16) /**< Shifted mode EFR32ZG13P for DEVINFO_PART */
+#define DEVINFO_PART_DEVICE_FAMILY_EFR32ZG13L (_DEVINFO_PART_DEVICE_FAMILY_EFR32ZG13L << 16) /**< Shifted mode EFR32ZG13L for DEVINFO_PART */
+#define DEVINFO_PART_DEVICE_FAMILY_EFR32ZG13S (_DEVINFO_PART_DEVICE_FAMILY_EFR32ZG13S << 16) /**< Shifted mode EFR32ZG13S for DEVINFO_PART */
#define DEVINFO_PART_DEVICE_FAMILY_EFR32FG13P (_DEVINFO_PART_DEVICE_FAMILY_EFR32FG13P << 16) /**< Shifted mode EFR32FG13P for DEVINFO_PART */
#define DEVINFO_PART_DEVICE_FAMILY_EFR32FG13B (_DEVINFO_PART_DEVICE_FAMILY_EFR32FG13B << 16) /**< Shifted mode EFR32FG13B for DEVINFO_PART */
#define DEVINFO_PART_DEVICE_FAMILY_EFR32FG13V (_DEVINFO_PART_DEVICE_FAMILY_EFR32FG13V << 16) /**< Shifted mode EFR32FG13V for DEVINFO_PART */
@@ -293,16 +296,16 @@ typedef struct {
#define DEVINFO_PART_DEVICE_FAMILY_G (_DEVINFO_PART_DEVICE_FAMILY_G << 16) /**< Shifted mode G for DEVINFO_PART */
#define DEVINFO_PART_DEVICE_FAMILY_EFM32GG (_DEVINFO_PART_DEVICE_FAMILY_EFM32GG << 16) /**< Shifted mode EFM32GG for DEVINFO_PART */
#define DEVINFO_PART_DEVICE_FAMILY_GG (_DEVINFO_PART_DEVICE_FAMILY_GG << 16) /**< Shifted mode GG for DEVINFO_PART */
-#define DEVINFO_PART_DEVICE_FAMILY_TG (_DEVINFO_PART_DEVICE_FAMILY_TG << 16) /**< Shifted mode TG for DEVINFO_PART */
#define DEVINFO_PART_DEVICE_FAMILY_EFM32TG (_DEVINFO_PART_DEVICE_FAMILY_EFM32TG << 16) /**< Shifted mode EFM32TG for DEVINFO_PART */
+#define DEVINFO_PART_DEVICE_FAMILY_TG (_DEVINFO_PART_DEVICE_FAMILY_TG << 16) /**< Shifted mode TG for DEVINFO_PART */
#define DEVINFO_PART_DEVICE_FAMILY_EFM32LG (_DEVINFO_PART_DEVICE_FAMILY_EFM32LG << 16) /**< Shifted mode EFM32LG for DEVINFO_PART */
#define DEVINFO_PART_DEVICE_FAMILY_LG (_DEVINFO_PART_DEVICE_FAMILY_LG << 16) /**< Shifted mode LG for DEVINFO_PART */
-#define DEVINFO_PART_DEVICE_FAMILY_EFM32WG (_DEVINFO_PART_DEVICE_FAMILY_EFM32WG << 16) /**< Shifted mode EFM32WG for DEVINFO_PART */
#define DEVINFO_PART_DEVICE_FAMILY_WG (_DEVINFO_PART_DEVICE_FAMILY_WG << 16) /**< Shifted mode WG for DEVINFO_PART */
+#define DEVINFO_PART_DEVICE_FAMILY_EFM32WG (_DEVINFO_PART_DEVICE_FAMILY_EFM32WG << 16) /**< Shifted mode EFM32WG for DEVINFO_PART */
#define DEVINFO_PART_DEVICE_FAMILY_ZG (_DEVINFO_PART_DEVICE_FAMILY_ZG << 16) /**< Shifted mode ZG for DEVINFO_PART */
#define DEVINFO_PART_DEVICE_FAMILY_EFM32ZG (_DEVINFO_PART_DEVICE_FAMILY_EFM32ZG << 16) /**< Shifted mode EFM32ZG for DEVINFO_PART */
-#define DEVINFO_PART_DEVICE_FAMILY_HG (_DEVINFO_PART_DEVICE_FAMILY_HG << 16) /**< Shifted mode HG for DEVINFO_PART */
#define DEVINFO_PART_DEVICE_FAMILY_EFM32HG (_DEVINFO_PART_DEVICE_FAMILY_EFM32HG << 16) /**< Shifted mode EFM32HG for DEVINFO_PART */
+#define DEVINFO_PART_DEVICE_FAMILY_HG (_DEVINFO_PART_DEVICE_FAMILY_HG << 16) /**< Shifted mode HG for DEVINFO_PART */
#define DEVINFO_PART_DEVICE_FAMILY_EFM32PG1B (_DEVINFO_PART_DEVICE_FAMILY_EFM32PG1B << 16) /**< Shifted mode EFM32PG1B for DEVINFO_PART */
#define DEVINFO_PART_DEVICE_FAMILY_EFM32JG1B (_DEVINFO_PART_DEVICE_FAMILY_EFM32JG1B << 16) /**< Shifted mode EFM32JG1B for DEVINFO_PART */
#define DEVINFO_PART_DEVICE_FAMILY_EFM32PG12B (_DEVINFO_PART_DEVICE_FAMILY_EFM32PG12B << 16) /**< Shifted mode EFM32PG12B for DEVINFO_PART */
diff --git a/cpu/efm32/families/efm32pg1b/include/vendor/efm32pg1b_dma_descriptor.h b/cpu/efm32/families/efm32pg1b/include/vendor/efm32pg1b_dma_descriptor.h
index 921a7d77fd..19825791f0 100644
--- a/cpu/efm32/families/efm32pg1b/include/vendor/efm32pg1b_dma_descriptor.h
+++ b/cpu/efm32/families/efm32pg1b/include/vendor/efm32pg1b_dma_descriptor.h
@@ -1,10 +1,9 @@
/***************************************************************************//**
* @file
* @brief EFM32PG1B_DMA_DESCRIPTOR register and bit field definitions
- * @version 5.8.3
*******************************************************************************
* # License
- * Copyright 2019 Silicon Laboratories Inc. www.silabs.com
+ * Copyright 2020 Silicon Laboratories Inc. www.silabs.com
*******************************************************************************
*
* SPDX-License-Identifier: Zlib
diff --git a/cpu/efm32/families/efm32pg1b/include/vendor/efm32pg1b_dmareq.h b/cpu/efm32/families/efm32pg1b/include/vendor/efm32pg1b_dmareq.h
index d97ed8e342..6a1530a6f5 100644
--- a/cpu/efm32/families/efm32pg1b/include/vendor/efm32pg1b_dmareq.h
+++ b/cpu/efm32/families/efm32pg1b/include/vendor/efm32pg1b_dmareq.h
@@ -1,10 +1,9 @@
/***************************************************************************//**
* @file
* @brief EFM32PG1B_DMAREQ register and bit field definitions
- * @version 5.8.3
*******************************************************************************
* # License
- * Copyright 2019 Silicon Laboratories Inc. www.silabs.com
+ * Copyright 2020 Silicon Laboratories Inc. www.silabs.com
*******************************************************************************
*
* SPDX-License-Identifier: Zlib
diff --git a/cpu/efm32/families/efm32pg1b/include/vendor/efm32pg1b_emu.h b/cpu/efm32/families/efm32pg1b/include/vendor/efm32pg1b_emu.h
index 504dacccaa..9ff4e32f64 100644
--- a/cpu/efm32/families/efm32pg1b/include/vendor/efm32pg1b_emu.h
+++ b/cpu/efm32/families/efm32pg1b/include/vendor/efm32pg1b_emu.h
@@ -1,10 +1,9 @@
/***************************************************************************//**
* @file
* @brief EFM32PG1B_EMU register and bit field definitions
- * @version 5.8.3
*******************************************************************************
* # License
- * Copyright 2019 Silicon Laboratories Inc. www.silabs.com
+ * Copyright 2020 Silicon Laboratories Inc. www.silabs.com
*******************************************************************************
*
* SPDX-License-Identifier: Zlib
@@ -167,13 +166,13 @@ typedef struct {
#define _EMU_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for EMU_LOCKKEY */
#define _EMU_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for EMU_LOCKKEY */
#define _EMU_LOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_LOCK */
-#define _EMU_LOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for EMU_LOCK */
#define _EMU_LOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for EMU_LOCK */
+#define _EMU_LOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for EMU_LOCK */
#define _EMU_LOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for EMU_LOCK */
#define _EMU_LOCK_LOCKKEY_UNLOCK 0x0000ADE8UL /**< Mode UNLOCK for EMU_LOCK */
#define EMU_LOCK_LOCKKEY_DEFAULT (_EMU_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_LOCK */
-#define EMU_LOCK_LOCKKEY_LOCK (_EMU_LOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for EMU_LOCK */
#define EMU_LOCK_LOCKKEY_UNLOCKED (_EMU_LOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for EMU_LOCK */
+#define EMU_LOCK_LOCKKEY_LOCK (_EMU_LOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for EMU_LOCK */
#define EMU_LOCK_LOCKKEY_LOCKED (_EMU_LOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for EMU_LOCK */
#define EMU_LOCK_LOCKKEY_UNLOCK (_EMU_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for EMU_LOCK */
@@ -673,13 +672,13 @@ typedef struct {
#define _EMU_PWRLOCK_LOCKKEY_SHIFT 0 /**< Shift value for EMU_LOCKKEY */
#define _EMU_PWRLOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for EMU_LOCKKEY */
#define _EMU_PWRLOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_PWRLOCK */
-#define _EMU_PWRLOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for EMU_PWRLOCK */
#define _EMU_PWRLOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for EMU_PWRLOCK */
+#define _EMU_PWRLOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for EMU_PWRLOCK */
#define _EMU_PWRLOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for EMU_PWRLOCK */
#define _EMU_PWRLOCK_LOCKKEY_UNLOCK 0x0000ADE8UL /**< Mode UNLOCK for EMU_PWRLOCK */
#define EMU_PWRLOCK_LOCKKEY_DEFAULT (_EMU_PWRLOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_PWRLOCK */
-#define EMU_PWRLOCK_LOCKKEY_LOCK (_EMU_PWRLOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for EMU_PWRLOCK */
#define EMU_PWRLOCK_LOCKKEY_UNLOCKED (_EMU_PWRLOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for EMU_PWRLOCK */
+#define EMU_PWRLOCK_LOCKKEY_LOCK (_EMU_PWRLOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for EMU_PWRLOCK */
#define EMU_PWRLOCK_LOCKKEY_LOCKED (_EMU_PWRLOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for EMU_PWRLOCK */
#define EMU_PWRLOCK_LOCKKEY_UNLOCK (_EMU_PWRLOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for EMU_PWRLOCK */
@@ -1094,13 +1093,13 @@ typedef struct {
#define _EMU_TESTLOCK_LOCKKEY_SHIFT 0 /**< Shift value for EMU_LOCKKEY */
#define _EMU_TESTLOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for EMU_LOCKKEY */
#define _EMU_TESTLOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_TESTLOCK */
-#define _EMU_TESTLOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for EMU_TESTLOCK */
#define _EMU_TESTLOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for EMU_TESTLOCK */
+#define _EMU_TESTLOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for EMU_TESTLOCK */
#define _EMU_TESTLOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for EMU_TESTLOCK */
#define _EMU_TESTLOCK_LOCKKEY_UNLOCK 0x0000ADE8UL /**< Mode UNLOCK for EMU_TESTLOCK */
#define EMU_TESTLOCK_LOCKKEY_DEFAULT (_EMU_TESTLOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_TESTLOCK */
-#define EMU_TESTLOCK_LOCKKEY_LOCK (_EMU_TESTLOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for EMU_TESTLOCK */
#define EMU_TESTLOCK_LOCKKEY_UNLOCKED (_EMU_TESTLOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for EMU_TESTLOCK */
+#define EMU_TESTLOCK_LOCKKEY_LOCK (_EMU_TESTLOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for EMU_TESTLOCK */
#define EMU_TESTLOCK_LOCKKEY_LOCKED (_EMU_TESTLOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for EMU_TESTLOCK */
#define EMU_TESTLOCK_LOCKKEY_UNLOCK (_EMU_TESTLOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for EMU_TESTLOCK */
diff --git a/cpu/efm32/families/efm32pg1b/include/vendor/efm32pg1b_fpueh.h b/cpu/efm32/families/efm32pg1b/include/vendor/efm32pg1b_fpueh.h
index fda35d44c6..f675ccd783 100644
--- a/cpu/efm32/families/efm32pg1b/include/vendor/efm32pg1b_fpueh.h
+++ b/cpu/efm32/families/efm32pg1b/include/vendor/efm32pg1b_fpueh.h
@@ -1,10 +1,9 @@
/***************************************************************************//**
* @file
* @brief EFM32PG1B_FPUEH register and bit field definitions
- * @version 5.8.3
*******************************************************************************
* # License
- * Copyright 2019 Silicon Laboratories Inc. www.silabs.com
+ * Copyright 2020 Silicon Laboratories Inc. www.silabs.com
*******************************************************************************
*
* SPDX-License-Identifier: Zlib
diff --git a/cpu/efm32/families/efm32pg1b/include/vendor/efm32pg1b_gpcrc.h b/cpu/efm32/families/efm32pg1b/include/vendor/efm32pg1b_gpcrc.h
index 4dbddc1fd6..fe0ca40645 100644
--- a/cpu/efm32/families/efm32pg1b/include/vendor/efm32pg1b_gpcrc.h
+++ b/cpu/efm32/families/efm32pg1b/include/vendor/efm32pg1b_gpcrc.h
@@ -1,10 +1,9 @@
/***************************************************************************//**
* @file
* @brief EFM32PG1B_GPCRC register and bit field definitions
- * @version 5.8.3
*******************************************************************************
* # License
- * Copyright 2019 Silicon Laboratories Inc. www.silabs.com
+ * Copyright 2020 Silicon Laboratories Inc. www.silabs.com
*******************************************************************************
*
* SPDX-License-Identifier: Zlib
diff --git a/cpu/efm32/families/efm32pg1b/include/vendor/efm32pg1b_gpio.h b/cpu/efm32/families/efm32pg1b/include/vendor/efm32pg1b_gpio.h
index 4733558f6d..861e3345c0 100644
--- a/cpu/efm32/families/efm32pg1b/include/vendor/efm32pg1b_gpio.h
+++ b/cpu/efm32/families/efm32pg1b/include/vendor/efm32pg1b_gpio.h
@@ -1,10 +1,9 @@
/***************************************************************************//**
* @file
* @brief EFM32PG1B_GPIO register and bit field definitions
- * @version 5.8.3
*******************************************************************************
* # License
- * Copyright 2019 Silicon Laboratories Inc. www.silabs.com
+ * Copyright 2020 Silicon Laboratories Inc. www.silabs.com
*******************************************************************************
*
* SPDX-License-Identifier: Zlib
@@ -1350,13 +1349,13 @@ typedef struct {
#define _GPIO_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for GPIO_LOCKKEY */
#define _GPIO_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for GPIO_LOCKKEY */
#define _GPIO_LOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_LOCK */
-#define _GPIO_LOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for GPIO_LOCK */
#define _GPIO_LOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for GPIO_LOCK */
+#define _GPIO_LOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for GPIO_LOCK */
#define _GPIO_LOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for GPIO_LOCK */
#define _GPIO_LOCK_LOCKKEY_UNLOCK 0x0000A534UL /**< Mode UNLOCK for GPIO_LOCK */
#define GPIO_LOCK_LOCKKEY_DEFAULT (_GPIO_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_LOCK */
-#define GPIO_LOCK_LOCKKEY_LOCK (_GPIO_LOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for GPIO_LOCK */
#define GPIO_LOCK_LOCKKEY_UNLOCKED (_GPIO_LOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for GPIO_LOCK */
+#define GPIO_LOCK_LOCKKEY_LOCK (_GPIO_LOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for GPIO_LOCK */
#define GPIO_LOCK_LOCKKEY_LOCKED (_GPIO_LOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for GPIO_LOCK */
#define GPIO_LOCK_LOCKKEY_UNLOCK (_GPIO_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for GPIO_LOCK */
diff --git a/cpu/efm32/families/efm32pg1b/include/vendor/efm32pg1b_gpio_p.h b/cpu/efm32/families/efm32pg1b/include/vendor/efm32pg1b_gpio_p.h
index 3a0fca1c0c..72cf724d48 100644
--- a/cpu/efm32/families/efm32pg1b/include/vendor/efm32pg1b_gpio_p.h
+++ b/cpu/efm32/families/efm32pg1b/include/vendor/efm32pg1b_gpio_p.h
@@ -1,10 +1,9 @@
/***************************************************************************//**
* @file
* @brief EFM32PG1B_GPIO_P register and bit field definitions
- * @version 5.8.3
*******************************************************************************
* # License
- * Copyright 2019 Silicon Laboratories Inc. www.silabs.com
+ * Copyright 2020 Silicon Laboratories Inc. www.silabs.com
*******************************************************************************
*
* SPDX-License-Identifier: Zlib
diff --git a/cpu/efm32/families/efm32pg1b/include/vendor/efm32pg1b_i2c.h b/cpu/efm32/families/efm32pg1b/include/vendor/efm32pg1b_i2c.h
index 7628b68d4e..3c61011ac6 100644
--- a/cpu/efm32/families/efm32pg1b/include/vendor/efm32pg1b_i2c.h
+++ b/cpu/efm32/families/efm32pg1b/include/vendor/efm32pg1b_i2c.h
@@ -1,10 +1,9 @@
/***************************************************************************//**
* @file
* @brief EFM32PG1B_I2C register and bit field definitions
- * @version 5.8.3
*******************************************************************************
* # License
- * Copyright 2019 Silicon Laboratories Inc. www.silabs.com
+ * Copyright 2020 Silicon Laboratories Inc. www.silabs.com
*******************************************************************************
*
* SPDX-License-Identifier: Zlib
diff --git a/cpu/efm32/families/efm32pg1b/include/vendor/efm32pg1b_idac.h b/cpu/efm32/families/efm32pg1b/include/vendor/efm32pg1b_idac.h
index 4768fe48d8..6519359386 100644
--- a/cpu/efm32/families/efm32pg1b/include/vendor/efm32pg1b_idac.h
+++ b/cpu/efm32/families/efm32pg1b/include/vendor/efm32pg1b_idac.h
@@ -1,10 +1,9 @@
/***************************************************************************//**
* @file
* @brief EFM32PG1B_IDAC register and bit field definitions
- * @version 5.8.3
*******************************************************************************
* # License
- * Copyright 2019 Silicon Laboratories Inc. www.silabs.com
+ * Copyright 2020 Silicon Laboratories Inc. www.silabs.com
*******************************************************************************
*
* SPDX-License-Identifier: Zlib
diff --git a/cpu/efm32/families/efm32pg1b/include/vendor/efm32pg1b_ldma.h b/cpu/efm32/families/efm32pg1b/include/vendor/efm32pg1b_ldma.h
index 8beabde46c..606633ceda 100644
--- a/cpu/efm32/families/efm32pg1b/include/vendor/efm32pg1b_ldma.h
+++ b/cpu/efm32/families/efm32pg1b/include/vendor/efm32pg1b_ldma.h
@@ -1,10 +1,9 @@
/***************************************************************************//**
* @file
* @brief EFM32PG1B_LDMA register and bit field definitions
- * @version 5.8.3
*******************************************************************************
* # License
- * Copyright 2019 Silicon Laboratories Inc. www.silabs.com
+ * Copyright 2020 Silicon Laboratories Inc. www.silabs.com
*******************************************************************************
*
* SPDX-License-Identifier: Zlib
diff --git a/cpu/efm32/families/efm32pg1b/include/vendor/efm32pg1b_ldma_ch.h b/cpu/efm32/families/efm32pg1b/include/vendor/efm32pg1b_ldma_ch.h
index 7b78b090f4..7658d204a9 100644
--- a/cpu/efm32/families/efm32pg1b/include/vendor/efm32pg1b_ldma_ch.h
+++ b/cpu/efm32/families/efm32pg1b/include/vendor/efm32pg1b_ldma_ch.h
@@ -1,10 +1,9 @@
/***************************************************************************//**
* @file
* @brief EFM32PG1B_LDMA_CH register and bit field definitions
- * @version 5.8.3
*******************************************************************************
* # License
- * Copyright 2019 Silicon Laboratories Inc. www.silabs.com
+ * Copyright 2020 Silicon Laboratories Inc. www.silabs.com
*******************************************************************************
*
* SPDX-License-Identifier: Zlib
diff --git a/cpu/efm32/families/efm32pg1b/include/vendor/efm32pg1b_letimer.h b/cpu/efm32/families/efm32pg1b/include/vendor/efm32pg1b_letimer.h
index 69d126584a..27e0dde73a 100644
--- a/cpu/efm32/families/efm32pg1b/include/vendor/efm32pg1b_letimer.h
+++ b/cpu/efm32/families/efm32pg1b/include/vendor/efm32pg1b_letimer.h
@@ -1,10 +1,9 @@
/***************************************************************************//**
* @file
* @brief EFM32PG1B_LETIMER register and bit field definitions
- * @version 5.8.3
*******************************************************************************
* # License
- * Copyright 2019 Silicon Laboratories Inc. www.silabs.com
+ * Copyright 2020 Silicon Laboratories Inc. www.silabs.com
*******************************************************************************
*
* SPDX-License-Identifier: Zlib
diff --git a/cpu/efm32/families/efm32pg1b/include/vendor/efm32pg1b_leuart.h b/cpu/efm32/families/efm32pg1b/include/vendor/efm32pg1b_leuart.h
index 422cfa73c0..f60297190d 100644
--- a/cpu/efm32/families/efm32pg1b/include/vendor/efm32pg1b_leuart.h
+++ b/cpu/efm32/families/efm32pg1b/include/vendor/efm32pg1b_leuart.h
@@ -1,10 +1,9 @@
/***************************************************************************//**
* @file
* @brief EFM32PG1B_LEUART register and bit field definitions
- * @version 5.8.3
*******************************************************************************
* # License
- * Copyright 2019 Silicon Laboratories Inc. www.silabs.com
+ * Copyright 2020 Silicon Laboratories Inc. www.silabs.com
*******************************************************************************
*
* SPDX-License-Identifier: Zlib
diff --git a/cpu/efm32/families/efm32pg1b/include/vendor/efm32pg1b_msc.h b/cpu/efm32/families/efm32pg1b/include/vendor/efm32pg1b_msc.h
index 3eca4993f1..c19bfa9acf 100644
--- a/cpu/efm32/families/efm32pg1b/include/vendor/efm32pg1b_msc.h
+++ b/cpu/efm32/families/efm32pg1b/include/vendor/efm32pg1b_msc.h
@@ -1,10 +1,9 @@
/***************************************************************************//**
* @file
* @brief EFM32PG1B_MSC register and bit field definitions
- * @version 5.8.3
*******************************************************************************
* # License
- * Copyright 2019 Silicon Laboratories Inc. www.silabs.com
+ * Copyright 2020 Silicon Laboratories Inc. www.silabs.com
*******************************************************************************
*
* SPDX-License-Identifier: Zlib
@@ -408,13 +407,13 @@ typedef struct {
#define _MSC_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for MSC_LOCKKEY */
#define _MSC_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for MSC_LOCKKEY */
#define _MSC_LOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_LOCK */
-#define _MSC_LOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for MSC_LOCK */
#define _MSC_LOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for MSC_LOCK */
+#define _MSC_LOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for MSC_LOCK */
#define _MSC_LOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for MSC_LOCK */
#define _MSC_LOCK_LOCKKEY_UNLOCK 0x00001B71UL /**< Mode UNLOCK for MSC_LOCK */
#define MSC_LOCK_LOCKKEY_DEFAULT (_MSC_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_LOCK */
-#define MSC_LOCK_LOCKKEY_LOCK (_MSC_LOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for MSC_LOCK */
#define MSC_LOCK_LOCKKEY_UNLOCKED (_MSC_LOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for MSC_LOCK */
+#define MSC_LOCK_LOCKKEY_LOCK (_MSC_LOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for MSC_LOCK */
#define MSC_LOCK_LOCKKEY_LOCKED (_MSC_LOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for MSC_LOCK */
#define MSC_LOCK_LOCKKEY_UNLOCK (_MSC_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for MSC_LOCK */
@@ -458,13 +457,13 @@ typedef struct {
#define _MSC_MASSLOCK_MASK 0x0000FFFFUL /**< Mask for MSC_MASSLOCK */
#define _MSC_MASSLOCK_LOCKKEY_SHIFT 0 /**< Shift value for MSC_LOCKKEY */
#define _MSC_MASSLOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for MSC_LOCKKEY */
-#define _MSC_MASSLOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for MSC_MASSLOCK */
#define _MSC_MASSLOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for MSC_MASSLOCK */
+#define _MSC_MASSLOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for MSC_MASSLOCK */
#define _MSC_MASSLOCK_LOCKKEY_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_MASSLOCK */
#define _MSC_MASSLOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for MSC_MASSLOCK */
#define _MSC_MASSLOCK_LOCKKEY_UNLOCK 0x0000631AUL /**< Mode UNLOCK for MSC_MASSLOCK */
-#define MSC_MASSLOCK_LOCKKEY_LOCK (_MSC_MASSLOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for MSC_MASSLOCK */
#define MSC_MASSLOCK_LOCKKEY_UNLOCKED (_MSC_MASSLOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for MSC_MASSLOCK */
+#define MSC_MASSLOCK_LOCKKEY_LOCK (_MSC_MASSLOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for MSC_MASSLOCK */
#define MSC_MASSLOCK_LOCKKEY_DEFAULT (_MSC_MASSLOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_MASSLOCK */
#define MSC_MASSLOCK_LOCKKEY_LOCKED (_MSC_MASSLOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for MSC_MASSLOCK */
#define MSC_MASSLOCK_LOCKKEY_UNLOCK (_MSC_MASSLOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for MSC_MASSLOCK */
diff --git a/cpu/efm32/families/efm32pg1b/include/vendor/efm32pg1b_pcnt.h b/cpu/efm32/families/efm32pg1b/include/vendor/efm32pg1b_pcnt.h
index 4097232288..63bb6e7e04 100644
--- a/cpu/efm32/families/efm32pg1b/include/vendor/efm32pg1b_pcnt.h
+++ b/cpu/efm32/families/efm32pg1b/include/vendor/efm32pg1b_pcnt.h
@@ -1,10 +1,9 @@
/***************************************************************************//**
* @file
* @brief EFM32PG1B_PCNT register and bit field definitions
- * @version 5.8.3
*******************************************************************************
* # License
- * Copyright 2019 Silicon Laboratories Inc. www.silabs.com
+ * Copyright 2020 Silicon Laboratories Inc. www.silabs.com
*******************************************************************************
*
* SPDX-License-Identifier: Zlib
diff --git a/cpu/efm32/families/efm32pg1b/include/vendor/efm32pg1b_prs.h b/cpu/efm32/families/efm32pg1b/include/vendor/efm32pg1b_prs.h
index 271bf6806b..f167c986a2 100644
--- a/cpu/efm32/families/efm32pg1b/include/vendor/efm32pg1b_prs.h
+++ b/cpu/efm32/families/efm32pg1b/include/vendor/efm32pg1b_prs.h
@@ -1,10 +1,9 @@
/***************************************************************************//**
* @file
* @brief EFM32PG1B_PRS register and bit field definitions
- * @version 5.8.3
*******************************************************************************
* # License
- * Copyright 2019 Silicon Laboratories Inc. www.silabs.com
+ * Copyright 2020 Silicon Laboratories Inc. www.silabs.com
*******************************************************************************
*
* SPDX-License-Identifier: Zlib
diff --git a/cpu/efm32/families/efm32pg1b/include/vendor/efm32pg1b_prs_ch.h b/cpu/efm32/families/efm32pg1b/include/vendor/efm32pg1b_prs_ch.h
index 48f1846076..3484e6f4c2 100644
--- a/cpu/efm32/families/efm32pg1b/include/vendor/efm32pg1b_prs_ch.h
+++ b/cpu/efm32/families/efm32pg1b/include/vendor/efm32pg1b_prs_ch.h
@@ -1,10 +1,9 @@
/***************************************************************************//**
* @file
* @brief EFM32PG1B_PRS_CH register and bit field definitions
- * @version 5.8.3
*******************************************************************************
* # License
- * Copyright 2019 Silicon Laboratories Inc. www.silabs.com
+ * Copyright 2020 Silicon Laboratories Inc. www.silabs.com
*******************************************************************************
*
* SPDX-License-Identifier: Zlib
diff --git a/cpu/efm32/families/efm32pg1b/include/vendor/efm32pg1b_prs_signals.h b/cpu/efm32/families/efm32pg1b/include/vendor/efm32pg1b_prs_signals.h
index 1cbc4f3004..7bbf6df26f 100644
--- a/cpu/efm32/families/efm32pg1b/include/vendor/efm32pg1b_prs_signals.h
+++ b/cpu/efm32/families/efm32pg1b/include/vendor/efm32pg1b_prs_signals.h
@@ -1,10 +1,9 @@
/***************************************************************************//**
* @file
* @brief EFM32PG1B_PRS_SIGNALS register and bit field definitions
- * @version 5.8.3
*******************************************************************************
* # License
- * Copyright 2019 Silicon Laboratories Inc. www.silabs.com
+ * Copyright 2020 Silicon Laboratories Inc. www.silabs.com
*******************************************************************************
*
* SPDX-License-Identifier: Zlib
diff --git a/cpu/efm32/families/efm32pg1b/include/vendor/efm32pg1b_rmu.h b/cpu/efm32/families/efm32pg1b/include/vendor/efm32pg1b_rmu.h
index a23d13503c..232453e0cf 100644
--- a/cpu/efm32/families/efm32pg1b/include/vendor/efm32pg1b_rmu.h
+++ b/cpu/efm32/families/efm32pg1b/include/vendor/efm32pg1b_rmu.h
@@ -1,10 +1,9 @@
/***************************************************************************//**
* @file
* @brief EFM32PG1B_RMU register and bit field definitions
- * @version 5.8.3
*******************************************************************************
* # License
- * Copyright 2019 Silicon Laboratories Inc. www.silabs.com
+ * Copyright 2020 Silicon Laboratories Inc. www.silabs.com
*******************************************************************************
*
* SPDX-License-Identifier: Zlib
@@ -189,13 +188,13 @@ typedef struct {
#define _RMU_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for RMU_LOCKKEY */
#define _RMU_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for RMU_LOCKKEY */
#define _RMU_LOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for RMU_LOCK */
-#define _RMU_LOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for RMU_LOCK */
#define _RMU_LOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for RMU_LOCK */
+#define _RMU_LOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for RMU_LOCK */
#define _RMU_LOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for RMU_LOCK */
#define _RMU_LOCK_LOCKKEY_UNLOCK 0x0000E084UL /**< Mode UNLOCK for RMU_LOCK */
#define RMU_LOCK_LOCKKEY_DEFAULT (_RMU_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for RMU_LOCK */
-#define RMU_LOCK_LOCKKEY_LOCK (_RMU_LOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for RMU_LOCK */
#define RMU_LOCK_LOCKKEY_UNLOCKED (_RMU_LOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for RMU_LOCK */
+#define RMU_LOCK_LOCKKEY_LOCK (_RMU_LOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for RMU_LOCK */
#define RMU_LOCK_LOCKKEY_LOCKED (_RMU_LOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for RMU_LOCK */
#define RMU_LOCK_LOCKKEY_UNLOCK (_RMU_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for RMU_LOCK */
diff --git a/cpu/efm32/families/efm32pg1b/include/vendor/efm32pg1b_romtable.h b/cpu/efm32/families/efm32pg1b/include/vendor/efm32pg1b_romtable.h
index 6b115637f6..9ceef4a0f9 100644
--- a/cpu/efm32/families/efm32pg1b/include/vendor/efm32pg1b_romtable.h
+++ b/cpu/efm32/families/efm32pg1b/include/vendor/efm32pg1b_romtable.h
@@ -1,10 +1,9 @@
/***************************************************************************//**
* @file
* @brief EFM32PG1B_ROMTABLE register and bit field definitions
- * @version 5.8.3
*******************************************************************************
* # License
- * Copyright 2019 Silicon Laboratories Inc. www.silabs.com
+ * Copyright 2020 Silicon Laboratories Inc. www.silabs.com
*******************************************************************************
*
* SPDX-License-Identifier: Zlib
diff --git a/cpu/efm32/families/efm32pg1b/include/vendor/efm32pg1b_rtcc.h b/cpu/efm32/families/efm32pg1b/include/vendor/efm32pg1b_rtcc.h
index 5aed970b6c..3c59ea8b62 100644
--- a/cpu/efm32/families/efm32pg1b/include/vendor/efm32pg1b_rtcc.h
+++ b/cpu/efm32/families/efm32pg1b/include/vendor/efm32pg1b_rtcc.h
@@ -1,10 +1,9 @@
/***************************************************************************//**
* @file
* @brief EFM32PG1B_RTCC register and bit field definitions
- * @version 5.8.3
*******************************************************************************
* # License
- * Copyright 2019 Silicon Laboratories Inc. www.silabs.com
+ * Copyright 2020 Silicon Laboratories Inc. www.silabs.com
*******************************************************************************
*
* SPDX-License-Identifier: Zlib
@@ -531,13 +530,13 @@ typedef struct {
#define _RTCC_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for RTCC_LOCKKEY */
#define _RTCC_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for RTCC_LOCKKEY */
#define _RTCC_LOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_LOCK */
-#define _RTCC_LOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for RTCC_LOCK */
#define _RTCC_LOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for RTCC_LOCK */
+#define _RTCC_LOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for RTCC_LOCK */
#define _RTCC_LOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for RTCC_LOCK */
#define _RTCC_LOCK_LOCKKEY_UNLOCK 0x0000AEE8UL /**< Mode UNLOCK for RTCC_LOCK */
#define RTCC_LOCK_LOCKKEY_DEFAULT (_RTCC_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for RTCC_LOCK */
-#define RTCC_LOCK_LOCKKEY_LOCK (_RTCC_LOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for RTCC_LOCK */
#define RTCC_LOCK_LOCKKEY_UNLOCKED (_RTCC_LOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for RTCC_LOCK */
+#define RTCC_LOCK_LOCKKEY_LOCK (_RTCC_LOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for RTCC_LOCK */
#define RTCC_LOCK_LOCKKEY_LOCKED (_RTCC_LOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for RTCC_LOCK */
#define RTCC_LOCK_LOCKKEY_UNLOCK (_RTCC_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for RTCC_LOCK */
diff --git a/cpu/efm32/families/efm32pg1b/include/vendor/efm32pg1b_rtcc_cc.h b/cpu/efm32/families/efm32pg1b/include/vendor/efm32pg1b_rtcc_cc.h
index 095f0c0e55..7e32f786fa 100644
--- a/cpu/efm32/families/efm32pg1b/include/vendor/efm32pg1b_rtcc_cc.h
+++ b/cpu/efm32/families/efm32pg1b/include/vendor/efm32pg1b_rtcc_cc.h
@@ -1,10 +1,9 @@
/***************************************************************************//**
* @file
* @brief EFM32PG1B_RTCC_CC register and bit field definitions
- * @version 5.8.3
*******************************************************************************
* # License
- * Copyright 2019 Silicon Laboratories Inc. www.silabs.com
+ * Copyright 2020 Silicon Laboratories Inc. www.silabs.com
*******************************************************************************
*
* SPDX-License-Identifier: Zlib
diff --git a/cpu/efm32/families/efm32pg1b/include/vendor/efm32pg1b_rtcc_ret.h b/cpu/efm32/families/efm32pg1b/include/vendor/efm32pg1b_rtcc_ret.h
index 54b750150c..dc5308fa62 100644
--- a/cpu/efm32/families/efm32pg1b/include/vendor/efm32pg1b_rtcc_ret.h
+++ b/cpu/efm32/families/efm32pg1b/include/vendor/efm32pg1b_rtcc_ret.h
@@ -1,10 +1,9 @@
/***************************************************************************//**
* @file
* @brief EFM32PG1B_RTCC_RET register and bit field definitions
- * @version 5.8.3
*******************************************************************************
* # License
- * Copyright 2019 Silicon Laboratories Inc. www.silabs.com
+ * Copyright 2020 Silicon Laboratories Inc. www.silabs.com
*******************************************************************************
*
* SPDX-License-Identifier: Zlib
diff --git a/cpu/efm32/families/efm32pg1b/include/vendor/efm32pg1b_timer.h b/cpu/efm32/families/efm32pg1b/include/vendor/efm32pg1b_timer.h
index 3560dc97b9..d0b26b31bf 100644
--- a/cpu/efm32/families/efm32pg1b/include/vendor/efm32pg1b_timer.h
+++ b/cpu/efm32/families/efm32pg1b/include/vendor/efm32pg1b_timer.h
@@ -1,10 +1,9 @@
/***************************************************************************//**
* @file
* @brief EFM32PG1B_TIMER register and bit field definitions
- * @version 5.8.3
*******************************************************************************
* # License
- * Copyright 2019 Silicon Laboratories Inc. www.silabs.com
+ * Copyright 2020 Silicon Laboratories Inc. www.silabs.com
*******************************************************************************
*
* SPDX-License-Identifier: Zlib
@@ -586,13 +585,13 @@ typedef struct {
#define _TIMER_LOCK_TIMERLOCKKEY_SHIFT 0 /**< Shift value for TIMER_TIMERLOCKKEY */
#define _TIMER_LOCK_TIMERLOCKKEY_MASK 0xFFFFUL /**< Bit mask for TIMER_TIMERLOCKKEY */
#define _TIMER_LOCK_TIMERLOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_LOCK */
-#define _TIMER_LOCK_TIMERLOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for TIMER_LOCK */
#define _TIMER_LOCK_TIMERLOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for TIMER_LOCK */
+#define _TIMER_LOCK_TIMERLOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for TIMER_LOCK */
#define _TIMER_LOCK_TIMERLOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for TIMER_LOCK */
#define _TIMER_LOCK_TIMERLOCKKEY_UNLOCK 0x0000CE80UL /**< Mode UNLOCK for TIMER_LOCK */
#define TIMER_LOCK_TIMERLOCKKEY_DEFAULT (_TIMER_LOCK_TIMERLOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_LOCK */
-#define TIMER_LOCK_TIMERLOCKKEY_LOCK (_TIMER_LOCK_TIMERLOCKKEY_LOCK << 0) /**< Shifted mode LOCK for TIMER_LOCK */
#define TIMER_LOCK_TIMERLOCKKEY_UNLOCKED (_TIMER_LOCK_TIMERLOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for TIMER_LOCK */
+#define TIMER_LOCK_TIMERLOCKKEY_LOCK (_TIMER_LOCK_TIMERLOCKKEY_LOCK << 0) /**< Shifted mode LOCK for TIMER_LOCK */
#define TIMER_LOCK_TIMERLOCKKEY_LOCKED (_TIMER_LOCK_TIMERLOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for TIMER_LOCK */
#define TIMER_LOCK_TIMERLOCKKEY_UNLOCK (_TIMER_LOCK_TIMERLOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for TIMER_LOCK */
@@ -1573,13 +1572,13 @@ typedef struct {
#define _TIMER_DTLOCK_LOCKKEY_SHIFT 0 /**< Shift value for TIMER_LOCKKEY */
#define _TIMER_DTLOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for TIMER_LOCKKEY */
#define _TIMER_DTLOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTLOCK */
-#define _TIMER_DTLOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for TIMER_DTLOCK */
#define _TIMER_DTLOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for TIMER_DTLOCK */
+#define _TIMER_DTLOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for TIMER_DTLOCK */
#define _TIMER_DTLOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for TIMER_DTLOCK */
#define _TIMER_DTLOCK_LOCKKEY_UNLOCK 0x0000CE80UL /**< Mode UNLOCK for TIMER_DTLOCK */
#define TIMER_DTLOCK_LOCKKEY_DEFAULT (_TIMER_DTLOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_DTLOCK */
-#define TIMER_DTLOCK_LOCKKEY_LOCK (_TIMER_DTLOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for TIMER_DTLOCK */
#define TIMER_DTLOCK_LOCKKEY_UNLOCKED (_TIMER_DTLOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for TIMER_DTLOCK */
+#define TIMER_DTLOCK_LOCKKEY_LOCK (_TIMER_DTLOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for TIMER_DTLOCK */
#define TIMER_DTLOCK_LOCKKEY_LOCKED (_TIMER_DTLOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for TIMER_DTLOCK */
#define TIMER_DTLOCK_LOCKKEY_UNLOCK (_TIMER_DTLOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for TIMER_DTLOCK */
diff --git a/cpu/efm32/families/efm32pg1b/include/vendor/efm32pg1b_timer_cc.h b/cpu/efm32/families/efm32pg1b/include/vendor/efm32pg1b_timer_cc.h
index 00af3b76f3..107d4923d2 100644
--- a/cpu/efm32/families/efm32pg1b/include/vendor/efm32pg1b_timer_cc.h
+++ b/cpu/efm32/families/efm32pg1b/include/vendor/efm32pg1b_timer_cc.h
@@ -1,10 +1,9 @@
/***************************************************************************//**
* @file
* @brief EFM32PG1B_TIMER_CC register and bit field definitions
- * @version 5.8.3
*******************************************************************************
* # License
- * Copyright 2019 Silicon Laboratories Inc. www.silabs.com
+ * Copyright 2020 Silicon Laboratories Inc. www.silabs.com
*******************************************************************************
*
* SPDX-License-Identifier: Zlib
diff --git a/cpu/efm32/families/efm32pg1b/include/vendor/efm32pg1b_usart.h b/cpu/efm32/families/efm32pg1b/include/vendor/efm32pg1b_usart.h
index 76254db0c1..7f4a0cb8fe 100644
--- a/cpu/efm32/families/efm32pg1b/include/vendor/efm32pg1b_usart.h
+++ b/cpu/efm32/families/efm32pg1b/include/vendor/efm32pg1b_usart.h
@@ -1,10 +1,9 @@
/***************************************************************************//**
* @file
* @brief EFM32PG1B_USART register and bit field definitions
- * @version 5.8.3
*******************************************************************************
* # License
- * Copyright 2019 Silicon Laboratories Inc. www.silabs.com
+ * Copyright 2020 Silicon Laboratories Inc. www.silabs.com
*******************************************************************************
*
* SPDX-License-Identifier: Zlib
diff --git a/cpu/efm32/families/efm32pg1b/include/vendor/efm32pg1b_wdog.h b/cpu/efm32/families/efm32pg1b/include/vendor/efm32pg1b_wdog.h
index 9758cd6efb..b7f46eedd5 100644
--- a/cpu/efm32/families/efm32pg1b/include/vendor/efm32pg1b_wdog.h
+++ b/cpu/efm32/families/efm32pg1b/include/vendor/efm32pg1b_wdog.h
@@ -1,10 +1,9 @@
/***************************************************************************//**
* @file
* @brief EFM32PG1B_WDOG register and bit field definitions
- * @version 5.8.3
*******************************************************************************
* # License
- * Copyright 2019 Silicon Laboratories Inc. www.silabs.com
+ * Copyright 2020 Silicon Laboratories Inc. www.silabs.com
*******************************************************************************
*
* SPDX-License-Identifier: Zlib
diff --git a/cpu/efm32/families/efm32pg1b/include/vendor/efm32pg1b_wdog_pch.h b/cpu/efm32/families/efm32pg1b/include/vendor/efm32pg1b_wdog_pch.h
index 95a57c6b60..118b3c0a49 100644
--- a/cpu/efm32/families/efm32pg1b/include/vendor/efm32pg1b_wdog_pch.h
+++ b/cpu/efm32/families/efm32pg1b/include/vendor/efm32pg1b_wdog_pch.h
@@ -1,10 +1,9 @@
/***************************************************************************//**
* @file
* @brief EFM32PG1B_WDOG_PCH register and bit field definitions
- * @version 5.8.3
*******************************************************************************
* # License
- * Copyright 2019 Silicon Laboratories Inc. www.silabs.com
+ * Copyright 2020 Silicon Laboratories Inc. www.silabs.com
*******************************************************************************
*
* SPDX-License-Identifier: Zlib
diff --git a/cpu/efm32/families/efm32pg1b/include/vendor/em_device.h b/cpu/efm32/families/efm32pg1b/include/vendor/em_device.h
index 6369dd1e4d..758eed3993 100644
--- a/cpu/efm32/families/efm32pg1b/include/vendor/em_device.h
+++ b/cpu/efm32/families/efm32pg1b/include/vendor/em_device.h
@@ -11,10 +11,9 @@
* Add "#include "em_device.h" to your source files
* @endverbatim
*
- * @version 5.8.3
*******************************************************************************
* # License
- * Copyright 2019 Silicon Laboratories Inc. www.silabs.com
+ * Copyright 2020 Silicon Laboratories Inc. www.silabs.com
*******************************************************************************
*
* SPDX-License-Identifier: Zlib
diff --git a/cpu/efm32/families/efm32pg1b/include/vendor/system_efm32pg1b.h b/cpu/efm32/families/efm32pg1b/include/vendor/system_efm32pg1b.h
index 947ee96268..9676571df8 100644
--- a/cpu/efm32/families/efm32pg1b/include/vendor/system_efm32pg1b.h
+++ b/cpu/efm32/families/efm32pg1b/include/vendor/system_efm32pg1b.h
@@ -1,10 +1,9 @@
/***************************************************************************//**
* @file
* @brief CMSIS Cortex-M3/M4 System Layer for EFM32 devices.
- * @version 5.8.3
*******************************************************************************
* # License
- * Copyright 2019 Silicon Laboratories Inc. www.silabs.com
+ * Copyright 2020 Silicon Laboratories Inc. www.silabs.com
*******************************************************************************
*
* SPDX-License-Identifier: Zlib
@@ -47,12 +46,29 @@ extern "C" {
* @{
******************************************************************************/
+/*******************************************************************************
+ ****************************** TYPEDEFS ***********************************
+ ******************************************************************************/
+
+/* Interrupt vectortable entry */
+typedef union {
+ void (*pFunc)(void);
+ void *topOfStack;
+} tVectorEntry;
+
/*******************************************************************************
************************** GLOBAL VARIABLES *******************************
******************************************************************************/
-extern uint32_t SystemCoreClock; /**< System Clock Frequency (Core Clock) */
-extern uint32_t SystemHfrcoFreq; /**< System HFRCO frequency */
+extern uint32_t SystemCoreClock; /**< System Clock Frequency (Core Clock) */
+extern uint32_t SystemHfrcoFreq; /**< System HFRCO frequency */
+
+#if defined(__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+#if defined(__ICCARM__) /* IAR requires the __vector_table symbol */
+#define __Vectors __vector_table
+#endif
+extern const tVectorEntry __Vectors[];
+#endif
/*******************************************************************************
***************************** PROTOTYPES **********************************
diff --git a/cpu/efm32/families/efm32pg1b/system.c b/cpu/efm32/families/efm32pg1b/system.c
index 0be22db05c..e60114ebfc 100644
--- a/cpu/efm32/families/efm32pg1b/system.c
+++ b/cpu/efm32/families/efm32pg1b/system.c
@@ -1,10 +1,9 @@
/***************************************************************************//**
* @file
* @brief CMSIS Cortex-M3/M4 System Layer for EFM32 devices.
- * @version 5.8.3
*******************************************************************************
* # License
- * Copyright 2019 Silicon Laboratories Inc. www.silabs.com
+ * Copyright 2020 Silicon Laboratories Inc. www.silabs.com
*******************************************************************************
*
* SPDX-License-Identifier: Zlib
@@ -117,13 +116,6 @@ uint32_t SystemHfrcoFreq = EFM32_HFRCO_STARTUP_FREQ;
************************** GLOBAL FUNCTIONS *******************************
******************************************************************************/
-#if defined(__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
-#if defined(__ICCARM__) /* IAR requires the __vector_table symbol */
-#define __Vectors __vector_table
-#endif
-extern uint32_t __Vectors;
-#endif
-
/***************************************************************************//**
* @brief
* Get the current core clock frequency.
@@ -215,6 +207,12 @@ uint32_t SystemHFClockGet(void)
#endif
break;
+#if defined(CMU_HFCLKSTATUS_SELECTED_HFRCODIV2)
+ case CMU_HFCLKSTATUS_SELECTED_HFRCODIV2:
+ ret = SystemHfrcoFreq / 2;
+ break;
+#endif
+
default: /* CMU_HFCLKSTATUS_SELECTED_HFRCO */
ret = SystemHfrcoFreq;
break;
@@ -303,6 +301,19 @@ void SystemInit(void)
#if defined(UNALIGNED_SUPPORT_DISABLE)
SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk;
#endif
+
+#if defined(_SILICON_LABS_32B_SERIES_1_CONFIG_1)
+ /****************************
+ * Fix for errata DCDC_E206
+ * Enable bypass switch as errata workaround. The bypass current limit will be
+ * disabled again in CHIP_Init() to avoid added current consumption. */
+
+ EMU->DCDCCLIMCTRL |= 1U << _EMU_DCDCCLIMCTRL_BYPLIMEN_SHIFT;
+ EMU->DCDCCTRL = (EMU->DCDCCTRL & ~_EMU_DCDCCTRL_DCDCMODE_MASK)
+ | EMU_DCDCCTRL_DCDCMODE_BYPASS;
+ *(volatile uint32_t *)(0x400E3074) &= ~(0x1UL << 0);
+ *(volatile uint32_t *)(0x400E3060) &= ~(0x1UL << 28);
+#endif
}
/***************************************************************************//**
diff --git a/cpu/efm32/families/efm32zg/include/vendor/efm32zg222f32.h b/cpu/efm32/families/efm32zg/include/vendor/efm32zg222f32.h
index 003cc4a10d..357eb98e85 100644
--- a/cpu/efm32/families/efm32zg/include/vendor/efm32zg222f32.h
+++ b/cpu/efm32/families/efm32zg/include/vendor/efm32zg222f32.h
@@ -1,35 +1,33 @@
-/**************************************************************************//**
- * @file efm32zg222f32.h
+/***************************************************************************//**
+ * @file
* @brief CMSIS Cortex-M Peripheral Access Layer Header File
* for EFM32ZG222F32
- * @version 5.4.0
- ******************************************************************************
+ *******************************************************************************
* # License
- * Copyright 2017 Silicon Laboratories, Inc. www.silabs.com
- ******************************************************************************
+ * Copyright 2020 Silicon Laboratories Inc. www.silabs.com
+ *******************************************************************************
+ *
+ * SPDX-License-Identifier: Zlib
+ *
+ * The licensor of this software is Silicon Laboratories Inc.
+ *
+ * This software is provided 'as-is', without any express or implied
+ * warranty. In no event will the authors be held liable for any damages
+ * arising from the use of this software.
*
* Permission is granted to anyone to use this software for any purpose,
* including commercial applications, and to alter it and redistribute it
* freely, subject to the following restrictions:
*
* 1. The origin of this software must not be misrepresented; you must not
- * claim that you wrote the original software.@n
+ * claim that you wrote the original software. If you use this software
+ * in a product, an acknowledgment in the product documentation would be
+ * appreciated but is not required.
* 2. Altered source versions must be plainly marked as such, and must not be
- * misrepresented as being the original software.@n
+ * misrepresented as being the original software.
* 3. This notice may not be removed or altered from any source distribution.
*
- * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
- * has no obligation to support this Software. Silicon Laboratories, Inc. is
- * providing the Software "AS IS", with no express or implied warranties of any
- * kind, including, but not limited to, any implied warranties of
- * merchantability or fitness for any particular purpose or warranties against
- * infringement of any proprietary rights of a third party.
- *
- * Silicon Laboratories, Inc. will not be liable for any consequential,
- * incidental, or special damages, or any other relief, or for any claim by
- * any third party, arising from your use of this Software.
- *
- *****************************************************************************/
+ ******************************************************************************/
#if defined(__ICCARM__)
#pragma system_include /* Treat file as system include file. */
@@ -44,15 +42,15 @@
extern "C" {
#endif
-/**************************************************************************//**
+/***************************************************************************//**
* @addtogroup Parts
* @{
- *****************************************************************************/
+ ******************************************************************************/
-/**************************************************************************//**
+/***************************************************************************//**
* @defgroup EFM32ZG222F32 EFM32ZG222F32
* @{
- *****************************************************************************/
+ ******************************************************************************/
/** Interrupt Number Definition */
typedef enum IRQn{
@@ -83,22 +81,22 @@ typedef enum IRQn{
AES_IRQn = 16, /*!< 16 EFM32 AES Interrupt */
} IRQn_Type;
-/**************************************************************************//**
+/***************************************************************************//**
* @defgroup EFM32ZG222F32_Core EFM32ZG222F32 Core
* @{
* @brief Processor and Core Peripheral Section
- *****************************************************************************/
-#define __MPU_PRESENT 0 /**< MPU not present */
-#define __VTOR_PRESENT 1 /**< Presence of VTOR register in SCB */
-#define __NVIC_PRIO_BITS 2 /**< NVIC interrupt priority bits */
-#define __Vendor_SysTickConfig 0 /**< Is 1 if different SysTick counter is used */
+ ******************************************************************************/
+#define __MPU_PRESENT 0U /**< MPU not present */
+#define __VTOR_PRESENT 1U /**< Presence of VTOR register in SCB */
+#define __NVIC_PRIO_BITS 2U /**< NVIC interrupt priority bits */
+#define __Vendor_SysTickConfig 0U /**< Is 1 if different SysTick counter is used */
/** @} End of group EFM32ZG222F32_Core */
-/**************************************************************************//**
+/***************************************************************************//**
* @defgroup EFM32ZG222F32_Part EFM32ZG222F32 Part
* @{
-******************************************************************************/
+*******************************************************************************/
/** Part family */
#define _EFM32_ZERO_FAMILY 1 /**< Zero Gecko EFM32ZG MCU Family */
@@ -119,26 +117,26 @@ typedef enum IRQn{
#define PART_NUMBER "EFM32ZG222F32" /**< Part Number */
/** Memory Base addresses and limits */
-#define FLASH_MEM_BASE ((uint32_t) 0x0UL) /**< FLASH base address */
-#define FLASH_MEM_SIZE ((uint32_t) 0x10000000UL) /**< FLASH available address space */
-#define FLASH_MEM_END ((uint32_t) 0xFFFFFFFUL) /**< FLASH end address */
-#define FLASH_MEM_BITS ((uint32_t) 0x28UL) /**< FLASH used bits */
-#define AES_MEM_BASE ((uint32_t) 0x400E0000UL) /**< AES base address */
-#define AES_MEM_SIZE ((uint32_t) 0x400UL) /**< AES available address space */
-#define AES_MEM_END ((uint32_t) 0x400E03FFUL) /**< AES end address */
-#define AES_MEM_BITS ((uint32_t) 0x10UL) /**< AES used bits */
-#define PER_MEM_BASE ((uint32_t) 0x40000000UL) /**< PER base address */
-#define PER_MEM_SIZE ((uint32_t) 0xE0000UL) /**< PER available address space */
-#define PER_MEM_END ((uint32_t) 0x400DFFFFUL) /**< PER end address */
-#define PER_MEM_BITS ((uint32_t) 0x20UL) /**< PER used bits */
-#define RAM_MEM_BASE ((uint32_t) 0x20000000UL) /**< RAM base address */
-#define RAM_MEM_SIZE ((uint32_t) 0x40000UL) /**< RAM available address space */
-#define RAM_MEM_END ((uint32_t) 0x2003FFFFUL) /**< RAM end address */
-#define RAM_MEM_BITS ((uint32_t) 0x18UL) /**< RAM used bits */
-#define RAM_CODE_MEM_BASE ((uint32_t) 0x10000000UL) /**< RAM_CODE base address */
-#define RAM_CODE_MEM_SIZE ((uint32_t) 0x20000UL) /**< RAM_CODE available address space */
-#define RAM_CODE_MEM_END ((uint32_t) 0x1001FFFFUL) /**< RAM_CODE end address */
-#define RAM_CODE_MEM_BITS ((uint32_t) 0x17UL) /**< RAM_CODE used bits */
+#define RAM_MEM_BASE (0x20000000UL) /**< RAM base address */
+#define RAM_MEM_SIZE (0x40000UL) /**< RAM available address space */
+#define RAM_MEM_END (0x2003FFFFUL) /**< RAM end address */
+#define RAM_MEM_BITS (0x18UL) /**< RAM used bits */
+#define RAM_CODE_MEM_BASE (0x10000000UL) /**< RAM_CODE base address */
+#define RAM_CODE_MEM_SIZE (0x20000UL) /**< RAM_CODE available address space */
+#define RAM_CODE_MEM_END (0x1001FFFFUL) /**< RAM_CODE end address */
+#define RAM_CODE_MEM_BITS (0x17UL) /**< RAM_CODE used bits */
+#define PER_MEM_BASE (0x40000000UL) /**< PER base address */
+#define PER_MEM_SIZE (0xE0000UL) /**< PER available address space */
+#define PER_MEM_END (0x400DFFFFUL) /**< PER end address */
+#define PER_MEM_BITS (0x20UL) /**< PER used bits */
+#define FLASH_MEM_BASE (0x0UL) /**< FLASH base address */
+#define FLASH_MEM_SIZE (0x10000000UL) /**< FLASH available address space */
+#define FLASH_MEM_END (0xFFFFFFFUL) /**< FLASH end address */
+#define FLASH_MEM_BITS (0x28UL) /**< FLASH used bits */
+#define AES_MEM_BASE (0x400E0000UL) /**< AES base address */
+#define AES_MEM_SIZE (0x400UL) /**< AES available address space */
+#define AES_MEM_END (0x400E03FFUL) /**< AES end address */
+#define AES_MEM_BITS (0x10UL) /**< AES used bits */
/** Flash and SRAM limits for EFM32ZG222F32 */
#define FLASH_BASE (0x00000000UL) /**< Flash Base Address */
@@ -146,7 +144,7 @@ typedef enum IRQn{
#define FLASH_PAGE_SIZE 1024U /**< Flash Memory page size */
#define SRAM_BASE (0x20000000UL) /**< SRAM Base Address */
#define SRAM_SIZE (0x00001000UL) /**< Available SRAM Memory */
-#define __CM0PLUS_REV 0x001 /**< Cortex-M0+ Core revision r0p1 */
+#define __CM0PLUS_REV 0x0001U /**< Cortex-M0+ Core revision r0p1 */
#define PRS_CHAN_COUNT 4 /**< Number of PRS channels */
#define DMA_CHAN_COUNT 4 /**< Number of DMA channels */
#define EXT_IRQ_COUNT 19 /**< Number of External (NVIC) interrupts */
@@ -219,11 +217,11 @@ typedef enum IRQn{
#include "core_cm0plus.h" /* Cortex-M0+ processor and core peripherals */
#include "system_efm32zg.h" /* System Header */
-/**************************************************************************//**
+/***************************************************************************//**
* @defgroup EFM32ZG222F32_Peripheral_TypeDefs EFM32ZG222F32 Peripheral TypeDefs
* @{
* @brief Device Specific Peripheral Register Structures
- *****************************************************************************/
+ ******************************************************************************/
#include "efm32zg_aes.h"
#include "efm32zg_dma_ch.h"
@@ -255,10 +253,10 @@ typedef enum IRQn{
/** @} End of group EFM32ZG222F32_Peripheral_TypeDefs */
-/**************************************************************************//**
+/***************************************************************************//**
* @defgroup EFM32ZG222F32_Peripheral_Base EFM32ZG222F32 Peripheral Memory Map
* @{
- *****************************************************************************/
+ ******************************************************************************/
#define AES_BASE (0x400E0000UL) /**< AES base address */
#define DMA_BASE (0x400C2000UL) /**< DMA base address */
@@ -288,10 +286,10 @@ typedef enum IRQn{
/** @} End of group EFM32ZG222F32_Peripheral_Base */
-/**************************************************************************//**
+/***************************************************************************//**
* @defgroup EFM32ZG222F32_Peripheral_Declaration EFM32ZG222F32 Peripheral Declarations
* @{
- *****************************************************************************/
+ ******************************************************************************/
#define AES ((AES_TypeDef *) AES_BASE) /**< AES base pointer */
#define DMA ((DMA_TypeDef *) DMA_BASE) /**< DMA base pointer */
@@ -319,19 +317,19 @@ typedef enum IRQn{
/** @} End of group EFM32ZG222F32_Peripheral_Declaration */
-/**************************************************************************//**
+/***************************************************************************//**
* @defgroup EFM32ZG222F32_BitFields EFM32ZG222F32 Bit Fields
* @{
- *****************************************************************************/
+ ******************************************************************************/
#include "efm32zg_prs_signals.h"
#include "efm32zg_dmareq.h"
#include "efm32zg_dmactrl.h"
-/**************************************************************************//**
+/***************************************************************************//**
* @defgroup EFM32ZG222F32_UNLOCK EFM32ZG222F32 Unlock Codes
* @{
- *****************************************************************************/
+ ******************************************************************************/
#define MSC_UNLOCK_CODE 0x1B71 /**< MSC unlock code */
#define EMU_UNLOCK_CODE 0xADE8 /**< EMU unlock code */
#define CMU_UNLOCK_CODE 0x580E /**< CMU unlock code */
@@ -342,17 +340,17 @@ typedef enum IRQn{
/** @} End of group EFM32ZG222F32_BitFields */
-/**************************************************************************//**
+/***************************************************************************//**
* @defgroup EFM32ZG222F32_Alternate_Function EFM32ZG222F32 Alternate Function
* @{
- *****************************************************************************/
+ ******************************************************************************/
#include "efm32zg_af_ports.h"
#include "efm32zg_af_pins.h"
/** @} End of group EFM32ZG222F32_Alternate_Function */
-/**************************************************************************//**
+/***************************************************************************//**
* @brief Set the value of a bit field within a register.
*
* @param REG
@@ -364,7 +362,7 @@ typedef enum IRQn{
* @param OFFSET
* The number of bits that the field is offset within the register.
* 0 (zero) means LSB.
- *****************************************************************************/
+ ******************************************************************************/
#define SET_BIT_FIELD(REG, MASK, VALUE, OFFSET) \
REG = ((REG) &~(MASK)) | (((VALUE) << (OFFSET)) & (MASK));
diff --git a/cpu/efm32/families/efm32zg/include/vendor/efm32zg_acmp.h b/cpu/efm32/families/efm32zg/include/vendor/efm32zg_acmp.h
index 6d59cfc0c2..9e637cf126 100644
--- a/cpu/efm32/families/efm32zg/include/vendor/efm32zg_acmp.h
+++ b/cpu/efm32/families/efm32zg/include/vendor/efm32zg_acmp.h
@@ -1,34 +1,32 @@
-/**************************************************************************//**
- * @file efm32zg_acmp.h
+/***************************************************************************//**
+ * @file
* @brief EFM32ZG_ACMP register and bit field definitions
- * @version 5.4.0
- ******************************************************************************
+ *******************************************************************************
* # License
- * Copyright 2017 Silicon Laboratories, Inc. www.silabs.com
- ******************************************************************************
+ * Copyright 2020 Silicon Laboratories Inc. www.silabs.com
+ *******************************************************************************
+ *
+ * SPDX-License-Identifier: Zlib
+ *
+ * The licensor of this software is Silicon Laboratories Inc.
+ *
+ * This software is provided 'as-is', without any express or implied
+ * warranty. In no event will the authors be held liable for any damages
+ * arising from the use of this software.
*
* Permission is granted to anyone to use this software for any purpose,
* including commercial applications, and to alter it and redistribute it
* freely, subject to the following restrictions:
*
* 1. The origin of this software must not be misrepresented; you must not
- * claim that you wrote the original software.@n
+ * claim that you wrote the original software. If you use this software
+ * in a product, an acknowledgment in the product documentation would be
+ * appreciated but is not required.
* 2. Altered source versions must be plainly marked as such, and must not be
- * misrepresented as being the original software.@n
+ * misrepresented as being the original software.
* 3. This notice may not be removed or altered from any source distribution.
*
- * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
- * has no obligation to support this Software. Silicon Laboratories, Inc. is
- * providing the Software "AS IS", with no express or implied warranties of any
- * kind, including, but not limited to, any implied warranties of
- * merchantability or fitness for any particular purpose or warranties against
- * infringement of any proprietary rights of a third party.
- *
- * Silicon Laboratories, Inc. will not be liable for any consequential,
- * incidental, or special damages, or any other relief, or for any claim by
- * any third party, arising from your use of this Software.
- *
- *****************************************************************************/
+ ******************************************************************************/
#ifdef __cplusplus
extern "C" {
@@ -41,15 +39,15 @@ extern "C" {
#pragma clang system_header /* Treat file as system include file. */
#endif
-/**************************************************************************//**
-* @addtogroup Parts
-* @{
-******************************************************************************/
-/**************************************************************************//**
+/***************************************************************************//**
+ * @addtogroup Parts
+ * @{
+ ******************************************************************************/
+/***************************************************************************//**
* @defgroup EFM32ZG_ACMP
* @{
* @brief EFM32ZG_ACMP Register Declaration
- *****************************************************************************/
+ ******************************************************************************/
typedef struct {
__IOM uint32_t CTRL; /**< Control Register */
__IOM uint32_t INPUTSEL; /**< Input Selection Register */
@@ -61,10 +59,10 @@ typedef struct {
__IOM uint32_t ROUTE; /**< I/O Routing Register */
} ACMP_TypeDef; /** ACMP Register Declaration *//** @} */
-/**************************************************************************//**
+/***************************************************************************//**
* @defgroup EFM32ZG_ACMP_BitFields
* @{
- *****************************************************************************/
+ ******************************************************************************/
/* Bit fields for ACMP CTRL */
#define _ACMP_CTRL_RESETVALUE 0x47000000UL /**< Default value for ACMP_CTRL */
diff --git a/cpu/efm32/families/efm32zg/include/vendor/efm32zg_adc.h b/cpu/efm32/families/efm32zg/include/vendor/efm32zg_adc.h
index dfca845f95..c7c0ed41a7 100644
--- a/cpu/efm32/families/efm32zg/include/vendor/efm32zg_adc.h
+++ b/cpu/efm32/families/efm32zg/include/vendor/efm32zg_adc.h
@@ -1,34 +1,32 @@
-/**************************************************************************//**
- * @file efm32zg_adc.h
+/***************************************************************************//**
+ * @file
* @brief EFM32ZG_ADC register and bit field definitions
- * @version 5.4.0
- ******************************************************************************
+ *******************************************************************************
* # License
- * Copyright 2017 Silicon Laboratories, Inc. www.silabs.com
- ******************************************************************************
+ * Copyright 2020 Silicon Laboratories Inc. www.silabs.com
+ *******************************************************************************
+ *
+ * SPDX-License-Identifier: Zlib
+ *
+ * The licensor of this software is Silicon Laboratories Inc.
+ *
+ * This software is provided 'as-is', without any express or implied
+ * warranty. In no event will the authors be held liable for any damages
+ * arising from the use of this software.
*
* Permission is granted to anyone to use this software for any purpose,
* including commercial applications, and to alter it and redistribute it
* freely, subject to the following restrictions:
*
* 1. The origin of this software must not be misrepresented; you must not
- * claim that you wrote the original software.@n
+ * claim that you wrote the original software. If you use this software
+ * in a product, an acknowledgment in the product documentation would be
+ * appreciated but is not required.
* 2. Altered source versions must be plainly marked as such, and must not be
- * misrepresented as being the original software.@n
+ * misrepresented as being the original software.
* 3. This notice may not be removed or altered from any source distribution.
*
- * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
- * has no obligation to support this Software. Silicon Laboratories, Inc. is
- * providing the Software "AS IS", with no express or implied warranties of any
- * kind, including, but not limited to, any implied warranties of
- * merchantability or fitness for any particular purpose or warranties against
- * infringement of any proprietary rights of a third party.
- *
- * Silicon Laboratories, Inc. will not be liable for any consequential,
- * incidental, or special damages, or any other relief, or for any claim by
- * any third party, arising from your use of this Software.
- *
- *****************************************************************************/
+ ******************************************************************************/
#ifdef __cplusplus
extern "C" {
@@ -41,39 +39,39 @@ extern "C" {
#pragma clang system_header /* Treat file as system include file. */
#endif
-/**************************************************************************//**
-* @addtogroup Parts
-* @{
-******************************************************************************/
-/**************************************************************************//**
+/***************************************************************************//**
+ * @addtogroup Parts
+ * @{
+ ******************************************************************************/
+/***************************************************************************//**
* @defgroup EFM32ZG_ADC
* @{
* @brief EFM32ZG_ADC Register Declaration
- *****************************************************************************/
+ ******************************************************************************/
typedef struct {
- __IOM uint32_t CTRL; /**< Control Register */
- __IOM uint32_t CMD; /**< Command Register */
- __IM uint32_t STATUS; /**< Status Register */
- __IOM uint32_t SINGLECTRL; /**< Single Sample Control Register */
- __IOM uint32_t SCANCTRL; /**< Scan Control Register */
- __IOM uint32_t IEN; /**< Interrupt Enable Register */
- __IM uint32_t IF; /**< Interrupt Flag Register */
- __IOM uint32_t IFS; /**< Interrupt Flag Set Register */
- __IOM uint32_t IFC; /**< Interrupt Flag Clear Register */
- __IM uint32_t SINGLEDATA; /**< Single Conversion Result Data */
- __IM uint32_t SCANDATA; /**< Scan Conversion Result Data */
- __IM uint32_t SINGLEDATAP; /**< Single Conversion Result Data Peek Register */
- __IM uint32_t SCANDATAP; /**< Scan Sequence Result Data Peek Register */
- __IOM uint32_t CAL; /**< Calibration Register */
+ __IOM uint32_t CTRL; /**< Control Register */
+ __IOM uint32_t CMD; /**< Command Register */
+ __IM uint32_t STATUS; /**< Status Register */
+ __IOM uint32_t SINGLECTRL; /**< Single Sample Control Register */
+ __IOM uint32_t SCANCTRL; /**< Scan Control Register */
+ __IOM uint32_t IEN; /**< Interrupt Enable Register */
+ __IM uint32_t IF; /**< Interrupt Flag Register */
+ __IOM uint32_t IFS; /**< Interrupt Flag Set Register */
+ __IOM uint32_t IFC; /**< Interrupt Flag Clear Register */
+ __IM uint32_t SINGLEDATA; /**< Single Conversion Result Data */
+ __IM uint32_t SCANDATA; /**< Scan Conversion Result Data */
+ __IM uint32_t SINGLEDATAP; /**< Single Conversion Result Data Peek Register */
+ __IM uint32_t SCANDATAP; /**< Scan Sequence Result Data Peek Register */
+ __IOM uint32_t CAL; /**< Calibration Register */
- uint32_t RESERVED0[1]; /**< Reserved for future use **/
- __IOM uint32_t BIASPROG; /**< Bias Programming Register */
-} ADC_TypeDef; /** ADC Register Declaration *//** @} */
+ uint32_t RESERVED0[1U]; /**< Reserved for future use **/
+ __IOM uint32_t BIASPROG; /**< Bias Programming Register */
+} ADC_TypeDef; /** ADC Register Declaration *//** @} */
-/**************************************************************************//**
+/***************************************************************************//**
* @defgroup EFM32ZG_ADC_BitFields
* @{
- *****************************************************************************/
+ ******************************************************************************/
/* Bit fields for ADC CTRL */
#define _ADC_CTRL_RESETVALUE 0x001F0000UL /**< Default value for ADC_CTRL */
@@ -273,16 +271,16 @@ typedef struct {
#define _ADC_SINGLECTRL_INPUTSEL_SHIFT 8 /**< Shift value for ADC_INPUTSEL */
#define _ADC_SINGLECTRL_INPUTSEL_MASK 0xF00UL /**< Bit mask for ADC_INPUTSEL */
#define _ADC_SINGLECTRL_INPUTSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SINGLECTRL */
-#define _ADC_SINGLECTRL_INPUTSEL_CH0 0x00000000UL /**< Mode CH0 for ADC_SINGLECTRL */
#define _ADC_SINGLECTRL_INPUTSEL_CH0CH1 0x00000000UL /**< Mode CH0CH1 for ADC_SINGLECTRL */
-#define _ADC_SINGLECTRL_INPUTSEL_CH1 0x00000001UL /**< Mode CH1 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_INPUTSEL_CH0 0x00000000UL /**< Mode CH0 for ADC_SINGLECTRL */
#define _ADC_SINGLECTRL_INPUTSEL_CH2CH3 0x00000001UL /**< Mode CH2CH3 for ADC_SINGLECTRL */
-#define _ADC_SINGLECTRL_INPUTSEL_CH2 0x00000002UL /**< Mode CH2 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_INPUTSEL_CH1 0x00000001UL /**< Mode CH1 for ADC_SINGLECTRL */
#define _ADC_SINGLECTRL_INPUTSEL_CH4CH5 0x00000002UL /**< Mode CH4CH5 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_INPUTSEL_CH2 0x00000002UL /**< Mode CH2 for ADC_SINGLECTRL */
#define _ADC_SINGLECTRL_INPUTSEL_CH6CH7 0x00000003UL /**< Mode CH6CH7 for ADC_SINGLECTRL */
#define _ADC_SINGLECTRL_INPUTSEL_CH3 0x00000003UL /**< Mode CH3 for ADC_SINGLECTRL */
-#define _ADC_SINGLECTRL_INPUTSEL_CH4 0x00000004UL /**< Mode CH4 for ADC_SINGLECTRL */
#define _ADC_SINGLECTRL_INPUTSEL_DIFF0 0x00000004UL /**< Mode DIFF0 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_INPUTSEL_CH4 0x00000004UL /**< Mode CH4 for ADC_SINGLECTRL */
#define _ADC_SINGLECTRL_INPUTSEL_CH5 0x00000005UL /**< Mode CH5 for ADC_SINGLECTRL */
#define _ADC_SINGLECTRL_INPUTSEL_CH6 0x00000006UL /**< Mode CH6 for ADC_SINGLECTRL */
#define _ADC_SINGLECTRL_INPUTSEL_CH7 0x00000007UL /**< Mode CH7 for ADC_SINGLECTRL */
@@ -294,16 +292,16 @@ typedef struct {
#define _ADC_SINGLECTRL_INPUTSEL_DAC0OUT0 0x0000000DUL /**< Mode DAC0OUT0 for ADC_SINGLECTRL */
#define _ADC_SINGLECTRL_INPUTSEL_DAC0OUT1 0x0000000EUL /**< Mode DAC0OUT1 for ADC_SINGLECTRL */
#define ADC_SINGLECTRL_INPUTSEL_DEFAULT (_ADC_SINGLECTRL_INPUTSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for ADC_SINGLECTRL */
-#define ADC_SINGLECTRL_INPUTSEL_CH0 (_ADC_SINGLECTRL_INPUTSEL_CH0 << 8) /**< Shifted mode CH0 for ADC_SINGLECTRL */
#define ADC_SINGLECTRL_INPUTSEL_CH0CH1 (_ADC_SINGLECTRL_INPUTSEL_CH0CH1 << 8) /**< Shifted mode CH0CH1 for ADC_SINGLECTRL */
-#define ADC_SINGLECTRL_INPUTSEL_CH1 (_ADC_SINGLECTRL_INPUTSEL_CH1 << 8) /**< Shifted mode CH1 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_INPUTSEL_CH0 (_ADC_SINGLECTRL_INPUTSEL_CH0 << 8) /**< Shifted mode CH0 for ADC_SINGLECTRL */
#define ADC_SINGLECTRL_INPUTSEL_CH2CH3 (_ADC_SINGLECTRL_INPUTSEL_CH2CH3 << 8) /**< Shifted mode CH2CH3 for ADC_SINGLECTRL */
-#define ADC_SINGLECTRL_INPUTSEL_CH2 (_ADC_SINGLECTRL_INPUTSEL_CH2 << 8) /**< Shifted mode CH2 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_INPUTSEL_CH1 (_ADC_SINGLECTRL_INPUTSEL_CH1 << 8) /**< Shifted mode CH1 for ADC_SINGLECTRL */
#define ADC_SINGLECTRL_INPUTSEL_CH4CH5 (_ADC_SINGLECTRL_INPUTSEL_CH4CH5 << 8) /**< Shifted mode CH4CH5 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_INPUTSEL_CH2 (_ADC_SINGLECTRL_INPUTSEL_CH2 << 8) /**< Shifted mode CH2 for ADC_SINGLECTRL */
#define ADC_SINGLECTRL_INPUTSEL_CH6CH7 (_ADC_SINGLECTRL_INPUTSEL_CH6CH7 << 8) /**< Shifted mode CH6CH7 for ADC_SINGLECTRL */
#define ADC_SINGLECTRL_INPUTSEL_CH3 (_ADC_SINGLECTRL_INPUTSEL_CH3 << 8) /**< Shifted mode CH3 for ADC_SINGLECTRL */
-#define ADC_SINGLECTRL_INPUTSEL_CH4 (_ADC_SINGLECTRL_INPUTSEL_CH4 << 8) /**< Shifted mode CH4 for ADC_SINGLECTRL */
#define ADC_SINGLECTRL_INPUTSEL_DIFF0 (_ADC_SINGLECTRL_INPUTSEL_DIFF0 << 8) /**< Shifted mode DIFF0 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_INPUTSEL_CH4 (_ADC_SINGLECTRL_INPUTSEL_CH4 << 8) /**< Shifted mode CH4 for ADC_SINGLECTRL */
#define ADC_SINGLECTRL_INPUTSEL_CH5 (_ADC_SINGLECTRL_INPUTSEL_CH5 << 8) /**< Shifted mode CH5 for ADC_SINGLECTRL */
#define ADC_SINGLECTRL_INPUTSEL_CH6 (_ADC_SINGLECTRL_INPUTSEL_CH6 << 8) /**< Shifted mode CH6 for ADC_SINGLECTRL */
#define ADC_SINGLECTRL_INPUTSEL_CH7 (_ADC_SINGLECTRL_INPUTSEL_CH7 << 8) /**< Shifted mode CH7 for ADC_SINGLECTRL */
@@ -409,12 +407,12 @@ typedef struct {
#define _ADC_SCANCTRL_INPUTMASK_SHIFT 8 /**< Shift value for ADC_INPUTMASK */
#define _ADC_SCANCTRL_INPUTMASK_MASK 0xFF00UL /**< Bit mask for ADC_INPUTMASK */
#define _ADC_SCANCTRL_INPUTMASK_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SCANCTRL */
-#define _ADC_SCANCTRL_INPUTMASK_CH0 0x00000001UL /**< Mode CH0 for ADC_SCANCTRL */
#define _ADC_SCANCTRL_INPUTMASK_CH0CH1 0x00000001UL /**< Mode CH0CH1 for ADC_SCANCTRL */
-#define _ADC_SCANCTRL_INPUTMASK_CH1 0x00000002UL /**< Mode CH1 for ADC_SCANCTRL */
+#define _ADC_SCANCTRL_INPUTMASK_CH0 0x00000001UL /**< Mode CH0 for ADC_SCANCTRL */
#define _ADC_SCANCTRL_INPUTMASK_CH2CH3 0x00000002UL /**< Mode CH2CH3 for ADC_SCANCTRL */
-#define _ADC_SCANCTRL_INPUTMASK_CH2 0x00000004UL /**< Mode CH2 for ADC_SCANCTRL */
+#define _ADC_SCANCTRL_INPUTMASK_CH1 0x00000002UL /**< Mode CH1 for ADC_SCANCTRL */
#define _ADC_SCANCTRL_INPUTMASK_CH4CH5 0x00000004UL /**< Mode CH4CH5 for ADC_SCANCTRL */
+#define _ADC_SCANCTRL_INPUTMASK_CH2 0x00000004UL /**< Mode CH2 for ADC_SCANCTRL */
#define _ADC_SCANCTRL_INPUTMASK_CH6CH7 0x00000008UL /**< Mode CH6CH7 for ADC_SCANCTRL */
#define _ADC_SCANCTRL_INPUTMASK_CH3 0x00000008UL /**< Mode CH3 for ADC_SCANCTRL */
#define _ADC_SCANCTRL_INPUTMASK_CH4 0x00000010UL /**< Mode CH4 for ADC_SCANCTRL */
@@ -422,12 +420,12 @@ typedef struct {
#define _ADC_SCANCTRL_INPUTMASK_CH6 0x00000040UL /**< Mode CH6 for ADC_SCANCTRL */
#define _ADC_SCANCTRL_INPUTMASK_CH7 0x00000080UL /**< Mode CH7 for ADC_SCANCTRL */
#define ADC_SCANCTRL_INPUTMASK_DEFAULT (_ADC_SCANCTRL_INPUTMASK_DEFAULT << 8) /**< Shifted mode DEFAULT for ADC_SCANCTRL */
-#define ADC_SCANCTRL_INPUTMASK_CH0 (_ADC_SCANCTRL_INPUTMASK_CH0 << 8) /**< Shifted mode CH0 for ADC_SCANCTRL */
#define ADC_SCANCTRL_INPUTMASK_CH0CH1 (_ADC_SCANCTRL_INPUTMASK_CH0CH1 << 8) /**< Shifted mode CH0CH1 for ADC_SCANCTRL */
-#define ADC_SCANCTRL_INPUTMASK_CH1 (_ADC_SCANCTRL_INPUTMASK_CH1 << 8) /**< Shifted mode CH1 for ADC_SCANCTRL */
+#define ADC_SCANCTRL_INPUTMASK_CH0 (_ADC_SCANCTRL_INPUTMASK_CH0 << 8) /**< Shifted mode CH0 for ADC_SCANCTRL */
#define ADC_SCANCTRL_INPUTMASK_CH2CH3 (_ADC_SCANCTRL_INPUTMASK_CH2CH3 << 8) /**< Shifted mode CH2CH3 for ADC_SCANCTRL */
-#define ADC_SCANCTRL_INPUTMASK_CH2 (_ADC_SCANCTRL_INPUTMASK_CH2 << 8) /**< Shifted mode CH2 for ADC_SCANCTRL */
+#define ADC_SCANCTRL_INPUTMASK_CH1 (_ADC_SCANCTRL_INPUTMASK_CH1 << 8) /**< Shifted mode CH1 for ADC_SCANCTRL */
#define ADC_SCANCTRL_INPUTMASK_CH4CH5 (_ADC_SCANCTRL_INPUTMASK_CH4CH5 << 8) /**< Shifted mode CH4CH5 for ADC_SCANCTRL */
+#define ADC_SCANCTRL_INPUTMASK_CH2 (_ADC_SCANCTRL_INPUTMASK_CH2 << 8) /**< Shifted mode CH2 for ADC_SCANCTRL */
#define ADC_SCANCTRL_INPUTMASK_CH6CH7 (_ADC_SCANCTRL_INPUTMASK_CH6CH7 << 8) /**< Shifted mode CH6CH7 for ADC_SCANCTRL */
#define ADC_SCANCTRL_INPUTMASK_CH3 (_ADC_SCANCTRL_INPUTMASK_CH3 << 8) /**< Shifted mode CH3 for ADC_SCANCTRL */
#define ADC_SCANCTRL_INPUTMASK_CH4 (_ADC_SCANCTRL_INPUTMASK_CH4 << 8) /**< Shifted mode CH4 for ADC_SCANCTRL */
diff --git a/cpu/efm32/families/efm32zg/include/vendor/efm32zg_aes.h b/cpu/efm32/families/efm32zg/include/vendor/efm32zg_aes.h
index fd636af700..8156431c56 100644
--- a/cpu/efm32/families/efm32zg/include/vendor/efm32zg_aes.h
+++ b/cpu/efm32/families/efm32zg/include/vendor/efm32zg_aes.h
@@ -1,34 +1,32 @@
-/**************************************************************************//**
- * @file efm32zg_aes.h
+/***************************************************************************//**
+ * @file
* @brief EFM32ZG_AES register and bit field definitions
- * @version 5.4.0
- ******************************************************************************
+ *******************************************************************************
* # License
- * Copyright 2017 Silicon Laboratories, Inc. www.silabs.com
- ******************************************************************************
+ * Copyright 2020 Silicon Laboratories Inc. www.silabs.com
+ *******************************************************************************
+ *
+ * SPDX-License-Identifier: Zlib
+ *
+ * The licensor of this software is Silicon Laboratories Inc.
+ *
+ * This software is provided 'as-is', without any express or implied
+ * warranty. In no event will the authors be held liable for any damages
+ * arising from the use of this software.
*
* Permission is granted to anyone to use this software for any purpose,
* including commercial applications, and to alter it and redistribute it
* freely, subject to the following restrictions:
*
* 1. The origin of this software must not be misrepresented; you must not
- * claim that you wrote the original software.@n
+ * claim that you wrote the original software. If you use this software
+ * in a product, an acknowledgment in the product documentation would be
+ * appreciated but is not required.
* 2. Altered source versions must be plainly marked as such, and must not be
- * misrepresented as being the original software.@n
+ * misrepresented as being the original software.
* 3. This notice may not be removed or altered from any source distribution.
*
- * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
- * has no obligation to support this Software. Silicon Laboratories, Inc. is
- * providing the Software "AS IS", with no express or implied warranties of any
- * kind, including, but not limited to, any implied warranties of
- * merchantability or fitness for any particular purpose or warranties against
- * infringement of any proprietary rights of a third party.
- *
- * Silicon Laboratories, Inc. will not be liable for any consequential,
- * incidental, or special damages, or any other relief, or for any claim by
- * any third party, arising from your use of this Software.
- *
- *****************************************************************************/
+ ******************************************************************************/
#ifdef __cplusplus
extern "C" {
@@ -41,36 +39,36 @@ extern "C" {
#pragma clang system_header /* Treat file as system include file. */
#endif
-/**************************************************************************//**
-* @addtogroup Parts
-* @{
-******************************************************************************/
-/**************************************************************************//**
+/***************************************************************************//**
+ * @addtogroup Parts
+ * @{
+ ******************************************************************************/
+/***************************************************************************//**
* @defgroup EFM32ZG_AES
* @{
* @brief EFM32ZG_AES Register Declaration
- *****************************************************************************/
+ ******************************************************************************/
typedef struct {
- __IOM uint32_t CTRL; /**< Control Register */
- __IOM uint32_t CMD; /**< Command Register */
- __IM uint32_t STATUS; /**< Status Register */
- __IOM uint32_t IEN; /**< Interrupt Enable Register */
- __IM uint32_t IF; /**< Interrupt Flag Register */
- __IOM uint32_t IFS; /**< Interrupt Flag Set Register */
- __IOM uint32_t IFC; /**< Interrupt Flag Clear Register */
- __IOM uint32_t DATA; /**< DATA Register */
- __IOM uint32_t XORDATA; /**< XORDATA Register */
- uint32_t RESERVED0[3]; /**< Reserved for future use **/
- __IOM uint32_t KEYLA; /**< KEY Low Register */
- __IOM uint32_t KEYLB; /**< KEY Low Register */
- __IOM uint32_t KEYLC; /**< KEY Low Register */
- __IOM uint32_t KEYLD; /**< KEY Low Register */
-} AES_TypeDef; /** AES Register Declaration *//** @} */
+ __IOM uint32_t CTRL; /**< Control Register */
+ __IOM uint32_t CMD; /**< Command Register */
+ __IM uint32_t STATUS; /**< Status Register */
+ __IOM uint32_t IEN; /**< Interrupt Enable Register */
+ __IM uint32_t IF; /**< Interrupt Flag Register */
+ __IOM uint32_t IFS; /**< Interrupt Flag Set Register */
+ __IOM uint32_t IFC; /**< Interrupt Flag Clear Register */
+ __IOM uint32_t DATA; /**< DATA Register */
+ __IOM uint32_t XORDATA; /**< XORDATA Register */
+ uint32_t RESERVED0[3U]; /**< Reserved for future use **/
+ __IOM uint32_t KEYLA; /**< KEY Low Register */
+ __IOM uint32_t KEYLB; /**< KEY Low Register */
+ __IOM uint32_t KEYLC; /**< KEY Low Register */
+ __IOM uint32_t KEYLD; /**< KEY Low Register */
+} AES_TypeDef; /** AES Register Declaration *//** @} */
-/**************************************************************************//**
+/***************************************************************************//**
* @defgroup EFM32ZG_AES_BitFields
* @{
- *****************************************************************************/
+ ******************************************************************************/
/* Bit fields for AES CTRL */
#define _AES_CTRL_RESETVALUE 0x00000000UL /**< Default value for AES_CTRL */
diff --git a/cpu/efm32/families/efm32zg/include/vendor/efm32zg_af_pins.h b/cpu/efm32/families/efm32zg/include/vendor/efm32zg_af_pins.h
index d7261ac17e..fba3684622 100644
--- a/cpu/efm32/families/efm32zg/include/vendor/efm32zg_af_pins.h
+++ b/cpu/efm32/families/efm32zg/include/vendor/efm32zg_af_pins.h
@@ -1,34 +1,32 @@
-/**************************************************************************//**
- * @file efm32zg_af_pins.h
+/***************************************************************************//**
+ * @file
* @brief EFM32ZG_AF_PINS register and bit field definitions
- * @version 5.4.0
- ******************************************************************************
+ *******************************************************************************
* # License
- * Copyright 2017 Silicon Laboratories, Inc. www.silabs.com
- ******************************************************************************
+ * Copyright 2020 Silicon Laboratories Inc. www.silabs.com
+ *******************************************************************************
+ *
+ * SPDX-License-Identifier: Zlib
+ *
+ * The licensor of this software is Silicon Laboratories Inc.
+ *
+ * This software is provided 'as-is', without any express or implied
+ * warranty. In no event will the authors be held liable for any damages
+ * arising from the use of this software.
*
* Permission is granted to anyone to use this software for any purpose,
* including commercial applications, and to alter it and redistribute it
* freely, subject to the following restrictions:
*
* 1. The origin of this software must not be misrepresented; you must not
- * claim that you wrote the original software.@n
+ * claim that you wrote the original software. If you use this software
+ * in a product, an acknowledgment in the product documentation would be
+ * appreciated but is not required.
* 2. Altered source versions must be plainly marked as such, and must not be
- * misrepresented as being the original software.@n
+ * misrepresented as being the original software.
* 3. This notice may not be removed or altered from any source distribution.
*
- * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
- * has no obligation to support this Software. Silicon Laboratories, Inc. is
- * providing the Software "AS IS", with no express or implied warranties of any
- * kind, including, but not limited to, any implied warranties of
- * merchantability or fitness for any particular purpose or warranties against
- * infringement of any proprietary rights of a third party.
- *
- * Silicon Laboratories, Inc. will not be liable for any consequential,
- * incidental, or special damages, or any other relief, or for any claim by
- * any third party, arising from your use of this Software.
- *
- *****************************************************************************/
+ ******************************************************************************/
#ifdef __cplusplus
extern "C" {
@@ -41,14 +39,14 @@ extern "C" {
#pragma clang system_header /* Treat file as system include file. */
#endif
-/**************************************************************************//**
-* @addtogroup Parts
-* @{
-******************************************************************************/
-/**************************************************************************//**
+/***************************************************************************//**
+ * @addtogroup Parts
+ * @{
+ ******************************************************************************/
+/***************************************************************************//**
* @defgroup EFM32ZG_AF_Pins
* @{
- *****************************************************************************/
+ ******************************************************************************/
#define AF_CMU_CLK0_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? -1 : (i) == 2 ? 7 : -1) /**< Pin number for AF_CMU_CLK0 location number i */
#define AF_CMU_CLK1_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? -1 : (i) == 2 ? 12 : -1) /**< Pin number for AF_CMU_CLK1 location number i */
diff --git a/cpu/efm32/families/efm32zg/include/vendor/efm32zg_af_ports.h b/cpu/efm32/families/efm32zg/include/vendor/efm32zg_af_ports.h
index 428dc49287..3053269cfb 100644
--- a/cpu/efm32/families/efm32zg/include/vendor/efm32zg_af_ports.h
+++ b/cpu/efm32/families/efm32zg/include/vendor/efm32zg_af_ports.h
@@ -1,34 +1,32 @@
-/**************************************************************************//**
- * @file efm32zg_af_ports.h
+/***************************************************************************//**
+ * @file
* @brief EFM32ZG_AF_PORTS register and bit field definitions
- * @version 5.4.0
- ******************************************************************************
+ *******************************************************************************
* # License
- * Copyright 2017 Silicon Laboratories, Inc. www.silabs.com
- ******************************************************************************
+ * Copyright 2020 Silicon Laboratories Inc. www.silabs.com
+ *******************************************************************************
+ *
+ * SPDX-License-Identifier: Zlib
+ *
+ * The licensor of this software is Silicon Laboratories Inc.
+ *
+ * This software is provided 'as-is', without any express or implied
+ * warranty. In no event will the authors be held liable for any damages
+ * arising from the use of this software.
*
* Permission is granted to anyone to use this software for any purpose,
* including commercial applications, and to alter it and redistribute it
* freely, subject to the following restrictions:
*
* 1. The origin of this software must not be misrepresented; you must not
- * claim that you wrote the original software.@n
+ * claim that you wrote the original software. If you use this software
+ * in a product, an acknowledgment in the product documentation would be
+ * appreciated but is not required.
* 2. Altered source versions must be plainly marked as such, and must not be
- * misrepresented as being the original software.@n
+ * misrepresented as being the original software.
* 3. This notice may not be removed or altered from any source distribution.
*
- * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
- * has no obligation to support this Software. Silicon Laboratories, Inc. is
- * providing the Software "AS IS", with no express or implied warranties of any
- * kind, including, but not limited to, any implied warranties of
- * merchantability or fitness for any particular purpose or warranties against
- * infringement of any proprietary rights of a third party.
- *
- * Silicon Laboratories, Inc. will not be liable for any consequential,
- * incidental, or special damages, or any other relief, or for any claim by
- * any third party, arising from your use of this Software.
- *
- *****************************************************************************/
+ ******************************************************************************/
#ifdef __cplusplus
extern "C" {
@@ -41,14 +39,14 @@ extern "C" {
#pragma clang system_header /* Treat file as system include file. */
#endif
-/**************************************************************************//**
-* @addtogroup Parts
-* @{
-******************************************************************************/
-/**************************************************************************//**
+/***************************************************************************//**
+ * @addtogroup Parts
+ * @{
+ ******************************************************************************/
+/***************************************************************************//**
* @defgroup EFM32ZG_AF_Ports
* @{
- *****************************************************************************/
+ ******************************************************************************/
#define AF_CMU_CLK0_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? -1 : (i) == 2 ? 3 : -1) /**< Port number for AF_CMU_CLK0 location number i */
#define AF_CMU_CLK1_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? -1 : (i) == 2 ? 4 : -1) /**< Port number for AF_CMU_CLK1 location number i */
diff --git a/cpu/efm32/families/efm32zg/include/vendor/efm32zg_calibrate.h b/cpu/efm32/families/efm32zg/include/vendor/efm32zg_calibrate.h
index 717897520a..b5ed6c0e84 100644
--- a/cpu/efm32/families/efm32zg/include/vendor/efm32zg_calibrate.h
+++ b/cpu/efm32/families/efm32zg/include/vendor/efm32zg_calibrate.h
@@ -1,34 +1,32 @@
-/**************************************************************************//**
- * @file efm32zg_calibrate.h
+/***************************************************************************//**
+ * @file
* @brief EFM32ZG_CALIBRATE register and bit field definitions
- * @version 5.4.0
- ******************************************************************************
+ *******************************************************************************
* # License
- * Copyright 2017 Silicon Laboratories, Inc. www.silabs.com
- ******************************************************************************
+ * Copyright 2020 Silicon Laboratories Inc. www.silabs.com
+ *******************************************************************************
+ *
+ * SPDX-License-Identifier: Zlib
+ *
+ * The licensor of this software is Silicon Laboratories Inc.
+ *
+ * This software is provided 'as-is', without any express or implied
+ * warranty. In no event will the authors be held liable for any damages
+ * arising from the use of this software.
*
* Permission is granted to anyone to use this software for any purpose,
* including commercial applications, and to alter it and redistribute it
* freely, subject to the following restrictions:
*
* 1. The origin of this software must not be misrepresented; you must not
- * claim that you wrote the original software.@n
+ * claim that you wrote the original software. If you use this software
+ * in a product, an acknowledgment in the product documentation would be
+ * appreciated but is not required.
* 2. Altered source versions must be plainly marked as such, and must not be
- * misrepresented as being the original software.@n
+ * misrepresented as being the original software.
* 3. This notice may not be removed or altered from any source distribution.
*
- * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
- * has no obligation to support this Software. Silicon Laboratories, Inc. is
- * providing the Software "AS IS", with no express or implied warranties of any
- * kind, including, but not limited to, any implied warranties of
- * merchantability or fitness for any particular purpose or warranties against
- * infringement of any proprietary rights of a third party.
- *
- * Silicon Laboratories, Inc. will not be liable for any consequential,
- * incidental, or special damages, or any other relief, or for any claim by
- * any third party, arising from your use of this Software.
- *
- *****************************************************************************/
+ ******************************************************************************/
#ifdef __cplusplus
extern "C" {
@@ -41,14 +39,14 @@ extern "C" {
#pragma clang system_header /* Treat file as system include file. */
#endif
-/**************************************************************************//**
-* @addtogroup Parts
-* @{
-******************************************************************************/
-/**************************************************************************//**
+/***************************************************************************//**
+ * @addtogroup Parts
+ * @{
+ ******************************************************************************/
+/***************************************************************************//**
* @defgroup EFM32ZG_CALIBRATE
* @{
- *****************************************************************************/
+ ******************************************************************************/
#define CALIBRATE_MAX_REGISTERS 50 /**< Max number of address/value pairs for calibration */
typedef struct {
diff --git a/cpu/efm32/families/efm32zg/include/vendor/efm32zg_cmu.h b/cpu/efm32/families/efm32zg/include/vendor/efm32zg_cmu.h
index 7e6a0224f0..15ffaca9ca 100644
--- a/cpu/efm32/families/efm32zg/include/vendor/efm32zg_cmu.h
+++ b/cpu/efm32/families/efm32zg/include/vendor/efm32zg_cmu.h
@@ -1,34 +1,32 @@
-/**************************************************************************//**
- * @file efm32zg_cmu.h
+/***************************************************************************//**
+ * @file
* @brief EFM32ZG_CMU register and bit field definitions
- * @version 5.4.0
- ******************************************************************************
+ *******************************************************************************
* # License
- * Copyright 2017 Silicon Laboratories, Inc. www.silabs.com
- ******************************************************************************
+ * Copyright 2020 Silicon Laboratories Inc. www.silabs.com
+ *******************************************************************************
+ *
+ * SPDX-License-Identifier: Zlib
+ *
+ * The licensor of this software is Silicon Laboratories Inc.
+ *
+ * This software is provided 'as-is', without any express or implied
+ * warranty. In no event will the authors be held liable for any damages
+ * arising from the use of this software.
*
* Permission is granted to anyone to use this software for any purpose,
* including commercial applications, and to alter it and redistribute it
* freely, subject to the following restrictions:
*
* 1. The origin of this software must not be misrepresented; you must not
- * claim that you wrote the original software.@n
+ * claim that you wrote the original software. If you use this software
+ * in a product, an acknowledgment in the product documentation would be
+ * appreciated but is not required.
* 2. Altered source versions must be plainly marked as such, and must not be
- * misrepresented as being the original software.@n
+ * misrepresented as being the original software.
* 3. This notice may not be removed or altered from any source distribution.
*
- * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
- * has no obligation to support this Software. Silicon Laboratories, Inc. is
- * providing the Software "AS IS", with no express or implied warranties of any
- * kind, including, but not limited to, any implied warranties of
- * merchantability or fitness for any particular purpose or warranties against
- * infringement of any proprietary rights of a third party.
- *
- * Silicon Laboratories, Inc. will not be liable for any consequential,
- * incidental, or special damages, or any other relief, or for any claim by
- * any third party, arising from your use of this Software.
- *
- *****************************************************************************/
+ ******************************************************************************/
#ifdef __cplusplus
extern "C" {
@@ -41,57 +39,57 @@ extern "C" {
#pragma clang system_header /* Treat file as system include file. */
#endif
-/**************************************************************************//**
-* @addtogroup Parts
-* @{
-******************************************************************************/
-/**************************************************************************//**
+/***************************************************************************//**
+ * @addtogroup Parts
+ * @{
+ ******************************************************************************/
+/***************************************************************************//**
* @defgroup EFM32ZG_CMU
* @{
* @brief EFM32ZG_CMU Register Declaration
- *****************************************************************************/
+ ******************************************************************************/
typedef struct {
- __IOM uint32_t CTRL; /**< CMU Control Register */
- __IOM uint32_t HFCORECLKDIV; /**< High Frequency Core Clock Division Register */
- __IOM uint32_t HFPERCLKDIV; /**< High Frequency Peripheral Clock Division Register */
- __IOM uint32_t HFRCOCTRL; /**< HFRCO Control Register */
- __IOM uint32_t LFRCOCTRL; /**< LFRCO Control Register */
- __IOM uint32_t AUXHFRCOCTRL; /**< AUXHFRCO Control Register */
- __IOM uint32_t CALCTRL; /**< Calibration Control Register */
- __IOM uint32_t CALCNT; /**< Calibration Counter Register */
- __IOM uint32_t OSCENCMD; /**< Oscillator Enable/Disable Command Register */
- __IOM uint32_t CMD; /**< Command Register */
- __IOM uint32_t LFCLKSEL; /**< Low Frequency Clock Select Register */
- __IM uint32_t STATUS; /**< Status Register */
- __IM uint32_t IF; /**< Interrupt Flag Register */
- __IOM uint32_t IFS; /**< Interrupt Flag Set Register */
- __IOM uint32_t IFC; /**< Interrupt Flag Clear Register */
- __IOM uint32_t IEN; /**< Interrupt Enable Register */
- __IOM uint32_t HFCORECLKEN0; /**< High Frequency Core Clock Enable Register 0 */
- __IOM uint32_t HFPERCLKEN0; /**< High Frequency Peripheral Clock Enable Register 0 */
- uint32_t RESERVED0[2]; /**< Reserved for future use **/
- __IM uint32_t SYNCBUSY; /**< Synchronization Busy Register */
- __IOM uint32_t FREEZE; /**< Freeze Register */
- __IOM uint32_t LFACLKEN0; /**< Low Frequency A Clock Enable Register 0 (Async Reg) */
- uint32_t RESERVED1[1]; /**< Reserved for future use **/
- __IOM uint32_t LFBCLKEN0; /**< Low Frequency B Clock Enable Register 0 (Async Reg) */
+ __IOM uint32_t CTRL; /**< CMU Control Register */
+ __IOM uint32_t HFCORECLKDIV; /**< High Frequency Core Clock Division Register */
+ __IOM uint32_t HFPERCLKDIV; /**< High Frequency Peripheral Clock Division Register */
+ __IOM uint32_t HFRCOCTRL; /**< HFRCO Control Register */
+ __IOM uint32_t LFRCOCTRL; /**< LFRCO Control Register */
+ __IOM uint32_t AUXHFRCOCTRL; /**< AUXHFRCO Control Register */
+ __IOM uint32_t CALCTRL; /**< Calibration Control Register */
+ __IOM uint32_t CALCNT; /**< Calibration Counter Register */
+ __IOM uint32_t OSCENCMD; /**< Oscillator Enable/Disable Command Register */
+ __IOM uint32_t CMD; /**< Command Register */
+ __IOM uint32_t LFCLKSEL; /**< Low Frequency Clock Select Register */
+ __IM uint32_t STATUS; /**< Status Register */
+ __IM uint32_t IF; /**< Interrupt Flag Register */
+ __IOM uint32_t IFS; /**< Interrupt Flag Set Register */
+ __IOM uint32_t IFC; /**< Interrupt Flag Clear Register */
+ __IOM uint32_t IEN; /**< Interrupt Enable Register */
+ __IOM uint32_t HFCORECLKEN0; /**< High Frequency Core Clock Enable Register 0 */
+ __IOM uint32_t HFPERCLKEN0; /**< High Frequency Peripheral Clock Enable Register 0 */
+ uint32_t RESERVED0[2U]; /**< Reserved for future use **/
+ __IM uint32_t SYNCBUSY; /**< Synchronization Busy Register */
+ __IOM uint32_t FREEZE; /**< Freeze Register */
+ __IOM uint32_t LFACLKEN0; /**< Low Frequency A Clock Enable Register 0 (Async Reg) */
+ uint32_t RESERVED1[1U]; /**< Reserved for future use **/
+ __IOM uint32_t LFBCLKEN0; /**< Low Frequency B Clock Enable Register 0 (Async Reg) */
- uint32_t RESERVED2[1]; /**< Reserved for future use **/
- __IOM uint32_t LFAPRESC0; /**< Low Frequency A Prescaler Register 0 (Async Reg) */
- uint32_t RESERVED3[1]; /**< Reserved for future use **/
- __IOM uint32_t LFBPRESC0; /**< Low Frequency B Prescaler Register 0 (Async Reg) */
- uint32_t RESERVED4[1]; /**< Reserved for future use **/
- __IOM uint32_t PCNTCTRL; /**< PCNT Control Register */
+ uint32_t RESERVED2[1U]; /**< Reserved for future use **/
+ __IOM uint32_t LFAPRESC0; /**< Low Frequency A Prescaler Register 0 (Async Reg) */
+ uint32_t RESERVED3[1U]; /**< Reserved for future use **/
+ __IOM uint32_t LFBPRESC0; /**< Low Frequency B Prescaler Register 0 (Async Reg) */
+ uint32_t RESERVED4[1U]; /**< Reserved for future use **/
+ __IOM uint32_t PCNTCTRL; /**< PCNT Control Register */
- uint32_t RESERVED5[1]; /**< Reserved for future use **/
- __IOM uint32_t ROUTE; /**< I/O Routing Register */
- __IOM uint32_t LOCK; /**< Configuration Lock Register */
-} CMU_TypeDef; /** CMU Register Declaration *//** @} */
+ uint32_t RESERVED5[1U]; /**< Reserved for future use **/
+ __IOM uint32_t ROUTE; /**< I/O Routing Register */
+ __IOM uint32_t LOCK; /**< Configuration Lock Register */
+} CMU_TypeDef; /** CMU Register Declaration *//** @} */
-/**************************************************************************//**
+/***************************************************************************//**
* @defgroup EFM32ZG_CMU_BitFields
* @{
- *****************************************************************************/
+ ******************************************************************************/
/* Bit fields for CMU CTRL */
#define _CMU_CTRL_RESETVALUE 0x000C262CUL /**< Default value for CMU_CTRL */
@@ -978,13 +976,13 @@ typedef struct {
#define _CMU_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for CMU_LOCKKEY */
#define _CMU_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for CMU_LOCKKEY */
#define _CMU_LOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LOCK */
-#define _CMU_LOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for CMU_LOCK */
#define _CMU_LOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for CMU_LOCK */
+#define _CMU_LOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for CMU_LOCK */
#define _CMU_LOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for CMU_LOCK */
#define _CMU_LOCK_LOCKKEY_UNLOCK 0x0000580EUL /**< Mode UNLOCK for CMU_LOCK */
#define CMU_LOCK_LOCKKEY_DEFAULT (_CMU_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LOCK */
-#define CMU_LOCK_LOCKKEY_LOCK (_CMU_LOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for CMU_LOCK */
#define CMU_LOCK_LOCKKEY_UNLOCKED (_CMU_LOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for CMU_LOCK */
+#define CMU_LOCK_LOCKKEY_LOCK (_CMU_LOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for CMU_LOCK */
#define CMU_LOCK_LOCKKEY_LOCKED (_CMU_LOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for CMU_LOCK */
#define CMU_LOCK_LOCKKEY_UNLOCK (_CMU_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for CMU_LOCK */
diff --git a/cpu/efm32/families/efm32zg/include/vendor/efm32zg_devinfo.h b/cpu/efm32/families/efm32zg/include/vendor/efm32zg_devinfo.h
index 4b78e751e6..78380651a0 100644
--- a/cpu/efm32/families/efm32zg/include/vendor/efm32zg_devinfo.h
+++ b/cpu/efm32/families/efm32zg/include/vendor/efm32zg_devinfo.h
@@ -1,34 +1,32 @@
-/**************************************************************************//**
- * @file efm32zg_devinfo.h
+/***************************************************************************//**
+ * @file
* @brief EFM32ZG_DEVINFO register and bit field definitions
- * @version 5.4.0
- ******************************************************************************
+ *******************************************************************************
* # License
- * Copyright 2017 Silicon Laboratories, Inc. www.silabs.com
- ******************************************************************************
+ * Copyright 2020 Silicon Laboratories Inc. www.silabs.com
+ *******************************************************************************
+ *
+ * SPDX-License-Identifier: Zlib
+ *
+ * The licensor of this software is Silicon Laboratories Inc.
+ *
+ * This software is provided 'as-is', without any express or implied
+ * warranty. In no event will the authors be held liable for any damages
+ * arising from the use of this software.
*
* Permission is granted to anyone to use this software for any purpose,
* including commercial applications, and to alter it and redistribute it
* freely, subject to the following restrictions:
*
* 1. The origin of this software must not be misrepresented; you must not
- * claim that you wrote the original software.@n
+ * claim that you wrote the original software. If you use this software
+ * in a product, an acknowledgment in the product documentation would be
+ * appreciated but is not required.
* 2. Altered source versions must be plainly marked as such, and must not be
- * misrepresented as being the original software.@n
+ * misrepresented as being the original software.
* 3. This notice may not be removed or altered from any source distribution.
*
- * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
- * has no obligation to support this Software. Silicon Laboratories, Inc. is
- * providing the Software "AS IS", with no express or implied warranties of any
- * kind, including, but not limited to, any implied warranties of
- * merchantability or fitness for any particular purpose or warranties against
- * infringement of any proprietary rights of a third party.
- *
- * Silicon Laboratories, Inc. will not be liable for any consequential,
- * incidental, or special damages, or any other relief, or for any claim by
- * any third party, arising from your use of this Software.
- *
- *****************************************************************************/
+ ******************************************************************************/
#ifdef __cplusplus
extern "C" {
@@ -41,38 +39,38 @@ extern "C" {
#pragma clang system_header /* Treat file as system include file. */
#endif
-/**************************************************************************//**
-* @addtogroup Parts
-* @{
-******************************************************************************/
-/**************************************************************************//**
+/***************************************************************************//**
+ * @addtogroup Parts
+ * @{
+ ******************************************************************************/
+/***************************************************************************//**
* @defgroup EFM32ZG_DEVINFO
* @{
- *****************************************************************************/
+ ******************************************************************************/
typedef struct {
- __IM uint32_t CAL; /**< Calibration temperature and checksum */
- __IM uint32_t ADC0CAL0; /**< ADC0 Calibration register 0 */
- __IM uint32_t ADC0CAL1; /**< ADC0 Calibration register 1 */
- __IM uint32_t ADC0CAL2; /**< ADC0 Calibration register 2 */
- uint32_t RESERVED0[2]; /**< Reserved */
- __IM uint32_t IDAC0CAL0; /**< IDAC0 calibration register */
- uint32_t RESERVED1[2]; /**< Reserved */
- __IM uint32_t AUXHFRCOCAL0; /**< AUXHFRCO calibration register 0 */
- __IM uint32_t AUXHFRCOCAL1; /**< AUXHFRCO calibration register 1 */
- __IM uint32_t HFRCOCAL0; /**< HFRCO calibration register 0 */
- __IM uint32_t HFRCOCAL1; /**< HFRCO calibration register 1 */
- __IM uint32_t MEMINFO; /**< Memory information */
- uint32_t RESERVED2[2]; /**< Reserved */
- __IM uint32_t UNIQUEL; /**< Low 32 bits of device unique number */
- __IM uint32_t UNIQUEH; /**< High 32 bits of device unique number */
- __IM uint32_t MSIZE; /**< Flash and SRAM Memory size in KiloBytes */
- __IM uint32_t PART; /**< Part description */
-} DEVINFO_TypeDef; /** @} */
+ __IM uint32_t CAL; /**< Calibration temperature and checksum */
+ __IM uint32_t ADC0CAL0; /**< ADC0 Calibration register 0 */
+ __IM uint32_t ADC0CAL1; /**< ADC0 Calibration register 1 */
+ __IM uint32_t ADC0CAL2; /**< ADC0 Calibration register 2 */
+ uint32_t RESERVED0[2U]; /**< Reserved */
+ __IM uint32_t IDAC0CAL0; /**< IDAC0 calibration register */
+ uint32_t RESERVED1[2U]; /**< Reserved */
+ __IM uint32_t AUXHFRCOCAL0; /**< AUXHFRCO calibration register 0 */
+ __IM uint32_t AUXHFRCOCAL1; /**< AUXHFRCO calibration register 1 */
+ __IM uint32_t HFRCOCAL0; /**< HFRCO calibration register 0 */
+ __IM uint32_t HFRCOCAL1; /**< HFRCO calibration register 1 */
+ __IM uint32_t MEMINFO; /**< Memory information */
+ uint32_t RESERVED2[2U]; /**< Reserved */
+ __IM uint32_t UNIQUEL; /**< Low 32 bits of device unique number */
+ __IM uint32_t UNIQUEH; /**< High 32 bits of device unique number */
+ __IM uint32_t MSIZE; /**< Flash and SRAM Memory size in KiloBytes */
+ __IM uint32_t PART; /**< Part description */
+} DEVINFO_TypeDef; /** @} */
-/**************************************************************************//**
+/***************************************************************************//**
* @defgroup EFM32ZG_DEVINFO_BitFields
* @{
- *****************************************************************************/
+ ******************************************************************************/
/* Bit fields for EFM32ZG_DEVINFO */
#define _DEVINFO_CAL_CRC_MASK 0x0000FFFFUL /**< Integrity CRC checksum mask */
#define _DEVINFO_CAL_CRC_SHIFT 0 /**< Integrity CRC checksum shift */
diff --git a/cpu/efm32/families/efm32zg/include/vendor/efm32zg_dma.h b/cpu/efm32/families/efm32zg/include/vendor/efm32zg_dma.h
index 9f0934d76a..4bfe93b175 100644
--- a/cpu/efm32/families/efm32zg/include/vendor/efm32zg_dma.h
+++ b/cpu/efm32/families/efm32zg/include/vendor/efm32zg_dma.h
@@ -1,34 +1,32 @@
-/**************************************************************************//**
- * @file efm32zg_dma.h
+/***************************************************************************//**
+ * @file
* @brief EFM32ZG_DMA register and bit field definitions
- * @version 5.4.0
- ******************************************************************************
+ *******************************************************************************
* # License
- * Copyright 2017 Silicon Laboratories, Inc. www.silabs.com
- ******************************************************************************
+ * Copyright 2020 Silicon Laboratories Inc. www.silabs.com
+ *******************************************************************************
+ *
+ * SPDX-License-Identifier: Zlib
+ *
+ * The licensor of this software is Silicon Laboratories Inc.
+ *
+ * This software is provided 'as-is', without any express or implied
+ * warranty. In no event will the authors be held liable for any damages
+ * arising from the use of this software.
*
* Permission is granted to anyone to use this software for any purpose,
* including commercial applications, and to alter it and redistribute it
* freely, subject to the following restrictions:
*
* 1. The origin of this software must not be misrepresented; you must not
- * claim that you wrote the original software.@n
+ * claim that you wrote the original software. If you use this software
+ * in a product, an acknowledgment in the product documentation would be
+ * appreciated but is not required.
* 2. Altered source versions must be plainly marked as such, and must not be
- * misrepresented as being the original software.@n
+ * misrepresented as being the original software.
* 3. This notice may not be removed or altered from any source distribution.
*
- * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
- * has no obligation to support this Software. Silicon Laboratories, Inc. is
- * providing the Software "AS IS", with no express or implied warranties of any
- * kind, including, but not limited to, any implied warranties of
- * merchantability or fitness for any particular purpose or warranties against
- * infringement of any proprietary rights of a third party.
- *
- * Silicon Laboratories, Inc. will not be liable for any consequential,
- * incidental, or special damages, or any other relief, or for any claim by
- * any third party, arising from your use of this Software.
- *
- *****************************************************************************/
+ ******************************************************************************/
#ifdef __cplusplus
extern "C" {
@@ -41,54 +39,54 @@ extern "C" {
#pragma clang system_header /* Treat file as system include file. */
#endif
-/**************************************************************************//**
-* @addtogroup Parts
-* @{
-******************************************************************************/
-/**************************************************************************//**
+/***************************************************************************//**
+ * @addtogroup Parts
+ * @{
+ ******************************************************************************/
+/***************************************************************************//**
* @defgroup EFM32ZG_DMA
* @{
* @brief EFM32ZG_DMA Register Declaration
- *****************************************************************************/
+ ******************************************************************************/
typedef struct {
- __IM uint32_t STATUS; /**< DMA Status Registers */
- __OM uint32_t CONFIG; /**< DMA Configuration Register */
- __IOM uint32_t CTRLBASE; /**< Channel Control Data Base Pointer Register */
- __IM uint32_t ALTCTRLBASE; /**< Channel Alternate Control Data Base Pointer Register */
- __IM uint32_t CHWAITSTATUS; /**< Channel Wait on Request Status Register */
- __OM uint32_t CHSWREQ; /**< Channel Software Request Register */
- __IOM uint32_t CHUSEBURSTS; /**< Channel Useburst Set Register */
- __OM uint32_t CHUSEBURSTC; /**< Channel Useburst Clear Register */
- __IOM uint32_t CHREQMASKS; /**< Channel Request Mask Set Register */
- __OM uint32_t CHREQMASKC; /**< Channel Request Mask Clear Register */
- __IOM uint32_t CHENS; /**< Channel Enable Set Register */
- __OM uint32_t CHENC; /**< Channel Enable Clear Register */
- __IOM uint32_t CHALTS; /**< Channel Alternate Set Register */
- __OM uint32_t CHALTC; /**< Channel Alternate Clear Register */
- __IOM uint32_t CHPRIS; /**< Channel Priority Set Register */
- __OM uint32_t CHPRIC; /**< Channel Priority Clear Register */
- uint32_t RESERVED0[3]; /**< Reserved for future use **/
- __IOM uint32_t ERRORC; /**< Bus Error Clear Register */
+ __IM uint32_t STATUS; /**< DMA Status Registers */
+ __OM uint32_t CONFIG; /**< DMA Configuration Register */
+ __IOM uint32_t CTRLBASE; /**< Channel Control Data Base Pointer Register */
+ __IM uint32_t ALTCTRLBASE; /**< Channel Alternate Control Data Base Pointer Register */
+ __IM uint32_t CHWAITSTATUS; /**< Channel Wait on Request Status Register */
+ __OM uint32_t CHSWREQ; /**< Channel Software Request Register */
+ __IOM uint32_t CHUSEBURSTS; /**< Channel Useburst Set Register */
+ __OM uint32_t CHUSEBURSTC; /**< Channel Useburst Clear Register */
+ __IOM uint32_t CHREQMASKS; /**< Channel Request Mask Set Register */
+ __OM uint32_t CHREQMASKC; /**< Channel Request Mask Clear Register */
+ __IOM uint32_t CHENS; /**< Channel Enable Set Register */
+ __OM uint32_t CHENC; /**< Channel Enable Clear Register */
+ __IOM uint32_t CHALTS; /**< Channel Alternate Set Register */
+ __OM uint32_t CHALTC; /**< Channel Alternate Clear Register */
+ __IOM uint32_t CHPRIS; /**< Channel Priority Set Register */
+ __OM uint32_t CHPRIC; /**< Channel Priority Clear Register */
+ uint32_t RESERVED0[3U]; /**< Reserved for future use **/
+ __IOM uint32_t ERRORC; /**< Bus Error Clear Register */
- uint32_t RESERVED1[880]; /**< Reserved for future use **/
- __IM uint32_t CHREQSTATUS; /**< Channel Request Status */
- uint32_t RESERVED2[1]; /**< Reserved for future use **/
- __IM uint32_t CHSREQSTATUS; /**< Channel Single Request Status */
+ uint32_t RESERVED1[880U]; /**< Reserved for future use **/
+ __IM uint32_t CHREQSTATUS; /**< Channel Request Status */
+ uint32_t RESERVED2[1U]; /**< Reserved for future use **/
+ __IM uint32_t CHSREQSTATUS; /**< Channel Single Request Status */
- uint32_t RESERVED3[121]; /**< Reserved for future use **/
- __IM uint32_t IF; /**< Interrupt Flag Register */
- __IOM uint32_t IFS; /**< Interrupt Flag Set Register */
- __IOM uint32_t IFC; /**< Interrupt Flag Clear Register */
- __IOM uint32_t IEN; /**< Interrupt Enable register */
+ uint32_t RESERVED3[121U]; /**< Reserved for future use **/
+ __IM uint32_t IF; /**< Interrupt Flag Register */
+ __IOM uint32_t IFS; /**< Interrupt Flag Set Register */
+ __IOM uint32_t IFC; /**< Interrupt Flag Clear Register */
+ __IOM uint32_t IEN; /**< Interrupt Enable register */
- uint32_t RESERVED4[60]; /**< Reserved registers */
- DMA_CH_TypeDef CH[4]; /**< Channel registers */
-} DMA_TypeDef; /** DMA Register Declaration *//** @} */
+ uint32_t RESERVED4[60U]; /**< Reserved registers */
+ DMA_CH_TypeDef CH[4U]; /**< Channel registers */
+} DMA_TypeDef; /** DMA Register Declaration *//** @} */
-/**************************************************************************//**
+/***************************************************************************//**
* @defgroup EFM32ZG_DMA_BitFields
* @{
- *****************************************************************************/
+ ******************************************************************************/
/* Bit fields for DMA STATUS */
#define _DMA_STATUS_RESETVALUE 0x10030000UL /**< Default value for DMA_STATUS */
diff --git a/cpu/efm32/families/efm32zg/include/vendor/efm32zg_dma_ch.h b/cpu/efm32/families/efm32zg/include/vendor/efm32zg_dma_ch.h
index 8562ff2191..b80e36ae31 100644
--- a/cpu/efm32/families/efm32zg/include/vendor/efm32zg_dma_ch.h
+++ b/cpu/efm32/families/efm32zg/include/vendor/efm32zg_dma_ch.h
@@ -1,34 +1,32 @@
-/**************************************************************************//**
- * @file efm32zg_dma_ch.h
+/***************************************************************************//**
+ * @file
* @brief EFM32ZG_DMA_CH register and bit field definitions
- * @version 5.4.0
- ******************************************************************************
+ *******************************************************************************
* # License
- * Copyright 2017 Silicon Laboratories, Inc. www.silabs.com
- ******************************************************************************
+ * Copyright 2020 Silicon Laboratories Inc. www.silabs.com
+ *******************************************************************************
+ *
+ * SPDX-License-Identifier: Zlib
+ *
+ * The licensor of this software is Silicon Laboratories Inc.
+ *
+ * This software is provided 'as-is', without any express or implied
+ * warranty. In no event will the authors be held liable for any damages
+ * arising from the use of this software.
*
* Permission is granted to anyone to use this software for any purpose,
* including commercial applications, and to alter it and redistribute it
* freely, subject to the following restrictions:
*
* 1. The origin of this software must not be misrepresented; you must not
- * claim that you wrote the original software.@n
+ * claim that you wrote the original software. If you use this software
+ * in a product, an acknowledgment in the product documentation would be
+ * appreciated but is not required.
* 2. Altered source versions must be plainly marked as such, and must not be
- * misrepresented as being the original software.@n
+ * misrepresented as being the original software.
* 3. This notice may not be removed or altered from any source distribution.
*
- * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
- * has no obligation to support this Software. Silicon Laboratories, Inc. is
- * providing the Software "AS IS", with no express or implied warranties of any
- * kind, including, but not limited to, any implied warranties of
- * merchantability or fitness for any particular purpose or warranties against
- * infringement of any proprietary rights of a third party.
- *
- * Silicon Laboratories, Inc. will not be liable for any consequential,
- * incidental, or special damages, or any other relief, or for any claim by
- * any third party, arising from your use of this Software.
- *
- *****************************************************************************/
+ ******************************************************************************/
#ifdef __cplusplus
extern "C" {
@@ -41,13 +39,13 @@ extern "C" {
#pragma clang system_header /* Treat file as system include file. */
#endif
-/**************************************************************************//**
-* @addtogroup Parts
-* @{
-******************************************************************************/
-/**************************************************************************//**
+/***************************************************************************//**
+ * @addtogroup Parts
+ * @{
+ ******************************************************************************/
+/***************************************************************************//**
* @brief DMA_CH EFM32ZG DMA CH
- *****************************************************************************/
+ ******************************************************************************/
typedef struct {
__IOM uint32_t CTRL; /**< Channel Control Register */
} DMA_CH_TypeDef;
diff --git a/cpu/efm32/families/efm32zg/include/vendor/efm32zg_dma_descriptor.h b/cpu/efm32/families/efm32zg/include/vendor/efm32zg_dma_descriptor.h
index 8cc78e6a18..4541d7bd52 100644
--- a/cpu/efm32/families/efm32zg/include/vendor/efm32zg_dma_descriptor.h
+++ b/cpu/efm32/families/efm32zg/include/vendor/efm32zg_dma_descriptor.h
@@ -1,34 +1,32 @@
-/**************************************************************************//**
- * @file efm32zg_dma_descriptor.h
+/***************************************************************************//**
+ * @file
* @brief EFM32ZG_DMA_DESCRIPTOR register and bit field definitions
- * @version 5.4.0
- ******************************************************************************
+ *******************************************************************************
* # License
- * Copyright 2017 Silicon Laboratories, Inc. www.silabs.com
- ******************************************************************************
+ * Copyright 2020 Silicon Laboratories Inc. www.silabs.com
+ *******************************************************************************
+ *
+ * SPDX-License-Identifier: Zlib
+ *
+ * The licensor of this software is Silicon Laboratories Inc.
+ *
+ * This software is provided 'as-is', without any express or implied
+ * warranty. In no event will the authors be held liable for any damages
+ * arising from the use of this software.
*
* Permission is granted to anyone to use this software for any purpose,
* including commercial applications, and to alter it and redistribute it
* freely, subject to the following restrictions:
*
* 1. The origin of this software must not be misrepresented; you must not
- * claim that you wrote the original software.@n
+ * claim that you wrote the original software. If you use this software
+ * in a product, an acknowledgment in the product documentation would be
+ * appreciated but is not required.
* 2. Altered source versions must be plainly marked as such, and must not be
- * misrepresented as being the original software.@n
+ * misrepresented as being the original software.
* 3. This notice may not be removed or altered from any source distribution.
*
- * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
- * has no obligation to support this Software. Silicon Laboratories, Inc. is
- * providing the Software "AS IS", with no express or implied warranties of any
- * kind, including, but not limited to, any implied warranties of
- * merchantability or fitness for any particular purpose or warranties against
- * infringement of any proprietary rights of a third party.
- *
- * Silicon Laboratories, Inc. will not be liable for any consequential,
- * incidental, or special damages, or any other relief, or for any claim by
- * any third party, arising from your use of this Software.
- *
- *****************************************************************************/
+ ******************************************************************************/
#ifdef __cplusplus
extern "C" {
@@ -41,14 +39,14 @@ extern "C" {
#pragma clang system_header /* Treat file as system include file. */
#endif
-/**************************************************************************//**
-* @addtogroup Parts
-* @{
-******************************************************************************/
-/**************************************************************************//**
+/***************************************************************************//**
+ * @addtogroup Parts
+ * @{
+ ******************************************************************************/
+/***************************************************************************//**
* @defgroup EFM32ZG_DMA_DESCRIPTOR
* @{
- *****************************************************************************/
+ ******************************************************************************/
typedef struct {
/* Note! Use of double __IOM (volatile) qualifier to ensure that both */
/* pointer and referenced memory are declared volatile. */
diff --git a/cpu/efm32/families/efm32zg/include/vendor/efm32zg_dmactrl.h b/cpu/efm32/families/efm32zg/include/vendor/efm32zg_dmactrl.h
index 897a0ed874..b3e2da8a18 100644
--- a/cpu/efm32/families/efm32zg/include/vendor/efm32zg_dmactrl.h
+++ b/cpu/efm32/families/efm32zg/include/vendor/efm32zg_dmactrl.h
@@ -1,34 +1,32 @@
-/**************************************************************************//**
- * @file efm32zg_dmactrl.h
+/***************************************************************************//**
+ * @file
* @brief EFM32ZG_DMACTRL register and bit field definitions
- * @version 5.4.0
- ******************************************************************************
+ *******************************************************************************
* # License
- * Copyright 2017 Silicon Laboratories, Inc. www.silabs.com
- ******************************************************************************
+ * Copyright 2020 Silicon Laboratories Inc. www.silabs.com
+ *******************************************************************************
+ *
+ * SPDX-License-Identifier: Zlib
+ *
+ * The licensor of this software is Silicon Laboratories Inc.
+ *
+ * This software is provided 'as-is', without any express or implied
+ * warranty. In no event will the authors be held liable for any damages
+ * arising from the use of this software.
*
* Permission is granted to anyone to use this software for any purpose,
* including commercial applications, and to alter it and redistribute it
* freely, subject to the following restrictions:
*
* 1. The origin of this software must not be misrepresented; you must not
- * claim that you wrote the original software.@n
+ * claim that you wrote the original software. If you use this software
+ * in a product, an acknowledgment in the product documentation would be
+ * appreciated but is not required.
* 2. Altered source versions must be plainly marked as such, and must not be
- * misrepresented as being the original software.@n
+ * misrepresented as being the original software.
* 3. This notice may not be removed or altered from any source distribution.
*
- * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
- * has no obligation to support this Software. Silicon Laboratories, Inc. is
- * providing the Software "AS IS", with no express or implied warranties of any
- * kind, including, but not limited to, any implied warranties of
- * merchantability or fitness for any particular purpose or warranties against
- * infringement of any proprietary rights of a third party.
- *
- * Silicon Laboratories, Inc. will not be liable for any consequential,
- * incidental, or special damages, or any other relief, or for any claim by
- * any third party, arising from your use of this Software.
- *
- *****************************************************************************/
+ ******************************************************************************/
#ifdef __cplusplus
extern "C" {
@@ -41,15 +39,15 @@ extern "C" {
#pragma clang system_header /* Treat file as system include file. */
#endif
-/**************************************************************************//**
-* @addtogroup Parts
-* @{
-******************************************************************************/
+/***************************************************************************//**
+ * @addtogroup Parts
+ * @{
+ ******************************************************************************/
-/**************************************************************************//**
+/***************************************************************************//**
* @defgroup EFM32ZG_DMACTRL_BitFields
* @{
- *****************************************************************************/
+ ******************************************************************************/
#define _DMA_CTRL_DST_INC_MASK 0xC0000000UL /**< Data increment for destination, bit mask */
#define _DMA_CTRL_DST_INC_SHIFT 30 /**< Data increment for destination, shift value */
#define _DMA_CTRL_DST_INC_BYTE 0x00 /**< Byte/8-bit increment */
diff --git a/cpu/efm32/families/efm32zg/include/vendor/efm32zg_dmareq.h b/cpu/efm32/families/efm32zg/include/vendor/efm32zg_dmareq.h
index aaa3634414..428dce2fe0 100644
--- a/cpu/efm32/families/efm32zg/include/vendor/efm32zg_dmareq.h
+++ b/cpu/efm32/families/efm32zg/include/vendor/efm32zg_dmareq.h
@@ -1,34 +1,32 @@
-/**************************************************************************//**
- * @file efm32zg_dmareq.h
+/***************************************************************************//**
+ * @file
* @brief EFM32ZG_DMAREQ register and bit field definitions
- * @version 5.4.0
- ******************************************************************************
+ *******************************************************************************
* # License
- * Copyright 2017 Silicon Laboratories, Inc. www.silabs.com
- ******************************************************************************
+ * Copyright 2020 Silicon Laboratories Inc. www.silabs.com
+ *******************************************************************************
+ *
+ * SPDX-License-Identifier: Zlib
+ *
+ * The licensor of this software is Silicon Laboratories Inc.
+ *
+ * This software is provided 'as-is', without any express or implied
+ * warranty. In no event will the authors be held liable for any damages
+ * arising from the use of this software.
*
* Permission is granted to anyone to use this software for any purpose,
* including commercial applications, and to alter it and redistribute it
* freely, subject to the following restrictions:
*
* 1. The origin of this software must not be misrepresented; you must not
- * claim that you wrote the original software.@n
+ * claim that you wrote the original software. If you use this software
+ * in a product, an acknowledgment in the product documentation would be
+ * appreciated but is not required.
* 2. Altered source versions must be plainly marked as such, and must not be
- * misrepresented as being the original software.@n
+ * misrepresented as being the original software.
* 3. This notice may not be removed or altered from any source distribution.
*
- * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
- * has no obligation to support this Software. Silicon Laboratories, Inc. is
- * providing the Software "AS IS", with no express or implied warranties of any
- * kind, including, but not limited to, any implied warranties of
- * merchantability or fitness for any particular purpose or warranties against
- * infringement of any proprietary rights of a third party.
- *
- * Silicon Laboratories, Inc. will not be liable for any consequential,
- * incidental, or special damages, or any other relief, or for any claim by
- * any third party, arising from your use of this Software.
- *
- *****************************************************************************/
+ ******************************************************************************/
#ifdef __cplusplus
extern "C" {
@@ -41,15 +39,15 @@ extern "C" {
#pragma clang system_header /* Treat file as system include file. */
#endif
-/**************************************************************************//**
-* @addtogroup Parts
-* @{
-******************************************************************************/
+/***************************************************************************//**
+ * @addtogroup Parts
+ * @{
+ ******************************************************************************/
-/**************************************************************************//**
+/***************************************************************************//**
* @defgroup EFM32ZG_DMAREQ_BitFields
* @{
- *****************************************************************************/
+ ******************************************************************************/
#define DMAREQ_ADC0_SINGLE ((8 << 16) + 0) /**< DMA channel select for ADC0_SINGLE */
#define DMAREQ_ADC0_SCAN ((8 << 16) + 1) /**< DMA channel select for ADC0_SCAN */
#define DMAREQ_USART1_RXDATAV ((13 << 16) + 0) /**< DMA channel select for USART1_RXDATAV */
diff --git a/cpu/efm32/families/efm32zg/include/vendor/efm32zg_emu.h b/cpu/efm32/families/efm32zg/include/vendor/efm32zg_emu.h
index 645c4ac258..780f31af1c 100644
--- a/cpu/efm32/families/efm32zg/include/vendor/efm32zg_emu.h
+++ b/cpu/efm32/families/efm32zg/include/vendor/efm32zg_emu.h
@@ -1,34 +1,32 @@
-/**************************************************************************//**
- * @file efm32zg_emu.h
+/***************************************************************************//**
+ * @file
* @brief EFM32ZG_EMU register and bit field definitions
- * @version 5.4.0
- ******************************************************************************
+ *******************************************************************************
* # License
- * Copyright 2017 Silicon Laboratories, Inc. www.silabs.com
- ******************************************************************************
+ * Copyright 2020 Silicon Laboratories Inc. www.silabs.com
+ *******************************************************************************
+ *
+ * SPDX-License-Identifier: Zlib
+ *
+ * The licensor of this software is Silicon Laboratories Inc.
+ *
+ * This software is provided 'as-is', without any express or implied
+ * warranty. In no event will the authors be held liable for any damages
+ * arising from the use of this software.
*
* Permission is granted to anyone to use this software for any purpose,
* including commercial applications, and to alter it and redistribute it
* freely, subject to the following restrictions:
*
* 1. The origin of this software must not be misrepresented; you must not
- * claim that you wrote the original software.@n
+ * claim that you wrote the original software. If you use this software
+ * in a product, an acknowledgment in the product documentation would be
+ * appreciated but is not required.
* 2. Altered source versions must be plainly marked as such, and must not be
- * misrepresented as being the original software.@n
+ * misrepresented as being the original software.
* 3. This notice may not be removed or altered from any source distribution.
*
- * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
- * has no obligation to support this Software. Silicon Laboratories, Inc. is
- * providing the Software "AS IS", with no express or implied warranties of any
- * kind, including, but not limited to, any implied warranties of
- * merchantability or fitness for any particular purpose or warranties against
- * infringement of any proprietary rights of a third party.
- *
- * Silicon Laboratories, Inc. will not be liable for any consequential,
- * incidental, or special damages, or any other relief, or for any claim by
- * any third party, arising from your use of this Software.
- *
- *****************************************************************************/
+ ******************************************************************************/
#ifdef __cplusplus
extern "C" {
@@ -41,29 +39,29 @@ extern "C" {
#pragma clang system_header /* Treat file as system include file. */
#endif
-/**************************************************************************//**
-* @addtogroup Parts
-* @{
-******************************************************************************/
-/**************************************************************************//**
+/***************************************************************************//**
+ * @addtogroup Parts
+ * @{
+ ******************************************************************************/
+/***************************************************************************//**
* @defgroup EFM32ZG_EMU
* @{
* @brief EFM32ZG_EMU Register Declaration
- *****************************************************************************/
+ ******************************************************************************/
typedef struct {
- __IOM uint32_t CTRL; /**< Control Register */
+ __IOM uint32_t CTRL; /**< Control Register */
- uint32_t RESERVED0[1]; /**< Reserved for future use **/
- __IOM uint32_t LOCK; /**< Configuration Lock Register */
+ uint32_t RESERVED0[1U]; /**< Reserved for future use **/
+ __IOM uint32_t LOCK; /**< Configuration Lock Register */
- uint32_t RESERVED1[6]; /**< Reserved for future use **/
- __IOM uint32_t AUXCTRL; /**< Auxiliary Control Register */
-} EMU_TypeDef; /** EMU Register Declaration *//** @} */
+ uint32_t RESERVED1[6U]; /**< Reserved for future use **/
+ __IOM uint32_t AUXCTRL; /**< Auxiliary Control Register */
+} EMU_TypeDef; /** EMU Register Declaration *//** @} */
-/**************************************************************************//**
+/***************************************************************************//**
* @defgroup EFM32ZG_EMU_BitFields
* @{
- *****************************************************************************/
+ ******************************************************************************/
/* Bit fields for EMU CTRL */
#define _EMU_CTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_CTRL */
@@ -93,13 +91,13 @@ typedef struct {
#define _EMU_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for EMU_LOCKKEY */
#define _EMU_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for EMU_LOCKKEY */
#define _EMU_LOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_LOCK */
-#define _EMU_LOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for EMU_LOCK */
#define _EMU_LOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for EMU_LOCK */
+#define _EMU_LOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for EMU_LOCK */
#define _EMU_LOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for EMU_LOCK */
#define _EMU_LOCK_LOCKKEY_UNLOCK 0x0000ADE8UL /**< Mode UNLOCK for EMU_LOCK */
#define EMU_LOCK_LOCKKEY_DEFAULT (_EMU_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_LOCK */
-#define EMU_LOCK_LOCKKEY_LOCK (_EMU_LOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for EMU_LOCK */
#define EMU_LOCK_LOCKKEY_UNLOCKED (_EMU_LOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for EMU_LOCK */
+#define EMU_LOCK_LOCKKEY_LOCK (_EMU_LOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for EMU_LOCK */
#define EMU_LOCK_LOCKKEY_LOCKED (_EMU_LOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for EMU_LOCK */
#define EMU_LOCK_LOCKKEY_UNLOCK (_EMU_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for EMU_LOCK */
diff --git a/cpu/efm32/families/efm32zg/include/vendor/efm32zg_gpio.h b/cpu/efm32/families/efm32zg/include/vendor/efm32zg_gpio.h
index 49a2f254cc..e26f89cd39 100644
--- a/cpu/efm32/families/efm32zg/include/vendor/efm32zg_gpio.h
+++ b/cpu/efm32/families/efm32zg/include/vendor/efm32zg_gpio.h
@@ -1,34 +1,32 @@
-/**************************************************************************//**
- * @file efm32zg_gpio.h
+/***************************************************************************//**
+ * @file
* @brief EFM32ZG_GPIO register and bit field definitions
- * @version 5.4.0
- ******************************************************************************
+ *******************************************************************************
* # License
- * Copyright 2017 Silicon Laboratories, Inc. www.silabs.com
- ******************************************************************************
+ * Copyright 2020 Silicon Laboratories Inc. www.silabs.com
+ *******************************************************************************
+ *
+ * SPDX-License-Identifier: Zlib
+ *
+ * The licensor of this software is Silicon Laboratories Inc.
+ *
+ * This software is provided 'as-is', without any express or implied
+ * warranty. In no event will the authors be held liable for any damages
+ * arising from the use of this software.
*
* Permission is granted to anyone to use this software for any purpose,
* including commercial applications, and to alter it and redistribute it
* freely, subject to the following restrictions:
*
* 1. The origin of this software must not be misrepresented; you must not
- * claim that you wrote the original software.@n
+ * claim that you wrote the original software. If you use this software
+ * in a product, an acknowledgment in the product documentation would be
+ * appreciated but is not required.
* 2. Altered source versions must be plainly marked as such, and must not be
- * misrepresented as being the original software.@n
+ * misrepresented as being the original software.
* 3. This notice may not be removed or altered from any source distribution.
*
- * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
- * has no obligation to support this Software. Silicon Laboratories, Inc. is
- * providing the Software "AS IS", with no express or implied warranties of any
- * kind, including, but not limited to, any implied warranties of
- * merchantability or fitness for any particular purpose or warranties against
- * infringement of any proprietary rights of a third party.
- *
- * Silicon Laboratories, Inc. will not be liable for any consequential,
- * incidental, or special damages, or any other relief, or for any claim by
- * any third party, arising from your use of this Software.
- *
- *****************************************************************************/
+ ******************************************************************************/
#ifdef __cplusplus
extern "C" {
@@ -41,42 +39,42 @@ extern "C" {
#pragma clang system_header /* Treat file as system include file. */
#endif
-/**************************************************************************//**
-* @addtogroup Parts
-* @{
-******************************************************************************/
-/**************************************************************************//**
+/***************************************************************************//**
+ * @addtogroup Parts
+ * @{
+ ******************************************************************************/
+/***************************************************************************//**
* @defgroup EFM32ZG_GPIO
* @{
* @brief EFM32ZG_GPIO Register Declaration
- *****************************************************************************/
+ ******************************************************************************/
typedef struct {
- GPIO_P_TypeDef P[6]; /**< Port configuration bits */
+ GPIO_P_TypeDef P[6U]; /**< Port configuration bits */
- uint32_t RESERVED0[10]; /**< Reserved for future use **/
- __IOM uint32_t EXTIPSELL; /**< External Interrupt Port Select Low Register */
- __IOM uint32_t EXTIPSELH; /**< External Interrupt Port Select High Register */
- __IOM uint32_t EXTIRISE; /**< External Interrupt Rising Edge Trigger Register */
- __IOM uint32_t EXTIFALL; /**< External Interrupt Falling Edge Trigger Register */
- __IOM uint32_t IEN; /**< Interrupt Enable Register */
- __IM uint32_t IF; /**< Interrupt Flag Register */
- __IOM uint32_t IFS; /**< Interrupt Flag Set Register */
- __IOM uint32_t IFC; /**< Interrupt Flag Clear Register */
+ uint32_t RESERVED0[10U]; /**< Reserved for future use **/
+ __IOM uint32_t EXTIPSELL; /**< External Interrupt Port Select Low Register */
+ __IOM uint32_t EXTIPSELH; /**< External Interrupt Port Select High Register */
+ __IOM uint32_t EXTIRISE; /**< External Interrupt Rising Edge Trigger Register */
+ __IOM uint32_t EXTIFALL; /**< External Interrupt Falling Edge Trigger Register */
+ __IOM uint32_t IEN; /**< Interrupt Enable Register */
+ __IM uint32_t IF; /**< Interrupt Flag Register */
+ __IOM uint32_t IFS; /**< Interrupt Flag Set Register */
+ __IOM uint32_t IFC; /**< Interrupt Flag Clear Register */
- __IOM uint32_t ROUTE; /**< I/O Routing Register */
- __IOM uint32_t INSENSE; /**< Input Sense Register */
- __IOM uint32_t LOCK; /**< Configuration Lock Register */
- __IOM uint32_t CTRL; /**< GPIO Control Register */
- __IOM uint32_t CMD; /**< GPIO Command Register */
- __IOM uint32_t EM4WUEN; /**< EM4 Wake-up Enable Register */
- __IOM uint32_t EM4WUPOL; /**< EM4 Wake-up Polarity Register */
- __IM uint32_t EM4WUCAUSE; /**< EM4 Wake-up Cause Register */
-} GPIO_TypeDef; /** GPIO Register Declaration *//** @} */
+ __IOM uint32_t ROUTE; /**< I/O Routing Register */
+ __IOM uint32_t INSENSE; /**< Input Sense Register */
+ __IOM uint32_t LOCK; /**< Configuration Lock Register */
+ __IOM uint32_t CTRL; /**< GPIO Control Register */
+ __IOM uint32_t CMD; /**< GPIO Command Register */
+ __IOM uint32_t EM4WUEN; /**< EM4 Wake-up Enable Register */
+ __IOM uint32_t EM4WUPOL; /**< EM4 Wake-up Polarity Register */
+ __IM uint32_t EM4WUCAUSE; /**< EM4 Wake-up Cause Register */
+} GPIO_TypeDef; /** GPIO Register Declaration *//** @} */
-/**************************************************************************//**
+/***************************************************************************//**
* @defgroup EFM32ZG_GPIO_BitFields
* @{
- *****************************************************************************/
+ ******************************************************************************/
/* Bit fields for GPIO P_CTRL */
#define _GPIO_P_CTRL_RESETVALUE 0x00000000UL /**< Default value for GPIO_P_CTRL */
@@ -1072,13 +1070,13 @@ typedef struct {
#define _GPIO_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for GPIO_LOCKKEY */
#define _GPIO_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for GPIO_LOCKKEY */
#define _GPIO_LOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_LOCK */
-#define _GPIO_LOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for GPIO_LOCK */
#define _GPIO_LOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for GPIO_LOCK */
+#define _GPIO_LOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for GPIO_LOCK */
#define _GPIO_LOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for GPIO_LOCK */
#define _GPIO_LOCK_LOCKKEY_UNLOCK 0x0000A534UL /**< Mode UNLOCK for GPIO_LOCK */
#define GPIO_LOCK_LOCKKEY_DEFAULT (_GPIO_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_LOCK */
-#define GPIO_LOCK_LOCKKEY_LOCK (_GPIO_LOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for GPIO_LOCK */
#define GPIO_LOCK_LOCKKEY_UNLOCKED (_GPIO_LOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for GPIO_LOCK */
+#define GPIO_LOCK_LOCKKEY_LOCK (_GPIO_LOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for GPIO_LOCK */
#define GPIO_LOCK_LOCKKEY_LOCKED (_GPIO_LOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for GPIO_LOCK */
#define GPIO_LOCK_LOCKKEY_UNLOCK (_GPIO_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for GPIO_LOCK */
diff --git a/cpu/efm32/families/efm32zg/include/vendor/efm32zg_gpio_p.h b/cpu/efm32/families/efm32zg/include/vendor/efm32zg_gpio_p.h
index 27743ce6b6..0f259ce9a0 100644
--- a/cpu/efm32/families/efm32zg/include/vendor/efm32zg_gpio_p.h
+++ b/cpu/efm32/families/efm32zg/include/vendor/efm32zg_gpio_p.h
@@ -1,34 +1,32 @@
-/**************************************************************************//**
- * @file efm32zg_gpio_p.h
+/***************************************************************************//**
+ * @file
* @brief EFM32ZG_GPIO_P register and bit field definitions
- * @version 5.4.0
- ******************************************************************************
+ *******************************************************************************
* # License
- * Copyright 2017 Silicon Laboratories, Inc. www.silabs.com
- ******************************************************************************
+ * Copyright 2020 Silicon Laboratories Inc. www.silabs.com
+ *******************************************************************************
+ *
+ * SPDX-License-Identifier: Zlib
+ *
+ * The licensor of this software is Silicon Laboratories Inc.
+ *
+ * This software is provided 'as-is', without any express or implied
+ * warranty. In no event will the authors be held liable for any damages
+ * arising from the use of this software.
*
* Permission is granted to anyone to use this software for any purpose,
* including commercial applications, and to alter it and redistribute it
* freely, subject to the following restrictions:
*
* 1. The origin of this software must not be misrepresented; you must not
- * claim that you wrote the original software.@n
+ * claim that you wrote the original software. If you use this software
+ * in a product, an acknowledgment in the product documentation would be
+ * appreciated but is not required.
* 2. Altered source versions must be plainly marked as such, and must not be
- * misrepresented as being the original software.@n
+ * misrepresented as being the original software.
* 3. This notice may not be removed or altered from any source distribution.
*
- * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
- * has no obligation to support this Software. Silicon Laboratories, Inc. is
- * providing the Software "AS IS", with no express or implied warranties of any
- * kind, including, but not limited to, any implied warranties of
- * merchantability or fitness for any particular purpose or warranties against
- * infringement of any proprietary rights of a third party.
- *
- * Silicon Laboratories, Inc. will not be liable for any consequential,
- * incidental, or special damages, or any other relief, or for any claim by
- * any third party, arising from your use of this Software.
- *
- *****************************************************************************/
+ ******************************************************************************/
#ifdef __cplusplus
extern "C" {
@@ -41,13 +39,13 @@ extern "C" {
#pragma clang system_header /* Treat file as system include file. */
#endif
-/**************************************************************************//**
-* @addtogroup Parts
-* @{
-******************************************************************************/
-/**************************************************************************//**
+/***************************************************************************//**
+ * @addtogroup Parts
+ * @{
+ ******************************************************************************/
+/***************************************************************************//**
* @brief GPIO_P EFM32ZG GPIO P
- *****************************************************************************/
+ ******************************************************************************/
typedef struct {
__IOM uint32_t CTRL; /**< Port Control Register */
__IOM uint32_t MODEL; /**< Port Pin Mode Low Register */
diff --git a/cpu/efm32/families/efm32zg/include/vendor/efm32zg_i2c.h b/cpu/efm32/families/efm32zg/include/vendor/efm32zg_i2c.h
index eeb7beccc8..a964a5de87 100644
--- a/cpu/efm32/families/efm32zg/include/vendor/efm32zg_i2c.h
+++ b/cpu/efm32/families/efm32zg/include/vendor/efm32zg_i2c.h
@@ -1,34 +1,32 @@
-/**************************************************************************//**
- * @file efm32zg_i2c.h
+/***************************************************************************//**
+ * @file
* @brief EFM32ZG_I2C register and bit field definitions
- * @version 5.4.0
- ******************************************************************************
+ *******************************************************************************
* # License
- * Copyright 2017 Silicon Laboratories, Inc. www.silabs.com
- ******************************************************************************
+ * Copyright 2020 Silicon Laboratories Inc. www.silabs.com
+ *******************************************************************************
+ *
+ * SPDX-License-Identifier: Zlib
+ *
+ * The licensor of this software is Silicon Laboratories Inc.
+ *
+ * This software is provided 'as-is', without any express or implied
+ * warranty. In no event will the authors be held liable for any damages
+ * arising from the use of this software.
*
* Permission is granted to anyone to use this software for any purpose,
* including commercial applications, and to alter it and redistribute it
* freely, subject to the following restrictions:
*
* 1. The origin of this software must not be misrepresented; you must not
- * claim that you wrote the original software.@n
+ * claim that you wrote the original software. If you use this software
+ * in a product, an acknowledgment in the product documentation would be
+ * appreciated but is not required.
* 2. Altered source versions must be plainly marked as such, and must not be
- * misrepresented as being the original software.@n
+ * misrepresented as being the original software.
* 3. This notice may not be removed or altered from any source distribution.
*
- * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
- * has no obligation to support this Software. Silicon Laboratories, Inc. is
- * providing the Software "AS IS", with no express or implied warranties of any
- * kind, including, but not limited to, any implied warranties of
- * merchantability or fitness for any particular purpose or warranties against
- * infringement of any proprietary rights of a third party.
- *
- * Silicon Laboratories, Inc. will not be liable for any consequential,
- * incidental, or special damages, or any other relief, or for any claim by
- * any third party, arising from your use of this Software.
- *
- *****************************************************************************/
+ ******************************************************************************/
#ifdef __cplusplus
extern "C" {
@@ -41,15 +39,15 @@ extern "C" {
#pragma clang system_header /* Treat file as system include file. */
#endif
-/**************************************************************************//**
-* @addtogroup Parts
-* @{
-******************************************************************************/
-/**************************************************************************//**
+/***************************************************************************//**
+ * @addtogroup Parts
+ * @{
+ ******************************************************************************/
+/***************************************************************************//**
* @defgroup EFM32ZG_I2C
* @{
* @brief EFM32ZG_I2C Register Declaration
- *****************************************************************************/
+ ******************************************************************************/
typedef struct {
__IOM uint32_t CTRL; /**< Control Register */
__IOM uint32_t CMD; /**< Command Register */
@@ -68,10 +66,10 @@ typedef struct {
__IOM uint32_t ROUTE; /**< I/O Routing Register */
} I2C_TypeDef; /** I2C Register Declaration *//** @} */
-/**************************************************************************//**
+/***************************************************************************//**
* @defgroup EFM32ZG_I2C_BitFields
* @{
- *****************************************************************************/
+ ******************************************************************************/
/* Bit fields for I2C CTRL */
#define _I2C_CTRL_RESETVALUE 0x00000000UL /**< Default value for I2C_CTRL */
diff --git a/cpu/efm32/families/efm32zg/include/vendor/efm32zg_idac.h b/cpu/efm32/families/efm32zg/include/vendor/efm32zg_idac.h
index bbbdcf8826..179682bc52 100644
--- a/cpu/efm32/families/efm32zg/include/vendor/efm32zg_idac.h
+++ b/cpu/efm32/families/efm32zg/include/vendor/efm32zg_idac.h
@@ -1,34 +1,32 @@
-/**************************************************************************//**
- * @file efm32zg_idac.h
+/***************************************************************************//**
+ * @file
* @brief EFM32ZG_IDAC register and bit field definitions
- * @version 5.4.0
- ******************************************************************************
+ *******************************************************************************
* # License
- * Copyright 2017 Silicon Laboratories, Inc. www.silabs.com
- ******************************************************************************
+ * Copyright 2020 Silicon Laboratories Inc. www.silabs.com
+ *******************************************************************************
+ *
+ * SPDX-License-Identifier: Zlib
+ *
+ * The licensor of this software is Silicon Laboratories Inc.
+ *
+ * This software is provided 'as-is', without any express or implied
+ * warranty. In no event will the authors be held liable for any damages
+ * arising from the use of this software.
*
* Permission is granted to anyone to use this software for any purpose,
* including commercial applications, and to alter it and redistribute it
* freely, subject to the following restrictions:
*
* 1. The origin of this software must not be misrepresented; you must not
- * claim that you wrote the original software.@n
+ * claim that you wrote the original software. If you use this software
+ * in a product, an acknowledgment in the product documentation would be
+ * appreciated but is not required.
* 2. Altered source versions must be plainly marked as such, and must not be
- * misrepresented as being the original software.@n
+ * misrepresented as being the original software.
* 3. This notice may not be removed or altered from any source distribution.
*
- * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
- * has no obligation to support this Software. Silicon Laboratories, Inc. is
- * providing the Software "AS IS", with no express or implied warranties of any
- * kind, including, but not limited to, any implied warranties of
- * merchantability or fitness for any particular purpose or warranties against
- * infringement of any proprietary rights of a third party.
- *
- * Silicon Laboratories, Inc. will not be liable for any consequential,
- * incidental, or special damages, or any other relief, or for any claim by
- * any third party, arising from your use of this Software.
- *
- *****************************************************************************/
+ ******************************************************************************/
#ifdef __cplusplus
extern "C" {
@@ -41,15 +39,15 @@ extern "C" {
#pragma clang system_header /* Treat file as system include file. */
#endif
-/**************************************************************************//**
-* @addtogroup Parts
-* @{
-******************************************************************************/
-/**************************************************************************//**
+/***************************************************************************//**
+ * @addtogroup Parts
+ * @{
+ ******************************************************************************/
+/***************************************************************************//**
* @defgroup EFM32ZG_IDAC
* @{
* @brief EFM32ZG_IDAC Register Declaration
- *****************************************************************************/
+ ******************************************************************************/
typedef struct {
__IOM uint32_t CTRL; /**< Control Register */
__IOM uint32_t CURPROG; /**< Current Programming Register */
@@ -57,10 +55,10 @@ typedef struct {
__IOM uint32_t DUTYCONFIG; /**< Duty Cycle Configauration Register */
} IDAC_TypeDef; /** IDAC Register Declaration *//** @} */
-/**************************************************************************//**
+/***************************************************************************//**
* @defgroup EFM32ZG_IDAC_BitFields
* @{
- *****************************************************************************/
+ ******************************************************************************/
/* Bit fields for IDAC CTRL */
#define _IDAC_CTRL_RESETVALUE 0x00000000UL /**< Default value for IDAC_CTRL */
diff --git a/cpu/efm32/families/efm32zg/include/vendor/efm32zg_leuart.h b/cpu/efm32/families/efm32zg/include/vendor/efm32zg_leuart.h
index 91813b3b18..84df2f4922 100644
--- a/cpu/efm32/families/efm32zg/include/vendor/efm32zg_leuart.h
+++ b/cpu/efm32/families/efm32zg/include/vendor/efm32zg_leuart.h
@@ -1,34 +1,32 @@
-/**************************************************************************//**
- * @file efm32zg_leuart.h
+/***************************************************************************//**
+ * @file
* @brief EFM32ZG_LEUART register and bit field definitions
- * @version 5.4.0
- ******************************************************************************
+ *******************************************************************************
* # License
- * Copyright 2017 Silicon Laboratories, Inc. www.silabs.com
- ******************************************************************************
+ * Copyright 2020 Silicon Laboratories Inc. www.silabs.com
+ *******************************************************************************
+ *
+ * SPDX-License-Identifier: Zlib
+ *
+ * The licensor of this software is Silicon Laboratories Inc.
+ *
+ * This software is provided 'as-is', without any express or implied
+ * warranty. In no event will the authors be held liable for any damages
+ * arising from the use of this software.
*
* Permission is granted to anyone to use this software for any purpose,
* including commercial applications, and to alter it and redistribute it
* freely, subject to the following restrictions:
*
* 1. The origin of this software must not be misrepresented; you must not
- * claim that you wrote the original software.@n
+ * claim that you wrote the original software. If you use this software
+ * in a product, an acknowledgment in the product documentation would be
+ * appreciated but is not required.
* 2. Altered source versions must be plainly marked as such, and must not be
- * misrepresented as being the original software.@n
+ * misrepresented as being the original software.
* 3. This notice may not be removed or altered from any source distribution.
*
- * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
- * has no obligation to support this Software. Silicon Laboratories, Inc. is
- * providing the Software "AS IS", with no express or implied warranties of any
- * kind, including, but not limited to, any implied warranties of
- * merchantability or fitness for any particular purpose or warranties against
- * infringement of any proprietary rights of a third party.
- *
- * Silicon Laboratories, Inc. will not be liable for any consequential,
- * incidental, or special damages, or any other relief, or for any claim by
- * any third party, arising from your use of this Software.
- *
- *****************************************************************************/
+ ******************************************************************************/
#ifdef __cplusplus
extern "C" {
@@ -41,46 +39,46 @@ extern "C" {
#pragma clang system_header /* Treat file as system include file. */
#endif
-/**************************************************************************//**
-* @addtogroup Parts
-* @{
-******************************************************************************/
-/**************************************************************************//**
+/***************************************************************************//**
+ * @addtogroup Parts
+ * @{
+ ******************************************************************************/
+/***************************************************************************//**
* @defgroup EFM32ZG_LEUART
* @{
* @brief EFM32ZG_LEUART Register Declaration
- *****************************************************************************/
+ ******************************************************************************/
typedef struct {
- __IOM uint32_t CTRL; /**< Control Register */
- __IOM uint32_t CMD; /**< Command Register */
- __IM uint32_t STATUS; /**< Status Register */
- __IOM uint32_t CLKDIV; /**< Clock Control Register */
- __IOM uint32_t STARTFRAME; /**< Start Frame Register */
- __IOM uint32_t SIGFRAME; /**< Signal Frame Register */
- __IM uint32_t RXDATAX; /**< Receive Buffer Data Extended Register */
- __IM uint32_t RXDATA; /**< Receive Buffer Data Register */
- __IM uint32_t RXDATAXP; /**< Receive Buffer Data Extended Peek Register */
- __IOM uint32_t TXDATAX; /**< Transmit Buffer Data Extended Register */
- __IOM uint32_t TXDATA; /**< Transmit Buffer Data Register */
- __IM uint32_t IF; /**< Interrupt Flag Register */
- __IOM uint32_t IFS; /**< Interrupt Flag Set Register */
- __IOM uint32_t IFC; /**< Interrupt Flag Clear Register */
- __IOM uint32_t IEN; /**< Interrupt Enable Register */
- __IOM uint32_t PULSECTRL; /**< Pulse Control Register */
+ __IOM uint32_t CTRL; /**< Control Register */
+ __IOM uint32_t CMD; /**< Command Register */
+ __IM uint32_t STATUS; /**< Status Register */
+ __IOM uint32_t CLKDIV; /**< Clock Control Register */
+ __IOM uint32_t STARTFRAME; /**< Start Frame Register */
+ __IOM uint32_t SIGFRAME; /**< Signal Frame Register */
+ __IM uint32_t RXDATAX; /**< Receive Buffer Data Extended Register */
+ __IM uint32_t RXDATA; /**< Receive Buffer Data Register */
+ __IM uint32_t RXDATAXP; /**< Receive Buffer Data Extended Peek Register */
+ __IOM uint32_t TXDATAX; /**< Transmit Buffer Data Extended Register */
+ __IOM uint32_t TXDATA; /**< Transmit Buffer Data Register */
+ __IM uint32_t IF; /**< Interrupt Flag Register */
+ __IOM uint32_t IFS; /**< Interrupt Flag Set Register */
+ __IOM uint32_t IFC; /**< Interrupt Flag Clear Register */
+ __IOM uint32_t IEN; /**< Interrupt Enable Register */
+ __IOM uint32_t PULSECTRL; /**< Pulse Control Register */
- __IOM uint32_t FREEZE; /**< Freeze Register */
- __IM uint32_t SYNCBUSY; /**< Synchronization Busy Register */
+ __IOM uint32_t FREEZE; /**< Freeze Register */
+ __IM uint32_t SYNCBUSY; /**< Synchronization Busy Register */
- uint32_t RESERVED0[3]; /**< Reserved for future use **/
- __IOM uint32_t ROUTE; /**< I/O Routing Register */
- uint32_t RESERVED1[21]; /**< Reserved for future use **/
- __IOM uint32_t INPUT; /**< LEUART Input Register */
-} LEUART_TypeDef; /** LEUART Register Declaration *//** @} */
+ uint32_t RESERVED0[3U]; /**< Reserved for future use **/
+ __IOM uint32_t ROUTE; /**< I/O Routing Register */
+ uint32_t RESERVED1[21U]; /**< Reserved for future use **/
+ __IOM uint32_t INPUT; /**< LEUART Input Register */
+} LEUART_TypeDef; /** LEUART Register Declaration *//** @} */
-/**************************************************************************//**
+/***************************************************************************//**
* @defgroup EFM32ZG_LEUART_BitFields
* @{
- *****************************************************************************/
+ ******************************************************************************/
/* Bit fields for LEUART CTRL */
#define _LEUART_CTRL_RESETVALUE 0x00000000UL /**< Default value for LEUART_CTRL */
diff --git a/cpu/efm32/families/efm32zg/include/vendor/efm32zg_msc.h b/cpu/efm32/families/efm32zg/include/vendor/efm32zg_msc.h
index 040954dffb..7ed4b1907d 100644
--- a/cpu/efm32/families/efm32zg/include/vendor/efm32zg_msc.h
+++ b/cpu/efm32/families/efm32zg/include/vendor/efm32zg_msc.h
@@ -1,34 +1,32 @@
-/**************************************************************************//**
- * @file efm32zg_msc.h
+/***************************************************************************//**
+ * @file
* @brief EFM32ZG_MSC register and bit field definitions
- * @version 5.4.0
- ******************************************************************************
+ *******************************************************************************
* # License
- * Copyright 2017 Silicon Laboratories, Inc. www.silabs.com
- ******************************************************************************
+ * Copyright 2020 Silicon Laboratories Inc. www.silabs.com
+ *******************************************************************************
+ *
+ * SPDX-License-Identifier: Zlib
+ *
+ * The licensor of this software is Silicon Laboratories Inc.
+ *
+ * This software is provided 'as-is', without any express or implied
+ * warranty. In no event will the authors be held liable for any damages
+ * arising from the use of this software.
*
* Permission is granted to anyone to use this software for any purpose,
* including commercial applications, and to alter it and redistribute it
* freely, subject to the following restrictions:
*
* 1. The origin of this software must not be misrepresented; you must not
- * claim that you wrote the original software.@n
+ * claim that you wrote the original software. If you use this software
+ * in a product, an acknowledgment in the product documentation would be
+ * appreciated but is not required.
* 2. Altered source versions must be plainly marked as such, and must not be
- * misrepresented as being the original software.@n
+ * misrepresented as being the original software.
* 3. This notice may not be removed or altered from any source distribution.
*
- * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
- * has no obligation to support this Software. Silicon Laboratories, Inc. is
- * providing the Software "AS IS", with no express or implied warranties of any
- * kind, including, but not limited to, any implied warranties of
- * merchantability or fitness for any particular purpose or warranties against
- * infringement of any proprietary rights of a third party.
- *
- * Silicon Laboratories, Inc. will not be liable for any consequential,
- * incidental, or special damages, or any other relief, or for any claim by
- * any third party, arising from your use of this Software.
- *
- *****************************************************************************/
+ ******************************************************************************/
#ifdef __cplusplus
extern "C" {
@@ -41,45 +39,45 @@ extern "C" {
#pragma clang system_header /* Treat file as system include file. */
#endif
-/**************************************************************************//**
-* @addtogroup Parts
-* @{
-******************************************************************************/
-/**************************************************************************//**
+/***************************************************************************//**
+ * @addtogroup Parts
+ * @{
+ ******************************************************************************/
+/***************************************************************************//**
* @defgroup EFM32ZG_MSC
* @{
* @brief EFM32ZG_MSC Register Declaration
- *****************************************************************************/
+ ******************************************************************************/
typedef struct {
- __IOM uint32_t CTRL; /**< Memory System Control Register */
- __IOM uint32_t READCTRL; /**< Read Control Register */
- __IOM uint32_t WRITECTRL; /**< Write Control Register */
- __IOM uint32_t WRITECMD; /**< Write Command Register */
- __IOM uint32_t ADDRB; /**< Page Erase/Write Address Buffer */
+ __IOM uint32_t CTRL; /**< Memory System Control Register */
+ __IOM uint32_t READCTRL; /**< Read Control Register */
+ __IOM uint32_t WRITECTRL; /**< Write Control Register */
+ __IOM uint32_t WRITECMD; /**< Write Command Register */
+ __IOM uint32_t ADDRB; /**< Page Erase/Write Address Buffer */
- uint32_t RESERVED0[1]; /**< Reserved for future use **/
- __IOM uint32_t WDATA; /**< Write Data Register */
- __IM uint32_t STATUS; /**< Status Register */
+ uint32_t RESERVED0[1U]; /**< Reserved for future use **/
+ __IOM uint32_t WDATA; /**< Write Data Register */
+ __IM uint32_t STATUS; /**< Status Register */
- uint32_t RESERVED1[3]; /**< Reserved for future use **/
- __IM uint32_t IF; /**< Interrupt Flag Register */
- __IOM uint32_t IFS; /**< Interrupt Flag Set Register */
- __IOM uint32_t IFC; /**< Interrupt Flag Clear Register */
- __IOM uint32_t IEN; /**< Interrupt Enable Register */
- __IOM uint32_t LOCK; /**< Configuration Lock Register */
- __IOM uint32_t CMD; /**< Command Register */
- __IM uint32_t CACHEHITS; /**< Cache Hits Performance Counter */
- __IM uint32_t CACHEMISSES; /**< Cache Misses Performance Counter */
- uint32_t RESERVED2[1]; /**< Reserved for future use **/
- __IOM uint32_t TIMEBASE; /**< Flash Write and Erase Timebase */
- __IOM uint32_t MASSLOCK; /**< Mass Erase Lock Register */
- __IOM uint32_t IRQLATENCY; /**< Irq Latency Register */
-} MSC_TypeDef; /** MSC Register Declaration *//** @} */
+ uint32_t RESERVED1[3U]; /**< Reserved for future use **/
+ __IM uint32_t IF; /**< Interrupt Flag Register */
+ __IOM uint32_t IFS; /**< Interrupt Flag Set Register */
+ __IOM uint32_t IFC; /**< Interrupt Flag Clear Register */
+ __IOM uint32_t IEN; /**< Interrupt Enable Register */
+ __IOM uint32_t LOCK; /**< Configuration Lock Register */
+ __IOM uint32_t CMD; /**< Command Register */
+ __IM uint32_t CACHEHITS; /**< Cache Hits Performance Counter */
+ __IM uint32_t CACHEMISSES; /**< Cache Misses Performance Counter */
+ uint32_t RESERVED2[1U]; /**< Reserved for future use **/
+ __IOM uint32_t TIMEBASE; /**< Flash Write and Erase Timebase */
+ __IOM uint32_t MASSLOCK; /**< Mass Erase Lock Register */
+ __IOM uint32_t IRQLATENCY; /**< Irq Latency Register */
+} MSC_TypeDef; /** MSC Register Declaration *//** @} */
-/**************************************************************************//**
+/***************************************************************************//**
* @defgroup EFM32ZG_MSC_BitFields
* @{
- *****************************************************************************/
+ ******************************************************************************/
/* Bit fields for MSC CTRL */
#define _MSC_CTRL_RESETVALUE 0x00000001UL /**< Default value for MSC_CTRL */
@@ -336,13 +334,13 @@ typedef struct {
#define _MSC_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for MSC_LOCKKEY */
#define _MSC_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for MSC_LOCKKEY */
#define _MSC_LOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_LOCK */
-#define _MSC_LOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for MSC_LOCK */
#define _MSC_LOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for MSC_LOCK */
+#define _MSC_LOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for MSC_LOCK */
#define _MSC_LOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for MSC_LOCK */
#define _MSC_LOCK_LOCKKEY_UNLOCK 0x00001B71UL /**< Mode UNLOCK for MSC_LOCK */
#define MSC_LOCK_LOCKKEY_DEFAULT (_MSC_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_LOCK */
-#define MSC_LOCK_LOCKKEY_LOCK (_MSC_LOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for MSC_LOCK */
#define MSC_LOCK_LOCKKEY_UNLOCKED (_MSC_LOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for MSC_LOCK */
+#define MSC_LOCK_LOCKKEY_LOCK (_MSC_LOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for MSC_LOCK */
#define MSC_LOCK_LOCKKEY_LOCKED (_MSC_LOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for MSC_LOCK */
#define MSC_LOCK_LOCKKEY_UNLOCK (_MSC_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for MSC_LOCK */
@@ -403,13 +401,13 @@ typedef struct {
#define _MSC_MASSLOCK_MASK 0x0000FFFFUL /**< Mask for MSC_MASSLOCK */
#define _MSC_MASSLOCK_LOCKKEY_SHIFT 0 /**< Shift value for MSC_LOCKKEY */
#define _MSC_MASSLOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for MSC_LOCKKEY */
-#define _MSC_MASSLOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for MSC_MASSLOCK */
#define _MSC_MASSLOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for MSC_MASSLOCK */
+#define _MSC_MASSLOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for MSC_MASSLOCK */
#define _MSC_MASSLOCK_LOCKKEY_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_MASSLOCK */
#define _MSC_MASSLOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for MSC_MASSLOCK */
#define _MSC_MASSLOCK_LOCKKEY_UNLOCK 0x0000631AUL /**< Mode UNLOCK for MSC_MASSLOCK */
-#define MSC_MASSLOCK_LOCKKEY_LOCK (_MSC_MASSLOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for MSC_MASSLOCK */
#define MSC_MASSLOCK_LOCKKEY_UNLOCKED (_MSC_MASSLOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for MSC_MASSLOCK */
+#define MSC_MASSLOCK_LOCKKEY_LOCK (_MSC_MASSLOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for MSC_MASSLOCK */
#define MSC_MASSLOCK_LOCKKEY_DEFAULT (_MSC_MASSLOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_MASSLOCK */
#define MSC_MASSLOCK_LOCKKEY_LOCKED (_MSC_MASSLOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for MSC_MASSLOCK */
#define MSC_MASSLOCK_LOCKKEY_UNLOCK (_MSC_MASSLOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for MSC_MASSLOCK */
diff --git a/cpu/efm32/families/efm32zg/include/vendor/efm32zg_pcnt.h b/cpu/efm32/families/efm32zg/include/vendor/efm32zg_pcnt.h
index cc897a7261..658e9e3bfc 100644
--- a/cpu/efm32/families/efm32zg/include/vendor/efm32zg_pcnt.h
+++ b/cpu/efm32/families/efm32zg/include/vendor/efm32zg_pcnt.h
@@ -1,34 +1,32 @@
-/**************************************************************************//**
- * @file efm32zg_pcnt.h
+/***************************************************************************//**
+ * @file
* @brief EFM32ZG_PCNT register and bit field definitions
- * @version 5.4.0
- ******************************************************************************
+ *******************************************************************************
* # License
- * Copyright 2017 Silicon Laboratories, Inc. www.silabs.com
- ******************************************************************************
+ * Copyright 2020 Silicon Laboratories Inc. www.silabs.com
+ *******************************************************************************
+ *
+ * SPDX-License-Identifier: Zlib
+ *
+ * The licensor of this software is Silicon Laboratories Inc.
+ *
+ * This software is provided 'as-is', without any express or implied
+ * warranty. In no event will the authors be held liable for any damages
+ * arising from the use of this software.
*
* Permission is granted to anyone to use this software for any purpose,
* including commercial applications, and to alter it and redistribute it
* freely, subject to the following restrictions:
*
* 1. The origin of this software must not be misrepresented; you must not
- * claim that you wrote the original software.@n
+ * claim that you wrote the original software. If you use this software
+ * in a product, an acknowledgment in the product documentation would be
+ * appreciated but is not required.
* 2. Altered source versions must be plainly marked as such, and must not be
- * misrepresented as being the original software.@n
+ * misrepresented as being the original software.
* 3. This notice may not be removed or altered from any source distribution.
*
- * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
- * has no obligation to support this Software. Silicon Laboratories, Inc. is
- * providing the Software "AS IS", with no express or implied warranties of any
- * kind, including, but not limited to, any implied warranties of
- * merchantability or fitness for any particular purpose or warranties against
- * infringement of any proprietary rights of a third party.
- *
- * Silicon Laboratories, Inc. will not be liable for any consequential,
- * incidental, or special damages, or any other relief, or for any claim by
- * any third party, arising from your use of this Software.
- *
- *****************************************************************************/
+ ******************************************************************************/
#ifdef __cplusplus
extern "C" {
@@ -41,40 +39,40 @@ extern "C" {
#pragma clang system_header /* Treat file as system include file. */
#endif
-/**************************************************************************//**
-* @addtogroup Parts
-* @{
-******************************************************************************/
-/**************************************************************************//**
+/***************************************************************************//**
+ * @addtogroup Parts
+ * @{
+ ******************************************************************************/
+/***************************************************************************//**
* @defgroup EFM32ZG_PCNT
* @{
* @brief EFM32ZG_PCNT Register Declaration
- *****************************************************************************/
+ ******************************************************************************/
typedef struct {
- __IOM uint32_t CTRL; /**< Control Register */
- __IOM uint32_t CMD; /**< Command Register */
- __IM uint32_t STATUS; /**< Status Register */
- __IM uint32_t CNT; /**< Counter Value Register */
- __IM uint32_t TOP; /**< Top Value Register */
- __IOM uint32_t TOPB; /**< Top Value Buffer Register */
- __IM uint32_t IF; /**< Interrupt Flag Register */
- __IOM uint32_t IFS; /**< Interrupt Flag Set Register */
- __IOM uint32_t IFC; /**< Interrupt Flag Clear Register */
- __IOM uint32_t IEN; /**< Interrupt Enable Register */
- __IOM uint32_t ROUTE; /**< I/O Routing Register */
+ __IOM uint32_t CTRL; /**< Control Register */
+ __IOM uint32_t CMD; /**< Command Register */
+ __IM uint32_t STATUS; /**< Status Register */
+ __IM uint32_t CNT; /**< Counter Value Register */
+ __IM uint32_t TOP; /**< Top Value Register */
+ __IOM uint32_t TOPB; /**< Top Value Buffer Register */
+ __IM uint32_t IF; /**< Interrupt Flag Register */
+ __IOM uint32_t IFS; /**< Interrupt Flag Set Register */
+ __IOM uint32_t IFC; /**< Interrupt Flag Clear Register */
+ __IOM uint32_t IEN; /**< Interrupt Enable Register */
+ __IOM uint32_t ROUTE; /**< I/O Routing Register */
- __IOM uint32_t FREEZE; /**< Freeze Register */
- __IM uint32_t SYNCBUSY; /**< Synchronization Busy Register */
+ __IOM uint32_t FREEZE; /**< Freeze Register */
+ __IM uint32_t SYNCBUSY; /**< Synchronization Busy Register */
- uint32_t RESERVED0[1]; /**< Reserved for future use **/
- __IOM uint32_t AUXCNT; /**< Auxiliary Counter Value Register */
- __IOM uint32_t INPUT; /**< PCNT Input Register */
-} PCNT_TypeDef; /** PCNT Register Declaration *//** @} */
+ uint32_t RESERVED0[1U]; /**< Reserved for future use **/
+ __IOM uint32_t AUXCNT; /**< Auxiliary Counter Value Register */
+ __IOM uint32_t INPUT; /**< PCNT Input Register */
+} PCNT_TypeDef; /** PCNT Register Declaration *//** @} */
-/**************************************************************************//**
+/***************************************************************************//**
* @defgroup EFM32ZG_PCNT_BitFields
* @{
- *****************************************************************************/
+ ******************************************************************************/
/* Bit fields for PCNT CTRL */
#define _PCNT_CTRL_RESETVALUE 0x00000000UL /**< Default value for PCNT_CTRL */
diff --git a/cpu/efm32/families/efm32zg/include/vendor/efm32zg_prs.h b/cpu/efm32/families/efm32zg/include/vendor/efm32zg_prs.h
index 0af20135e6..a05bd5fb72 100644
--- a/cpu/efm32/families/efm32zg/include/vendor/efm32zg_prs.h
+++ b/cpu/efm32/families/efm32zg/include/vendor/efm32zg_prs.h
@@ -1,34 +1,32 @@
-/**************************************************************************//**
- * @file efm32zg_prs.h
+/***************************************************************************//**
+ * @file
* @brief EFM32ZG_PRS register and bit field definitions
- * @version 5.4.0
- ******************************************************************************
+ *******************************************************************************
* # License
- * Copyright 2017 Silicon Laboratories, Inc. www.silabs.com
- ******************************************************************************
+ * Copyright 2020 Silicon Laboratories Inc. www.silabs.com
+ *******************************************************************************
+ *
+ * SPDX-License-Identifier: Zlib
+ *
+ * The licensor of this software is Silicon Laboratories Inc.
+ *
+ * This software is provided 'as-is', without any express or implied
+ * warranty. In no event will the authors be held liable for any damages
+ * arising from the use of this software.
*
* Permission is granted to anyone to use this software for any purpose,
* including commercial applications, and to alter it and redistribute it
* freely, subject to the following restrictions:
*
* 1. The origin of this software must not be misrepresented; you must not
- * claim that you wrote the original software.@n
+ * claim that you wrote the original software. If you use this software
+ * in a product, an acknowledgment in the product documentation would be
+ * appreciated but is not required.
* 2. Altered source versions must be plainly marked as such, and must not be
- * misrepresented as being the original software.@n
+ * misrepresented as being the original software.
* 3. This notice may not be removed or altered from any source distribution.
*
- * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
- * has no obligation to support this Software. Silicon Laboratories, Inc. is
- * providing the Software "AS IS", with no express or implied warranties of any
- * kind, including, but not limited to, any implied warranties of
- * merchantability or fitness for any particular purpose or warranties against
- * infringement of any proprietary rights of a third party.
- *
- * Silicon Laboratories, Inc. will not be liable for any consequential,
- * incidental, or special damages, or any other relief, or for any claim by
- * any third party, arising from your use of this Software.
- *
- *****************************************************************************/
+ ******************************************************************************/
#ifdef __cplusplus
extern "C" {
@@ -41,28 +39,28 @@ extern "C" {
#pragma clang system_header /* Treat file as system include file. */
#endif
-/**************************************************************************//**
-* @addtogroup Parts
-* @{
-******************************************************************************/
-/**************************************************************************//**
+/***************************************************************************//**
+ * @addtogroup Parts
+ * @{
+ ******************************************************************************/
+/***************************************************************************//**
* @defgroup EFM32ZG_PRS
* @{
* @brief EFM32ZG_PRS Register Declaration
- *****************************************************************************/
+ ******************************************************************************/
typedef struct {
- __IOM uint32_t SWPULSE; /**< Software Pulse Register */
- __IOM uint32_t SWLEVEL; /**< Software Level Register */
- __IOM uint32_t ROUTE; /**< I/O Routing Register */
+ __IOM uint32_t SWPULSE; /**< Software Pulse Register */
+ __IOM uint32_t SWLEVEL; /**< Software Level Register */
+ __IOM uint32_t ROUTE; /**< I/O Routing Register */
- uint32_t RESERVED0[1]; /**< Reserved registers */
- PRS_CH_TypeDef CH[4]; /**< Channel registers */
-} PRS_TypeDef; /** PRS Register Declaration *//** @} */
+ uint32_t RESERVED0[1U]; /**< Reserved registers */
+ PRS_CH_TypeDef CH[4U]; /**< Channel registers */
+} PRS_TypeDef; /** PRS Register Declaration *//** @} */
-/**************************************************************************//**
+/***************************************************************************//**
* @defgroup EFM32ZG_PRS_BitFields
* @{
- *****************************************************************************/
+ ******************************************************************************/
/* Bit fields for PRS SWPULSE */
#define _PRS_SWPULSE_RESETVALUE 0x00000000UL /**< Default value for PRS_SWPULSE */
diff --git a/cpu/efm32/families/efm32zg/include/vendor/efm32zg_prs_ch.h b/cpu/efm32/families/efm32zg/include/vendor/efm32zg_prs_ch.h
index 8100a071b6..67c29300da 100644
--- a/cpu/efm32/families/efm32zg/include/vendor/efm32zg_prs_ch.h
+++ b/cpu/efm32/families/efm32zg/include/vendor/efm32zg_prs_ch.h
@@ -1,34 +1,32 @@
-/**************************************************************************//**
- * @file efm32zg_prs_ch.h
+/***************************************************************************//**
+ * @file
* @brief EFM32ZG_PRS_CH register and bit field definitions
- * @version 5.4.0
- ******************************************************************************
+ *******************************************************************************
* # License
- * Copyright 2017 Silicon Laboratories, Inc. www.silabs.com
- ******************************************************************************
+ * Copyright 2020 Silicon Laboratories Inc. www.silabs.com
+ *******************************************************************************
+ *
+ * SPDX-License-Identifier: Zlib
+ *
+ * The licensor of this software is Silicon Laboratories Inc.
+ *
+ * This software is provided 'as-is', without any express or implied
+ * warranty. In no event will the authors be held liable for any damages
+ * arising from the use of this software.
*
* Permission is granted to anyone to use this software for any purpose,
* including commercial applications, and to alter it and redistribute it
* freely, subject to the following restrictions:
*
* 1. The origin of this software must not be misrepresented; you must not
- * claim that you wrote the original software.@n
+ * claim that you wrote the original software. If you use this software
+ * in a product, an acknowledgment in the product documentation would be
+ * appreciated but is not required.
* 2. Altered source versions must be plainly marked as such, and must not be
- * misrepresented as being the original software.@n
+ * misrepresented as being the original software.
* 3. This notice may not be removed or altered from any source distribution.
*
- * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
- * has no obligation to support this Software. Silicon Laboratories, Inc. is
- * providing the Software "AS IS", with no express or implied warranties of any
- * kind, including, but not limited to, any implied warranties of
- * merchantability or fitness for any particular purpose or warranties against
- * infringement of any proprietary rights of a third party.
- *
- * Silicon Laboratories, Inc. will not be liable for any consequential,
- * incidental, or special damages, or any other relief, or for any claim by
- * any third party, arising from your use of this Software.
- *
- *****************************************************************************/
+ ******************************************************************************/
#ifdef __cplusplus
extern "C" {
@@ -41,13 +39,13 @@ extern "C" {
#pragma clang system_header /* Treat file as system include file. */
#endif
-/**************************************************************************//**
-* @addtogroup Parts
-* @{
-******************************************************************************/
-/**************************************************************************//**
+/***************************************************************************//**
+ * @addtogroup Parts
+ * @{
+ ******************************************************************************/
+/***************************************************************************//**
* @brief PRS_CH EFM32ZG PRS CH
- *****************************************************************************/
+ ******************************************************************************/
typedef struct {
__IOM uint32_t CTRL; /**< Channel Control Register */
} PRS_CH_TypeDef;
diff --git a/cpu/efm32/families/efm32zg/include/vendor/efm32zg_prs_signals.h b/cpu/efm32/families/efm32zg/include/vendor/efm32zg_prs_signals.h
index 4fffeddb1d..bfdeb26de8 100644
--- a/cpu/efm32/families/efm32zg/include/vendor/efm32zg_prs_signals.h
+++ b/cpu/efm32/families/efm32zg/include/vendor/efm32zg_prs_signals.h
@@ -1,34 +1,32 @@
-/**************************************************************************//**
- * @file efm32zg_prs_signals.h
+/***************************************************************************//**
+ * @file
* @brief EFM32ZG_PRS_SIGNALS register and bit field definitions
- * @version 5.4.0
- ******************************************************************************
+ *******************************************************************************
* # License
- * Copyright 2017 Silicon Laboratories, Inc. www.silabs.com
- ******************************************************************************
+ * Copyright 2020 Silicon Laboratories Inc. www.silabs.com
+ *******************************************************************************
+ *
+ * SPDX-License-Identifier: Zlib
+ *
+ * The licensor of this software is Silicon Laboratories Inc.
+ *
+ * This software is provided 'as-is', without any express or implied
+ * warranty. In no event will the authors be held liable for any damages
+ * arising from the use of this software.
*
* Permission is granted to anyone to use this software for any purpose,
* including commercial applications, and to alter it and redistribute it
* freely, subject to the following restrictions:
*
* 1. The origin of this software must not be misrepresented; you must not
- * claim that you wrote the original software.@n
+ * claim that you wrote the original software. If you use this software
+ * in a product, an acknowledgment in the product documentation would be
+ * appreciated but is not required.
* 2. Altered source versions must be plainly marked as such, and must not be
- * misrepresented as being the original software.@n
+ * misrepresented as being the original software.
* 3. This notice may not be removed or altered from any source distribution.
*
- * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
- * has no obligation to support this Software. Silicon Laboratories, Inc. is
- * providing the Software "AS IS", with no express or implied warranties of any
- * kind, including, but not limited to, any implied warranties of
- * merchantability or fitness for any particular purpose or warranties against
- * infringement of any proprietary rights of a third party.
- *
- * Silicon Laboratories, Inc. will not be liable for any consequential,
- * incidental, or special damages, or any other relief, or for any claim by
- * any third party, arising from your use of this Software.
- *
- *****************************************************************************/
+ ******************************************************************************/
#ifdef __cplusplus
extern "C" {
@@ -41,15 +39,15 @@ extern "C" {
#pragma clang system_header /* Treat file as system include file. */
#endif
-/**************************************************************************//**
-* @addtogroup Parts
-* @{
-******************************************************************************/
-/**************************************************************************//**
+/***************************************************************************//**
+ * @addtogroup Parts
+ * @{
+ ******************************************************************************/
+/***************************************************************************//**
* @addtogroup EFM32ZG_PRS_Signals
* @{
* @brief PRS Signal names
- *****************************************************************************/
+ ******************************************************************************/
#define PRS_VCMP_OUT ((1 << 16) + 0) /**< PRS Voltage comparator output */
#define PRS_ACMP0_OUT ((2 << 16) + 0) /**< PRS Analog comparator output */
#define PRS_ADC0_SINGLE ((8 << 16) + 0) /**< PRS ADC single conversion done */
diff --git a/cpu/efm32/families/efm32zg/include/vendor/efm32zg_rmu.h b/cpu/efm32/families/efm32zg/include/vendor/efm32zg_rmu.h
index 0a620b7be2..78d315d18a 100644
--- a/cpu/efm32/families/efm32zg/include/vendor/efm32zg_rmu.h
+++ b/cpu/efm32/families/efm32zg/include/vendor/efm32zg_rmu.h
@@ -1,34 +1,32 @@
-/**************************************************************************//**
- * @file efm32zg_rmu.h
+/***************************************************************************//**
+ * @file
* @brief EFM32ZG_RMU register and bit field definitions
- * @version 5.4.0
- ******************************************************************************
+ *******************************************************************************
* # License
- * Copyright 2017 Silicon Laboratories, Inc. www.silabs.com
- ******************************************************************************
+ * Copyright 2020 Silicon Laboratories Inc. www.silabs.com
+ *******************************************************************************
+ *
+ * SPDX-License-Identifier: Zlib
+ *
+ * The licensor of this software is Silicon Laboratories Inc.
+ *
+ * This software is provided 'as-is', without any express or implied
+ * warranty. In no event will the authors be held liable for any damages
+ * arising from the use of this software.
*
* Permission is granted to anyone to use this software for any purpose,
* including commercial applications, and to alter it and redistribute it
* freely, subject to the following restrictions:
*
* 1. The origin of this software must not be misrepresented; you must not
- * claim that you wrote the original software.@n
+ * claim that you wrote the original software. If you use this software
+ * in a product, an acknowledgment in the product documentation would be
+ * appreciated but is not required.
* 2. Altered source versions must be plainly marked as such, and must not be
- * misrepresented as being the original software.@n
+ * misrepresented as being the original software.
* 3. This notice may not be removed or altered from any source distribution.
*
- * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
- * has no obligation to support this Software. Silicon Laboratories, Inc. is
- * providing the Software "AS IS", with no express or implied warranties of any
- * kind, including, but not limited to, any implied warranties of
- * merchantability or fitness for any particular purpose or warranties against
- * infringement of any proprietary rights of a third party.
- *
- * Silicon Laboratories, Inc. will not be liable for any consequential,
- * incidental, or special damages, or any other relief, or for any claim by
- * any third party, arising from your use of this Software.
- *
- *****************************************************************************/
+ ******************************************************************************/
#ifdef __cplusplus
extern "C" {
@@ -41,25 +39,25 @@ extern "C" {
#pragma clang system_header /* Treat file as system include file. */
#endif
-/**************************************************************************//**
-* @addtogroup Parts
-* @{
-******************************************************************************/
-/**************************************************************************//**
+/***************************************************************************//**
+ * @addtogroup Parts
+ * @{
+ ******************************************************************************/
+/***************************************************************************//**
* @defgroup EFM32ZG_RMU
* @{
* @brief EFM32ZG_RMU Register Declaration
- *****************************************************************************/
+ ******************************************************************************/
typedef struct {
__IOM uint32_t CTRL; /**< Control Register */
__IM uint32_t RSTCAUSE; /**< Reset Cause Register */
__OM uint32_t CMD; /**< Command Register */
} RMU_TypeDef; /** RMU Register Declaration *//** @} */
-/**************************************************************************//**
+/***************************************************************************//**
* @defgroup EFM32ZG_RMU_BitFields
* @{
- *****************************************************************************/
+ ******************************************************************************/
/* Bit fields for RMU CTRL */
#define _RMU_CTRL_RESETVALUE 0x00000000UL /**< Default value for RMU_CTRL */
diff --git a/cpu/efm32/families/efm32zg/include/vendor/efm32zg_romtable.h b/cpu/efm32/families/efm32zg/include/vendor/efm32zg_romtable.h
index c9de517a7a..6fe9a19719 100644
--- a/cpu/efm32/families/efm32zg/include/vendor/efm32zg_romtable.h
+++ b/cpu/efm32/families/efm32zg/include/vendor/efm32zg_romtable.h
@@ -1,34 +1,32 @@
-/**************************************************************************//**
- * @file efm32zg_romtable.h
+/***************************************************************************//**
+ * @file
* @brief EFM32ZG_ROMTABLE register and bit field definitions
- * @version 5.4.0
- ******************************************************************************
+ *******************************************************************************
* # License
- * Copyright 2017 Silicon Laboratories, Inc. www.silabs.com
- ******************************************************************************
+ * Copyright 2020 Silicon Laboratories Inc. www.silabs.com
+ *******************************************************************************
+ *
+ * SPDX-License-Identifier: Zlib
+ *
+ * The licensor of this software is Silicon Laboratories Inc.
+ *
+ * This software is provided 'as-is', without any express or implied
+ * warranty. In no event will the authors be held liable for any damages
+ * arising from the use of this software.
*
* Permission is granted to anyone to use this software for any purpose,
* including commercial applications, and to alter it and redistribute it
* freely, subject to the following restrictions:
*
* 1. The origin of this software must not be misrepresented; you must not
- * claim that you wrote the original software.@n
+ * claim that you wrote the original software. If you use this software
+ * in a product, an acknowledgment in the product documentation would be
+ * appreciated but is not required.
* 2. Altered source versions must be plainly marked as such, and must not be
- * misrepresented as being the original software.@n
+ * misrepresented as being the original software.
* 3. This notice may not be removed or altered from any source distribution.
*
- * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
- * has no obligation to support this Software. Silicon Laboratories, Inc. is
- * providing the Software "AS IS", with no express or implied warranties of any
- * kind, including, but not limited to, any implied warranties of
- * merchantability or fitness for any particular purpose or warranties against
- * infringement of any proprietary rights of a third party.
- *
- * Silicon Laboratories, Inc. will not be liable for any consequential,
- * incidental, or special damages, or any other relief, or for any claim by
- * any third party, arising from your use of this Software.
- *
- *****************************************************************************/
+ ******************************************************************************/
#ifdef __cplusplus
extern "C" {
@@ -41,15 +39,15 @@ extern "C" {
#pragma clang system_header /* Treat file as system include file. */
#endif
-/**************************************************************************//**
-* @addtogroup Parts
-* @{
-******************************************************************************/
-/**************************************************************************//**
+/***************************************************************************//**
+ * @addtogroup Parts
+ * @{
+ ******************************************************************************/
+/***************************************************************************//**
* @defgroup EFM32ZG_ROMTABLE
* @{
* @brief Chip Information, Revision numbers
- *****************************************************************************/
+ ******************************************************************************/
typedef struct {
__IM uint32_t PID4; /**< JEP_106_BANK */
__IM uint32_t PID5; /**< Unused */
@@ -62,10 +60,10 @@ typedef struct {
__IM uint32_t CID0; /**< Unused */
} ROMTABLE_TypeDef; /** @} */
-/**************************************************************************//**
+/***************************************************************************//**
* @defgroup EFM32ZG_ROMTABLE_BitFields
* @{
- *****************************************************************************/
+ ******************************************************************************/
/* Bit fields for EFM32ZG_ROMTABLE */
#define _ROMTABLE_PID0_FAMILYLSB_MASK 0x000000C0UL /**< Least Significant Bits [1:0] of CHIP FAMILY, mask */
#define _ROMTABLE_PID0_FAMILYLSB_SHIFT 6 /**< Least Significant Bits [1:0] of CHIP FAMILY, shift */
diff --git a/cpu/efm32/families/efm32zg/include/vendor/efm32zg_rtc.h b/cpu/efm32/families/efm32zg/include/vendor/efm32zg_rtc.h
index 12c8616876..8de86467df 100644
--- a/cpu/efm32/families/efm32zg/include/vendor/efm32zg_rtc.h
+++ b/cpu/efm32/families/efm32zg/include/vendor/efm32zg_rtc.h
@@ -1,34 +1,32 @@
-/**************************************************************************//**
- * @file efm32zg_rtc.h
+/***************************************************************************//**
+ * @file
* @brief EFM32ZG_RTC register and bit field definitions
- * @version 5.4.0
- ******************************************************************************
+ *******************************************************************************
* # License
- * Copyright 2017 Silicon Laboratories, Inc. www.silabs.com
- ******************************************************************************
+ * Copyright 2020 Silicon Laboratories Inc. www.silabs.com
+ *******************************************************************************
+ *
+ * SPDX-License-Identifier: Zlib
+ *
+ * The licensor of this software is Silicon Laboratories Inc.
+ *
+ * This software is provided 'as-is', without any express or implied
+ * warranty. In no event will the authors be held liable for any damages
+ * arising from the use of this software.
*
* Permission is granted to anyone to use this software for any purpose,
* including commercial applications, and to alter it and redistribute it
* freely, subject to the following restrictions:
*
* 1. The origin of this software must not be misrepresented; you must not
- * claim that you wrote the original software.@n
+ * claim that you wrote the original software. If you use this software
+ * in a product, an acknowledgment in the product documentation would be
+ * appreciated but is not required.
* 2. Altered source versions must be plainly marked as such, and must not be
- * misrepresented as being the original software.@n
+ * misrepresented as being the original software.
* 3. This notice may not be removed or altered from any source distribution.
*
- * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
- * has no obligation to support this Software. Silicon Laboratories, Inc. is
- * providing the Software "AS IS", with no express or implied warranties of any
- * kind, including, but not limited to, any implied warranties of
- * merchantability or fitness for any particular purpose or warranties against
- * infringement of any proprietary rights of a third party.
- *
- * Silicon Laboratories, Inc. will not be liable for any consequential,
- * incidental, or special damages, or any other relief, or for any claim by
- * any third party, arising from your use of this Software.
- *
- *****************************************************************************/
+ ******************************************************************************/
#ifdef __cplusplus
extern "C" {
@@ -41,15 +39,15 @@ extern "C" {
#pragma clang system_header /* Treat file as system include file. */
#endif
-/**************************************************************************//**
-* @addtogroup Parts
-* @{
-******************************************************************************/
-/**************************************************************************//**
+/***************************************************************************//**
+ * @addtogroup Parts
+ * @{
+ ******************************************************************************/
+/***************************************************************************//**
* @defgroup EFM32ZG_RTC
* @{
* @brief EFM32ZG_RTC Register Declaration
- *****************************************************************************/
+ ******************************************************************************/
typedef struct {
__IOM uint32_t CTRL; /**< Control Register */
__IOM uint32_t CNT; /**< Counter Value Register */
@@ -64,10 +62,10 @@ typedef struct {
__IM uint32_t SYNCBUSY; /**< Synchronization Busy Register */
} RTC_TypeDef; /** RTC Register Declaration *//** @} */
-/**************************************************************************//**
+/***************************************************************************//**
* @defgroup EFM32ZG_RTC_BitFields
* @{
- *****************************************************************************/
+ ******************************************************************************/
/* Bit fields for RTC CTRL */
#define _RTC_CTRL_RESETVALUE 0x00000000UL /**< Default value for RTC_CTRL */
diff --git a/cpu/efm32/families/efm32zg/include/vendor/efm32zg_timer.h b/cpu/efm32/families/efm32zg/include/vendor/efm32zg_timer.h
index 80740134fd..69d01832ae 100644
--- a/cpu/efm32/families/efm32zg/include/vendor/efm32zg_timer.h
+++ b/cpu/efm32/families/efm32zg/include/vendor/efm32zg_timer.h
@@ -1,34 +1,32 @@
-/**************************************************************************//**
- * @file efm32zg_timer.h
+/***************************************************************************//**
+ * @file
* @brief EFM32ZG_TIMER register and bit field definitions
- * @version 5.4.0
- ******************************************************************************
+ *******************************************************************************
* # License
- * Copyright 2017 Silicon Laboratories, Inc. www.silabs.com
- ******************************************************************************
+ * Copyright 2020 Silicon Laboratories Inc. www.silabs.com
+ *******************************************************************************
+ *
+ * SPDX-License-Identifier: Zlib
+ *
+ * The licensor of this software is Silicon Laboratories Inc.
+ *
+ * This software is provided 'as-is', without any express or implied
+ * warranty. In no event will the authors be held liable for any damages
+ * arising from the use of this software.
*
* Permission is granted to anyone to use this software for any purpose,
* including commercial applications, and to alter it and redistribute it
* freely, subject to the following restrictions:
*
* 1. The origin of this software must not be misrepresented; you must not
- * claim that you wrote the original software.@n
+ * claim that you wrote the original software. If you use this software
+ * in a product, an acknowledgment in the product documentation would be
+ * appreciated but is not required.
* 2. Altered source versions must be plainly marked as such, and must not be
- * misrepresented as being the original software.@n
+ * misrepresented as being the original software.
* 3. This notice may not be removed or altered from any source distribution.
*
- * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
- * has no obligation to support this Software. Silicon Laboratories, Inc. is
- * providing the Software "AS IS", with no express or implied warranties of any
- * kind, including, but not limited to, any implied warranties of
- * merchantability or fitness for any particular purpose or warranties against
- * infringement of any proprietary rights of a third party.
- *
- * Silicon Laboratories, Inc. will not be liable for any consequential,
- * incidental, or special damages, or any other relief, or for any claim by
- * any third party, arising from your use of this Software.
- *
- *****************************************************************************/
+ ******************************************************************************/
#ifdef __cplusplus
extern "C" {
@@ -41,36 +39,36 @@ extern "C" {
#pragma clang system_header /* Treat file as system include file. */
#endif
-/**************************************************************************//**
-* @addtogroup Parts
-* @{
-******************************************************************************/
-/**************************************************************************//**
+/***************************************************************************//**
+ * @addtogroup Parts
+ * @{
+ ******************************************************************************/
+/***************************************************************************//**
* @defgroup EFM32ZG_TIMER
* @{
* @brief EFM32ZG_TIMER Register Declaration
- *****************************************************************************/
+ ******************************************************************************/
typedef struct {
- __IOM uint32_t CTRL; /**< Control Register */
- __IOM uint32_t CMD; /**< Command Register */
- __IM uint32_t STATUS; /**< Status Register */
- __IOM uint32_t IEN; /**< Interrupt Enable Register */
- __IM uint32_t IF; /**< Interrupt Flag Register */
- __IOM uint32_t IFS; /**< Interrupt Flag Set Register */
- __IOM uint32_t IFC; /**< Interrupt Flag Clear Register */
- __IOM uint32_t TOP; /**< Counter Top Value Register */
- __IOM uint32_t TOPB; /**< Counter Top Value Buffer Register */
- __IOM uint32_t CNT; /**< Counter Value Register */
- __IOM uint32_t ROUTE; /**< I/O Routing Register */
+ __IOM uint32_t CTRL; /**< Control Register */
+ __IOM uint32_t CMD; /**< Command Register */
+ __IM uint32_t STATUS; /**< Status Register */
+ __IOM uint32_t IEN; /**< Interrupt Enable Register */
+ __IM uint32_t IF; /**< Interrupt Flag Register */
+ __IOM uint32_t IFS; /**< Interrupt Flag Set Register */
+ __IOM uint32_t IFC; /**< Interrupt Flag Clear Register */
+ __IOM uint32_t TOP; /**< Counter Top Value Register */
+ __IOM uint32_t TOPB; /**< Counter Top Value Buffer Register */
+ __IOM uint32_t CNT; /**< Counter Value Register */
+ __IOM uint32_t ROUTE; /**< I/O Routing Register */
- uint32_t RESERVED0[1]; /**< Reserved registers */
- TIMER_CC_TypeDef CC[3]; /**< Compare/Capture Channel */
-} TIMER_TypeDef; /** TIMER Register Declaration *//** @} */
+ uint32_t RESERVED0[1U]; /**< Reserved registers */
+ TIMER_CC_TypeDef CC[3U]; /**< Compare/Capture Channel */
+} TIMER_TypeDef; /** TIMER Register Declaration *//** @} */
-/**************************************************************************//**
+/***************************************************************************//**
* @defgroup EFM32ZG_TIMER_BitFields
* @{
- *****************************************************************************/
+ ******************************************************************************/
/* Bit fields for TIMER CTRL */
#define _TIMER_CTRL_RESETVALUE 0x00000000UL /**< Default value for TIMER_CTRL */
diff --git a/cpu/efm32/families/efm32zg/include/vendor/efm32zg_timer_cc.h b/cpu/efm32/families/efm32zg/include/vendor/efm32zg_timer_cc.h
index 81d1601794..c6353c7073 100644
--- a/cpu/efm32/families/efm32zg/include/vendor/efm32zg_timer_cc.h
+++ b/cpu/efm32/families/efm32zg/include/vendor/efm32zg_timer_cc.h
@@ -1,34 +1,32 @@
-/**************************************************************************//**
- * @file efm32zg_timer_cc.h
+/***************************************************************************//**
+ * @file
* @brief EFM32ZG_TIMER_CC register and bit field definitions
- * @version 5.4.0
- ******************************************************************************
+ *******************************************************************************
* # License
- * Copyright 2017 Silicon Laboratories, Inc. www.silabs.com
- ******************************************************************************
+ * Copyright 2020 Silicon Laboratories Inc. www.silabs.com
+ *******************************************************************************
+ *
+ * SPDX-License-Identifier: Zlib
+ *
+ * The licensor of this software is Silicon Laboratories Inc.
+ *
+ * This software is provided 'as-is', without any express or implied
+ * warranty. In no event will the authors be held liable for any damages
+ * arising from the use of this software.
*
* Permission is granted to anyone to use this software for any purpose,
* including commercial applications, and to alter it and redistribute it
* freely, subject to the following restrictions:
*
* 1. The origin of this software must not be misrepresented; you must not
- * claim that you wrote the original software.@n
+ * claim that you wrote the original software. If you use this software
+ * in a product, an acknowledgment in the product documentation would be
+ * appreciated but is not required.
* 2. Altered source versions must be plainly marked as such, and must not be
- * misrepresented as being the original software.@n
+ * misrepresented as being the original software.
* 3. This notice may not be removed or altered from any source distribution.
*
- * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
- * has no obligation to support this Software. Silicon Laboratories, Inc. is
- * providing the Software "AS IS", with no express or implied warranties of any
- * kind, including, but not limited to, any implied warranties of
- * merchantability or fitness for any particular purpose or warranties against
- * infringement of any proprietary rights of a third party.
- *
- * Silicon Laboratories, Inc. will not be liable for any consequential,
- * incidental, or special damages, or any other relief, or for any claim by
- * any third party, arising from your use of this Software.
- *
- *****************************************************************************/
+ ******************************************************************************/
#ifdef __cplusplus
extern "C" {
@@ -41,13 +39,13 @@ extern "C" {
#pragma clang system_header /* Treat file as system include file. */
#endif
-/**************************************************************************//**
-* @addtogroup Parts
-* @{
-******************************************************************************/
-/**************************************************************************//**
+/***************************************************************************//**
+ * @addtogroup Parts
+ * @{
+ ******************************************************************************/
+/***************************************************************************//**
* @brief TIMER_CC EFM32ZG TIMER CC
- *****************************************************************************/
+ ******************************************************************************/
typedef struct {
__IOM uint32_t CTRL; /**< CC Channel Control Register */
__IOM uint32_t CCV; /**< CC Channel Value Register */
diff --git a/cpu/efm32/families/efm32zg/include/vendor/efm32zg_usart.h b/cpu/efm32/families/efm32zg/include/vendor/efm32zg_usart.h
index 2b4691956e..a1ed0909a9 100644
--- a/cpu/efm32/families/efm32zg/include/vendor/efm32zg_usart.h
+++ b/cpu/efm32/families/efm32zg/include/vendor/efm32zg_usart.h
@@ -1,34 +1,32 @@
-/**************************************************************************//**
- * @file efm32zg_usart.h
+/***************************************************************************//**
+ * @file
* @brief EFM32ZG_USART register and bit field definitions
- * @version 5.4.0
- ******************************************************************************
+ *******************************************************************************
* # License
- * Copyright 2017 Silicon Laboratories, Inc. www.silabs.com
- ******************************************************************************
+ * Copyright 2020 Silicon Laboratories Inc. www.silabs.com
+ *******************************************************************************
+ *
+ * SPDX-License-Identifier: Zlib
+ *
+ * The licensor of this software is Silicon Laboratories Inc.
+ *
+ * This software is provided 'as-is', without any express or implied
+ * warranty. In no event will the authors be held liable for any damages
+ * arising from the use of this software.
*
* Permission is granted to anyone to use this software for any purpose,
* including commercial applications, and to alter it and redistribute it
* freely, subject to the following restrictions:
*
* 1. The origin of this software must not be misrepresented; you must not
- * claim that you wrote the original software.@n
+ * claim that you wrote the original software. If you use this software
+ * in a product, an acknowledgment in the product documentation would be
+ * appreciated but is not required.
* 2. Altered source versions must be plainly marked as such, and must not be
- * misrepresented as being the original software.@n
+ * misrepresented as being the original software.
* 3. This notice may not be removed or altered from any source distribution.
*
- * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
- * has no obligation to support this Software. Silicon Laboratories, Inc. is
- * providing the Software "AS IS", with no express or implied warranties of any
- * kind, including, but not limited to, any implied warranties of
- * merchantability or fitness for any particular purpose or warranties against
- * infringement of any proprietary rights of a third party.
- *
- * Silicon Laboratories, Inc. will not be liable for any consequential,
- * incidental, or special damages, or any other relief, or for any claim by
- * any third party, arising from your use of this Software.
- *
- *****************************************************************************/
+ ******************************************************************************/
#ifdef __cplusplus
extern "C" {
@@ -41,15 +39,15 @@ extern "C" {
#pragma clang system_header /* Treat file as system include file. */
#endif
-/**************************************************************************//**
-* @addtogroup Parts
-* @{
-******************************************************************************/
-/**************************************************************************//**
+/***************************************************************************//**
+ * @addtogroup Parts
+ * @{
+ ******************************************************************************/
+/***************************************************************************//**
* @defgroup EFM32ZG_USART
* @{
* @brief EFM32ZG_USART Register Declaration
- *****************************************************************************/
+ ******************************************************************************/
typedef struct {
__IOM uint32_t CTRL; /**< Control Register */
__IOM uint32_t FRAME; /**< USART Frame Format Register */
@@ -77,10 +75,10 @@ typedef struct {
__IOM uint32_t I2SCTRL; /**< I2S Control Register */
} USART_TypeDef; /** USART Register Declaration *//** @} */
-/**************************************************************************//**
+/***************************************************************************//**
* @defgroup EFM32ZG_USART_BitFields
* @{
- *****************************************************************************/
+ ******************************************************************************/
/* Bit fields for USART CTRL */
#define _USART_CTRL_RESETVALUE 0x00000000UL /**< Default value for USART_CTRL */
diff --git a/cpu/efm32/families/efm32zg/include/vendor/efm32zg_vcmp.h b/cpu/efm32/families/efm32zg/include/vendor/efm32zg_vcmp.h
index 78ea07a7b7..6788a221bc 100644
--- a/cpu/efm32/families/efm32zg/include/vendor/efm32zg_vcmp.h
+++ b/cpu/efm32/families/efm32zg/include/vendor/efm32zg_vcmp.h
@@ -1,34 +1,32 @@
-/**************************************************************************//**
- * @file efm32zg_vcmp.h
+/***************************************************************************//**
+ * @file
* @brief EFM32ZG_VCMP register and bit field definitions
- * @version 5.4.0
- ******************************************************************************
+ *******************************************************************************
* # License
- * Copyright 2017 Silicon Laboratories, Inc. www.silabs.com
- ******************************************************************************
+ * Copyright 2020 Silicon Laboratories Inc. www.silabs.com
+ *******************************************************************************
+ *
+ * SPDX-License-Identifier: Zlib
+ *
+ * The licensor of this software is Silicon Laboratories Inc.
+ *
+ * This software is provided 'as-is', without any express or implied
+ * warranty. In no event will the authors be held liable for any damages
+ * arising from the use of this software.
*
* Permission is granted to anyone to use this software for any purpose,
* including commercial applications, and to alter it and redistribute it
* freely, subject to the following restrictions:
*
* 1. The origin of this software must not be misrepresented; you must not
- * claim that you wrote the original software.@n
+ * claim that you wrote the original software. If you use this software
+ * in a product, an acknowledgment in the product documentation would be
+ * appreciated but is not required.
* 2. Altered source versions must be plainly marked as such, and must not be
- * misrepresented as being the original software.@n
+ * misrepresented as being the original software.
* 3. This notice may not be removed or altered from any source distribution.
*
- * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
- * has no obligation to support this Software. Silicon Laboratories, Inc. is
- * providing the Software "AS IS", with no express or implied warranties of any
- * kind, including, but not limited to, any implied warranties of
- * merchantability or fitness for any particular purpose or warranties against
- * infringement of any proprietary rights of a third party.
- *
- * Silicon Laboratories, Inc. will not be liable for any consequential,
- * incidental, or special damages, or any other relief, or for any claim by
- * any third party, arising from your use of this Software.
- *
- *****************************************************************************/
+ ******************************************************************************/
#ifdef __cplusplus
extern "C" {
@@ -41,15 +39,15 @@ extern "C" {
#pragma clang system_header /* Treat file as system include file. */
#endif
-/**************************************************************************//**
-* @addtogroup Parts
-* @{
-******************************************************************************/
-/**************************************************************************//**
+/***************************************************************************//**
+ * @addtogroup Parts
+ * @{
+ ******************************************************************************/
+/***************************************************************************//**
* @defgroup EFM32ZG_VCMP
* @{
* @brief EFM32ZG_VCMP Register Declaration
- *****************************************************************************/
+ ******************************************************************************/
typedef struct {
__IOM uint32_t CTRL; /**< Control Register */
__IOM uint32_t INPUTSEL; /**< Input Selection Register */
@@ -60,10 +58,10 @@ typedef struct {
__IOM uint32_t IFC; /**< Interrupt Flag Clear Register */
} VCMP_TypeDef; /** VCMP Register Declaration *//** @} */
-/**************************************************************************//**
+/***************************************************************************//**
* @defgroup EFM32ZG_VCMP_BitFields
* @{
- *****************************************************************************/
+ ******************************************************************************/
/* Bit fields for VCMP CTRL */
#define _VCMP_CTRL_RESETVALUE 0x47000000UL /**< Default value for VCMP_CTRL */
diff --git a/cpu/efm32/families/efm32zg/include/vendor/efm32zg_wdog.h b/cpu/efm32/families/efm32zg/include/vendor/efm32zg_wdog.h
index b6df1a572f..d125c06877 100644
--- a/cpu/efm32/families/efm32zg/include/vendor/efm32zg_wdog.h
+++ b/cpu/efm32/families/efm32zg/include/vendor/efm32zg_wdog.h
@@ -1,34 +1,32 @@
-/**************************************************************************//**
- * @file efm32zg_wdog.h
+/***************************************************************************//**
+ * @file
* @brief EFM32ZG_WDOG register and bit field definitions
- * @version 5.4.0
- ******************************************************************************
+ *******************************************************************************
* # License
- * Copyright 2017 Silicon Laboratories, Inc. www.silabs.com
- ******************************************************************************
+ * Copyright 2020 Silicon Laboratories Inc. www.silabs.com
+ *******************************************************************************
+ *
+ * SPDX-License-Identifier: Zlib
+ *
+ * The licensor of this software is Silicon Laboratories Inc.
+ *
+ * This software is provided 'as-is', without any express or implied
+ * warranty. In no event will the authors be held liable for any damages
+ * arising from the use of this software.
*
* Permission is granted to anyone to use this software for any purpose,
* including commercial applications, and to alter it and redistribute it
* freely, subject to the following restrictions:
*
* 1. The origin of this software must not be misrepresented; you must not
- * claim that you wrote the original software.@n
+ * claim that you wrote the original software. If you use this software
+ * in a product, an acknowledgment in the product documentation would be
+ * appreciated but is not required.
* 2. Altered source versions must be plainly marked as such, and must not be
- * misrepresented as being the original software.@n
+ * misrepresented as being the original software.
* 3. This notice may not be removed or altered from any source distribution.
*
- * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
- * has no obligation to support this Software. Silicon Laboratories, Inc. is
- * providing the Software "AS IS", with no express or implied warranties of any
- * kind, including, but not limited to, any implied warranties of
- * merchantability or fitness for any particular purpose or warranties against
- * infringement of any proprietary rights of a third party.
- *
- * Silicon Laboratories, Inc. will not be liable for any consequential,
- * incidental, or special damages, or any other relief, or for any claim by
- * any third party, arising from your use of this Software.
- *
- *****************************************************************************/
+ ******************************************************************************/
#ifdef __cplusplus
extern "C" {
@@ -41,15 +39,15 @@ extern "C" {
#pragma clang system_header /* Treat file as system include file. */
#endif
-/**************************************************************************//**
-* @addtogroup Parts
-* @{
-******************************************************************************/
-/**************************************************************************//**
+/***************************************************************************//**
+ * @addtogroup Parts
+ * @{
+ ******************************************************************************/
+/***************************************************************************//**
* @defgroup EFM32ZG_WDOG
* @{
* @brief EFM32ZG_WDOG Register Declaration
- *****************************************************************************/
+ ******************************************************************************/
typedef struct {
__IOM uint32_t CTRL; /**< Control Register */
__IOM uint32_t CMD; /**< Command Register */
@@ -57,10 +55,10 @@ typedef struct {
__IM uint32_t SYNCBUSY; /**< Synchronization Busy Register */
} WDOG_TypeDef; /** WDOG Register Declaration *//** @} */
-/**************************************************************************//**
+/***************************************************************************//**
* @defgroup EFM32ZG_WDOG_BitFields
* @{
- *****************************************************************************/
+ ******************************************************************************/
/* Bit fields for WDOG CTRL */
#define _WDOG_CTRL_RESETVALUE 0x00000F00UL /**< Default value for WDOG_CTRL */
diff --git a/cpu/efm32/families/efm32zg/include/vendor/em_device.h b/cpu/efm32/families/efm32zg/include/vendor/em_device.h
index d60d6fce01..09812262ed 100644
--- a/cpu/efm32/families/efm32zg/include/vendor/em_device.h
+++ b/cpu/efm32/families/efm32zg/include/vendor/em_device.h
@@ -1,5 +1,5 @@
-/**************************************************************************//**
- * @file em_device.h
+/***************************************************************************//**
+ * @file
* @brief CMSIS Cortex-M Peripheral Access Layer for Silicon Laboratories
* microcontroller devices
*
@@ -9,37 +9,34 @@
* @verbatim
* Example: Add "-DEFM32G890F128" to your build options, to define part
* Add "#include "em_device.h" to your source files
-
- *
* @endverbatim
- * @version 5.4.0
- ******************************************************************************
+ *
+ *******************************************************************************
* # License
- * Copyright 2017 Silicon Laboratories, Inc. www.silabs.com
- ******************************************************************************
+ * Copyright 2020 Silicon Laboratories Inc. www.silabs.com
+ *******************************************************************************
+ *
+ * SPDX-License-Identifier: Zlib
+ *
+ * The licensor of this software is Silicon Laboratories Inc.
+ *
+ * This software is provided 'as-is', without any express or implied
+ * warranty. In no event will the authors be held liable for any damages
+ * arising from the use of this software.
*
* Permission is granted to anyone to use this software for any purpose,
* including commercial applications, and to alter it and redistribute it
* freely, subject to the following restrictions:
*
* 1. The origin of this software must not be misrepresented; you must not
- * claim that you wrote the original software.@n
+ * claim that you wrote the original software. If you use this software
+ * in a product, an acknowledgment in the product documentation would be
+ * appreciated but is not required.
* 2. Altered source versions must be plainly marked as such, and must not be
- * misrepresented as being the original software.@n
+ * misrepresented as being the original software.
* 3. This notice may not be removed or altered from any source distribution.
*
- * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
- * has no obligation to support this Software. Silicon Laboratories, Inc. is
- * providing the Software "AS IS", with no express or implied warranties of any
- * kind, including, but not limited to, any implied warranties of
- * merchantability or fitness for any particular purpose or warranties against
- * infringement of any proprietary rights of a third party.
- *
- * Silicon Laboratories, Inc. will not be liable for any consequential,
- * incidental, or special damages, or any other relief, or for any claim by
- * any third party, arising from your use of this Software.
- *
- *****************************************************************************/
+ ******************************************************************************/
#ifdef __cplusplus
extern "C" {
diff --git a/cpu/efm32/families/efm32zg/include/vendor/system_efm32zg.h b/cpu/efm32/families/efm32zg/include/vendor/system_efm32zg.h
index 67019b2ad8..3762ba2a83 100644
--- a/cpu/efm32/families/efm32zg/include/vendor/system_efm32zg.h
+++ b/cpu/efm32/families/efm32zg/include/vendor/system_efm32zg.h
@@ -1,34 +1,32 @@
-/**************************************************************************//**
- * @file system_efm32zg.h
+/***************************************************************************//**
+ * @file
* @brief CMSIS Cortex-M System Layer for EFM32 devices.
- * @version 5.4.0
- ******************************************************************************
+ *******************************************************************************
* # License
- * Copyright 2017 Silicon Laboratories, Inc. www.silabs.com
- ******************************************************************************
+ * Copyright 2020 Silicon Laboratories Inc. www.silabs.com
+ *******************************************************************************
+ *
+ * SPDX-License-Identifier: Zlib
+ *
+ * The licensor of this software is Silicon Laboratories Inc.
+ *
+ * This software is provided 'as-is', without any express or implied
+ * warranty. In no event will the authors be held liable for any damages
+ * arising from the use of this software.
*
* Permission is granted to anyone to use this software for any purpose,
* including commercial applications, and to alter it and redistribute it
* freely, subject to the following restrictions:
*
* 1. The origin of this software must not be misrepresented; you must not
- * claim that you wrote the original software.@n
+ * claim that you wrote the original software. If you use this software
+ * in a product, an acknowledgment in the product documentation would be
+ * appreciated but is not required.
* 2. Altered source versions must be plainly marked as such, and must not be
- * misrepresented as being the original software.@n
+ * misrepresented as being the original software.
* 3. This notice may not be removed or altered from any source distribution.
*
- * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
- * has no obligation to support this Software. Silicon Laboratories, Inc. is
- * providing the Software "AS IS", with no express or implied warranties of any
- * kind, including, but not limited to, any implied warranties of
- * merchantability or fitness for any particular purpose or warranties against
- * infringement of any proprietary rights of a third party.
- *
- * Silicon Laboratories, Inc. will not be liable for any consequential,
- * incidental, or special damages, or any other relief, or for any claim by
- * any third party, arising from your use of this Software.
- *
- *****************************************************************************/
+ ******************************************************************************/
#ifndef SYSTEM_EFM32ZG_H
#define SYSTEM_EFM32ZG_H
@@ -39,14 +37,24 @@ extern "C" {
#include
-/**************************************************************************//**
+/***************************************************************************//**
* @addtogroup Parts
* @{
- *****************************************************************************/
-/**************************************************************************//**
+ ******************************************************************************/
+/***************************************************************************//**
* @addtogroup EFM32ZG EFM32ZG
* @{
- *****************************************************************************/
+ ******************************************************************************/
+
+/*******************************************************************************
+ ****************************** TYPEDEFS ***********************************
+ ******************************************************************************/
+
+/* Interrupt vectortable entry */
+typedef union {
+ void (*pFunc)(void);
+ void *topOfStack;
+} tVectorEntry;
/*******************************************************************************
************************** GLOBAL VARIABLES *******************************
@@ -54,6 +62,13 @@ extern "C" {
extern uint32_t SystemCoreClock; /**< System Clock Frequency (Core Clock) */
+#if defined(__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+#if defined(__ICCARM__) /* IAR requires the __vector_table symbol */
+#define __Vectors __vector_table
+#endif
+extern const tVectorEntry __Vectors[];
+#endif
+
/*******************************************************************************
***************************** PROTOTYPES **********************************
******************************************************************************/
@@ -87,7 +102,7 @@ void AES_IRQHandler(void); /**< AES IRQ Handler */
uint32_t SystemCoreClockGet(void);
uint32_t SystemMaxCoreClockGet(void);
-/**************************************************************************//**
+/***************************************************************************//**
* @brief
* Update CMSIS SystemCoreClock variable.
*
@@ -100,7 +115,7 @@ uint32_t SystemMaxCoreClockGet(void);
* API, this variable will be kept updated. This function is only provided
* for CMSIS compliance and if a user modifies the the core clock outside
* the CMU API.
- *****************************************************************************/
+ ******************************************************************************/
static __INLINE void SystemCoreClockUpdate(void)
{
(void)SystemCoreClockGet();
diff --git a/cpu/efm32/families/efm32zg/system.c b/cpu/efm32/families/efm32zg/system.c
index e7af3806c2..1fa5380883 100644
--- a/cpu/efm32/families/efm32zg/system.c
+++ b/cpu/efm32/families/efm32zg/system.c
@@ -1,34 +1,32 @@
/***************************************************************************//**
- * @file system_efm32zg.c
+ * @file
* @brief CMSIS Cortex-M0+ System Layer for EFM32ZG devices.
- * @version 5.4.0
- ******************************************************************************
+ *******************************************************************************
* # License
- * Copyright 2017 Silicon Laboratories, Inc. www.silabs.com
- ******************************************************************************
+ * Copyright 2020 Silicon Laboratories Inc. www.silabs.com
+ *******************************************************************************
+ *
+ * SPDX-License-Identifier: Zlib
+ *
+ * The licensor of this software is Silicon Laboratories Inc.
+ *
+ * This software is provided 'as-is', without any express or implied
+ * warranty. In no event will the authors be held liable for any damages
+ * arising from the use of this software.
*
* Permission is granted to anyone to use this software for any purpose,
* including commercial applications, and to alter it and redistribute it
* freely, subject to the following restrictions:
*
* 1. The origin of this software must not be misrepresented; you must not
- * claim that you wrote the original software.@n
+ * claim that you wrote the original software. If you use this software
+ * in a product, an acknowledgment in the product documentation would be
+ * appreciated but is not required.
* 2. Altered source versions must be plainly marked as such, and must not be
- * misrepresented as being the original software.@n
+ * misrepresented as being the original software.
* 3. This notice may not be removed or altered from any source distribution.
*
- * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
- * has no obligation to support this Software. Silicon Laboratories, Inc. is
- * providing the Software "AS IS", with no express or implied warranties of any
- * kind, including, but not limited to, any implied warranties of
- * merchantability or fitness for any particular purpose or warranties against
- * infringement of any proprietary rights of a third party.
- *
- * Silicon Laboratories, Inc. will not be liable for any consequential,
- * incidental, or special damages, or any other relief, or for any claim by
- * any third party, arising from your use of this Software.
- *
- *****************************************************************************/
+ ******************************************************************************/
#include
#include "em_device.h"
@@ -63,7 +61,7 @@
#define EFM32_HFRCO_MAX_FREQ (21000000UL)
/* Do not define variable if HF crystal oscillator not present */
-#if (EFM32_HFXO_FREQ > 0)
+#if (EFM32_HFXO_FREQ > 0U)
/** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */
/** System HFXO clock. */
static uint32_t SystemHFXOClock = EFM32_HFXO_FREQ;
@@ -76,7 +74,7 @@ static uint32_t SystemHFXOClock = EFM32_HFXO_FREQ;
#endif
/* Do not define variable if LF crystal oscillator not present */
-#if (EFM32_LFXO_FREQ > 0)
+#if (EFM32_LFXO_FREQ > 0U)
/** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */
/** System LFXO clock. */
static uint32_t SystemLFXOClock = EFM32_LFXO_FREQ;
@@ -167,12 +165,12 @@ uint32_t SystemHFClockGet(void)
switch (CMU->STATUS & (CMU_STATUS_HFRCOSEL | CMU_STATUS_HFXOSEL
| CMU_STATUS_LFRCOSEL | CMU_STATUS_LFXOSEL)) {
case CMU_STATUS_LFXOSEL:
-#if (EFM32_LFXO_FREQ > 0)
+#if (EFM32_LFXO_FREQ > 0U)
ret = SystemLFXOClock;
#else
/* We should not get here, since core should not be clocked. May */
/* be caused by a misconfiguration though. */
- ret = 0;
+ ret = 0U;
#endif
break;
@@ -181,12 +179,12 @@ uint32_t SystemHFClockGet(void)
break;
case CMU_STATUS_HFXOSEL:
-#if (EFM32_HFXO_FREQ > 0)
+#if (EFM32_HFXO_FREQ > 0U)
ret = SystemHFXOClock;
#else
/* We should not get here, since core should not be clocked. May */
/* be caused by a misconfiguration though. */
- ret = 0;
+ ret = 0U;
#endif
break;
@@ -213,7 +211,7 @@ uint32_t SystemHFClockGet(void)
break;
default:
- ret = 0;
+ ret = 0U;
break;
}
break;
@@ -222,7 +220,7 @@ uint32_t SystemHFClockGet(void)
return ret;
}
-/**************************************************************************//**
+/***************************************************************************//**
* @brief
* Get high frequency crystal oscillator clock frequency for target system.
*
@@ -231,18 +229,18 @@ uint32_t SystemHFClockGet(void)
*
* @return
* HFXO frequency in Hz.
- *****************************************************************************/
+ ******************************************************************************/
uint32_t SystemHFXOClockGet(void)
{
/* External crystal oscillator present? */
-#if (EFM32_HFXO_FREQ > 0)
+#if (EFM32_HFXO_FREQ > 0U)
return SystemHFXOClock;
#else
- return 0;
+ return 0U;
#endif
}
-/**************************************************************************//**
+/***************************************************************************//**
* @brief
* Set high frequency crystal oscillator clock frequency for target system.
*
@@ -256,11 +254,11 @@ uint32_t SystemHFXOClockGet(void)
*
* @param[in] freq
* HFXO frequency in Hz used for target.
- *****************************************************************************/
+ ******************************************************************************/
void SystemHFXOClockSet(uint32_t freq)
{
/* External crystal oscillator present? */
-#if (EFM32_HFXO_FREQ > 0)
+#if (EFM32_HFXO_FREQ > 0U)
SystemHFXOClock = freq;
/* Update core clock frequency if HFXO is used to clock core */
@@ -273,7 +271,7 @@ void SystemHFXOClockSet(uint32_t freq)
#endif
}
-/**************************************************************************//**
+/***************************************************************************//**
* @brief
* Initialize the system.
*
@@ -284,12 +282,15 @@ void SystemHFXOClockSet(uint32_t freq)
* This function is invoked during system init, before the main() routine
* and any data has been initialized. For this reason, it cannot do any
* initialization of variables etc.
- *****************************************************************************/
+ ******************************************************************************/
void SystemInit(void)
{
+#if defined(__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+ SCB->VTOR = (uint32_t)&__Vectors;
+#endif
}
-/**************************************************************************//**
+/***************************************************************************//**
* @brief
* Get low frequency RC oscillator clock frequency for target system.
*
@@ -298,7 +299,7 @@ void SystemInit(void)
*
* @return
* LFRCO frequency in Hz.
- *****************************************************************************/
+ ******************************************************************************/
uint32_t SystemLFRCOClockGet(void)
{
/* Currently we assume that this frequency is properly tuned during */
@@ -307,7 +308,7 @@ uint32_t SystemLFRCOClockGet(void)
return EFM32_LFRCO_FREQ;
}
-/**************************************************************************//**
+/***************************************************************************//**
* @brief
* Get ultra low frequency RC oscillator clock frequency for target system.
*
@@ -316,14 +317,14 @@ uint32_t SystemLFRCOClockGet(void)
*
* @return
* ULFRCO frequency in Hz.
- *****************************************************************************/
+ ******************************************************************************/
uint32_t SystemULFRCOClockGet(void)
{
/* The ULFRCO frequency is not tuned, and can be very inaccurate */
return EFM32_ULFRCO_FREQ;
}
-/**************************************************************************//**
+/***************************************************************************//**
* @brief
* Get low frequency crystal oscillator clock frequency for target system.
*
@@ -332,18 +333,18 @@ uint32_t SystemULFRCOClockGet(void)
*
* @return
* LFXO frequency in Hz.
- *****************************************************************************/
+ ******************************************************************************/
uint32_t SystemLFXOClockGet(void)
{
/* External crystal oscillator present? */
-#if (EFM32_LFXO_FREQ > 0)
+#if (EFM32_LFXO_FREQ > 0U)
return SystemLFXOClock;
#else
- return 0;
+ return 0U;
#endif
}
-/**************************************************************************//**
+/***************************************************************************//**
* @brief
* Set low frequency crystal oscillator clock frequency for target system.
*
@@ -357,11 +358,11 @@ uint32_t SystemLFXOClockGet(void)
*
* @param[in] freq
* LFXO frequency in Hz used for target.
- *****************************************************************************/
+ ******************************************************************************/
void SystemLFXOClockSet(uint32_t freq)
{
/* External crystal oscillator present? */
-#if (EFM32_LFXO_FREQ > 0)
+#if (EFM32_LFXO_FREQ > 0U)
SystemLFXOClock = freq;
/* Update core clock frequency if LFXO is used to clock core */
diff --git a/cpu/efm32/families/efr32mg12p/Makefile.include b/cpu/efm32/families/efr32mg12p/Makefile.include
index ada98dbed5..ade161eb69 100644
--- a/cpu/efm32/families/efr32mg12p/Makefile.include
+++ b/cpu/efm32/families/efr32mg12p/Makefile.include
@@ -4,4 +4,4 @@
EFM32_HEADER = $(wildcard $(RIOTCPU)/efm32/families/efr32mg12p/include/vendor/$(CPU_MODEL).h)
# include vendor device headers
-INCLUDES += -I$(RIOTCPU)/efm32/families/efr32mg12p/include/vendor
+INCLUDES += -I$(RIOTCPU)/efm32/families/efr32mg12p/include/vendor
\ No newline at end of file
diff --git a/cpu/efm32/families/efr32mg12p/include/vendor/efr32mg12p332f1024gl125.h b/cpu/efm32/families/efr32mg12p/include/vendor/efr32mg12p332f1024gl125.h
index 6abd26b3b7..44c7b67e57 100644
--- a/cpu/efm32/families/efr32mg12p/include/vendor/efr32mg12p332f1024gl125.h
+++ b/cpu/efm32/families/efr32mg12p/include/vendor/efr32mg12p332f1024gl125.h
@@ -2,10 +2,9 @@
* @file
* @brief CMSIS Cortex-M Peripheral Access Layer Header File
* for EFR32MG12P332F1024GL125
- * @version 5.8.3
*******************************************************************************
* # License
- * Copyright 2019 Silicon Laboratories Inc. www.silabs.com
+ * Copyright 2020 Silicon Laboratories Inc. www.silabs.com
*******************************************************************************
*
* SPDX-License-Identifier: Zlib
@@ -167,58 +166,18 @@ typedef enum IRQn{
#define PART_NUMBER "EFR32MG12P332F1024GL125" /**< Part Number */
/** Memory Base addresses and limits */
-#define RAM0_CODE_MEM_BASE (0x10000000UL) /**< RAM0_CODE base address */
-#define RAM0_CODE_MEM_SIZE (0x20000UL) /**< RAM0_CODE available address space */
-#define RAM0_CODE_MEM_END (0x1001FFFFUL) /**< RAM0_CODE end address */
-#define RAM0_CODE_MEM_BITS (0x00000011UL) /**< RAM0_CODE used bits */
-#define RAM2_MEM_BASE (0x20040000UL) /**< RAM2 base address */
-#define RAM2_MEM_SIZE (0x800UL) /**< RAM2 available address space */
-#define RAM2_MEM_END (0x200407FFUL) /**< RAM2 end address */
-#define RAM2_MEM_BITS (0x0000000BUL) /**< RAM2 used bits */
-#define RAM1_MEM_BASE (0x20020000UL) /**< RAM1 base address */
-#define RAM1_MEM_SIZE (0x20000UL) /**< RAM1 available address space */
-#define RAM1_MEM_END (0x2003FFFFUL) /**< RAM1 end address */
-#define RAM1_MEM_BITS (0x00000011UL) /**< RAM1 used bits */
#define CRYPTO1_BITCLR_MEM_BASE (0x440F0400UL) /**< CRYPTO1_BITCLR base address */
#define CRYPTO1_BITCLR_MEM_SIZE (0x400UL) /**< CRYPTO1_BITCLR available address space */
#define CRYPTO1_BITCLR_MEM_END (0x440F07FFUL) /**< CRYPTO1_BITCLR end address */
#define CRYPTO1_BITCLR_MEM_BITS (0x0000000AUL) /**< CRYPTO1_BITCLR used bits */
-#define PER_MEM_BASE (0x40000000UL) /**< PER base address */
-#define PER_MEM_SIZE (0xF0000UL) /**< PER available address space */
-#define PER_MEM_END (0x400EFFFFUL) /**< PER end address */
-#define PER_MEM_BITS (0x00000014UL) /**< PER used bits */
-#define RAM1_CODE_MEM_BASE (0x10020000UL) /**< RAM1_CODE base address */
-#define RAM1_CODE_MEM_SIZE (0x20000UL) /**< RAM1_CODE available address space */
-#define RAM1_CODE_MEM_END (0x1003FFFFUL) /**< RAM1_CODE end address */
-#define RAM1_CODE_MEM_BITS (0x00000011UL) /**< RAM1_CODE used bits */
-#define CRYPTO1_MEM_BASE (0x400F0400UL) /**< CRYPTO1 base address */
-#define CRYPTO1_MEM_SIZE (0x400UL) /**< CRYPTO1 available address space */
-#define CRYPTO1_MEM_END (0x400F07FFUL) /**< CRYPTO1 end address */
-#define CRYPTO1_MEM_BITS (0x0000000AUL) /**< CRYPTO1 used bits */
-#define FLASH_MEM_BASE (0x00000000UL) /**< FLASH base address */
-#define FLASH_MEM_SIZE (0x10000000UL) /**< FLASH available address space */
-#define FLASH_MEM_END (0x0FFFFFFFUL) /**< FLASH end address */
-#define FLASH_MEM_BITS (0x0000001CUL) /**< FLASH used bits */
-#define CRYPTO0_MEM_BASE (0x400F0000UL) /**< CRYPTO0 base address */
-#define CRYPTO0_MEM_SIZE (0x400UL) /**< CRYPTO0 available address space */
-#define CRYPTO0_MEM_END (0x400F03FFUL) /**< CRYPTO0 end address */
-#define CRYPTO0_MEM_BITS (0x0000000AUL) /**< CRYPTO0 used bits */
-#define CRYPTO_MEM_BASE CRYPTO0_MEM_BASE /**< Alias for CRYPTO0_MEM_BASE */
-#define CRYPTO_MEM_SIZE CRYPTO0_MEM_SIZE /**< Alias for CRYPTO0_MEM_SIZE */
-#define CRYPTO_MEM_END CRYPTO0_MEM_END /**< Alias for CRYPTO0_MEM_END */
-#define CRYPTO_MEM_BITS CRYPTO0_MEM_BITS /**< Alias for CRYPTO0_MEM_BITS */
-#define PER_BITCLR_MEM_BASE (0x44000000UL) /**< PER_BITCLR base address */
-#define PER_BITCLR_MEM_SIZE (0xF0000UL) /**< PER_BITCLR available address space */
-#define PER_BITCLR_MEM_END (0x440EFFFFUL) /**< PER_BITCLR end address */
-#define PER_BITCLR_MEM_BITS (0x00000014UL) /**< PER_BITCLR used bits */
-#define CRYPTO0_BITSET_MEM_BASE (0x460F0000UL) /**< CRYPTO0_BITSET base address */
-#define CRYPTO0_BITSET_MEM_SIZE (0x400UL) /**< CRYPTO0_BITSET available address space */
-#define CRYPTO0_BITSET_MEM_END (0x460F03FFUL) /**< CRYPTO0_BITSET end address */
-#define CRYPTO0_BITSET_MEM_BITS (0x0000000AUL) /**< CRYPTO0_BITSET used bits */
-#define CRYPTO_BITSET_MEM_BASE CRYPTO0_BITSET_MEM_BASE /**< Alias for CRYPTO0_BITSET_MEM_BASE */
-#define CRYPTO_BITSET_MEM_SIZE CRYPTO0_BITSET_MEM_SIZE /**< Alias for CRYPTO0_BITSET_MEM_SIZE */
-#define CRYPTO_BITSET_MEM_END CRYPTO0_BITSET_MEM_END /**< Alias for CRYPTO0_BITSET_MEM_END */
-#define CRYPTO_BITSET_MEM_BITS CRYPTO0_BITSET_MEM_BITS /**< Alias for CRYPTO0_BITSET_MEM_BITS */
+#define RAM1_MEM_BASE (0x20020000UL) /**< RAM1 base address */
+#define RAM1_MEM_SIZE (0x20000UL) /**< RAM1 available address space */
+#define RAM1_MEM_END (0x2003FFFFUL) /**< RAM1 end address */
+#define RAM1_MEM_BITS (0x00000011UL) /**< RAM1 used bits */
+#define RAM2_MEM_BASE (0x20040000UL) /**< RAM2 base address */
+#define RAM2_MEM_SIZE (0x800UL) /**< RAM2 available address space */
+#define RAM2_MEM_END (0x200407FFUL) /**< RAM2 end address */
+#define RAM2_MEM_BITS (0x0000000BUL) /**< RAM2 used bits */
#define CRYPTO0_BITCLR_MEM_BASE (0x440F0000UL) /**< CRYPTO0_BITCLR base address */
#define CRYPTO0_BITCLR_MEM_SIZE (0x400UL) /**< CRYPTO0_BITCLR available address space */
#define CRYPTO0_BITCLR_MEM_END (0x440F03FFUL) /**< CRYPTO0_BITCLR end address */
@@ -227,22 +186,62 @@ typedef enum IRQn{
#define CRYPTO_BITCLR_MEM_SIZE CRYPTO0_BITCLR_MEM_SIZE /**< Alias for CRYPTO0_BITCLR_MEM_SIZE */
#define CRYPTO_BITCLR_MEM_END CRYPTO0_BITCLR_MEM_END /**< Alias for CRYPTO0_BITCLR_MEM_END */
#define CRYPTO_BITCLR_MEM_BITS CRYPTO0_BITCLR_MEM_BITS /**< Alias for CRYPTO0_BITCLR_MEM_BITS */
-#define PER_BITSET_MEM_BASE (0x46000000UL) /**< PER_BITSET base address */
-#define PER_BITSET_MEM_SIZE (0xF0000UL) /**< PER_BITSET available address space */
-#define PER_BITSET_MEM_END (0x460EFFFFUL) /**< PER_BITSET end address */
-#define PER_BITSET_MEM_BITS (0x00000014UL) /**< PER_BITSET used bits */
+#define CRYPTO1_MEM_BASE (0x400F0400UL) /**< CRYPTO1 base address */
+#define CRYPTO1_MEM_SIZE (0x400UL) /**< CRYPTO1 available address space */
+#define CRYPTO1_MEM_END (0x400F07FFUL) /**< CRYPTO1 end address */
+#define CRYPTO1_MEM_BITS (0x0000000AUL) /**< CRYPTO1 used bits */
+#define CRYPTO0_BITSET_MEM_BASE (0x460F0000UL) /**< CRYPTO0_BITSET base address */
+#define CRYPTO0_BITSET_MEM_SIZE (0x400UL) /**< CRYPTO0_BITSET available address space */
+#define CRYPTO0_BITSET_MEM_END (0x460F03FFUL) /**< CRYPTO0_BITSET end address */
+#define CRYPTO0_BITSET_MEM_BITS (0x0000000AUL) /**< CRYPTO0_BITSET used bits */
+#define CRYPTO_BITSET_MEM_BASE CRYPTO0_BITSET_MEM_BASE /**< Alias for CRYPTO0_BITSET_MEM_BASE */
+#define CRYPTO_BITSET_MEM_SIZE CRYPTO0_BITSET_MEM_SIZE /**< Alias for CRYPTO0_BITSET_MEM_SIZE */
+#define CRYPTO_BITSET_MEM_END CRYPTO0_BITSET_MEM_END /**< Alias for CRYPTO0_BITSET_MEM_END */
+#define CRYPTO_BITSET_MEM_BITS CRYPTO0_BITSET_MEM_BITS /**< Alias for CRYPTO0_BITSET_MEM_BITS */
+#define RAM1_CODE_MEM_BASE (0x10020000UL) /**< RAM1_CODE base address */
+#define RAM1_CODE_MEM_SIZE (0x20000UL) /**< RAM1_CODE available address space */
+#define RAM1_CODE_MEM_END (0x1003FFFFUL) /**< RAM1_CODE end address */
+#define RAM1_CODE_MEM_BITS (0x00000011UL) /**< RAM1_CODE used bits */
+#define RAM0_CODE_MEM_BASE (0x10000000UL) /**< RAM0_CODE base address */
+#define RAM0_CODE_MEM_SIZE (0x20000UL) /**< RAM0_CODE available address space */
+#define RAM0_CODE_MEM_END (0x1001FFFFUL) /**< RAM0_CODE end address */
+#define RAM0_CODE_MEM_BITS (0x00000011UL) /**< RAM0_CODE used bits */
+#define FLASH_MEM_BASE (0x00000000UL) /**< FLASH base address */
+#define FLASH_MEM_SIZE (0x10000000UL) /**< FLASH available address space */
+#define FLASH_MEM_END (0x0FFFFFFFUL) /**< FLASH end address */
+#define FLASH_MEM_BITS (0x0000001CUL) /**< FLASH used bits */
#define CRYPTO1_BITSET_MEM_BASE (0x460F0400UL) /**< CRYPTO1_BITSET base address */
#define CRYPTO1_BITSET_MEM_SIZE (0x400UL) /**< CRYPTO1_BITSET available address space */
#define CRYPTO1_BITSET_MEM_END (0x460F07FFUL) /**< CRYPTO1_BITSET end address */
#define CRYPTO1_BITSET_MEM_BITS (0x0000000AUL) /**< CRYPTO1_BITSET used bits */
-#define RAM2_CODE_MEM_BASE (0x10040000UL) /**< RAM2_CODE base address */
-#define RAM2_CODE_MEM_SIZE (0x800UL) /**< RAM2_CODE available address space */
-#define RAM2_CODE_MEM_END (0x100407FFUL) /**< RAM2_CODE end address */
-#define RAM2_CODE_MEM_BITS (0x0000000BUL) /**< RAM2_CODE used bits */
#define RAM_MEM_BASE (0x20000000UL) /**< RAM base address */
#define RAM_MEM_SIZE (0x20000UL) /**< RAM available address space */
#define RAM_MEM_END (0x2001FFFFUL) /**< RAM end address */
#define RAM_MEM_BITS (0x00000011UL) /**< RAM used bits */
+#define CRYPTO0_MEM_BASE (0x400F0000UL) /**< CRYPTO0 base address */
+#define CRYPTO0_MEM_SIZE (0x400UL) /**< CRYPTO0 available address space */
+#define CRYPTO0_MEM_END (0x400F03FFUL) /**< CRYPTO0 end address */
+#define CRYPTO0_MEM_BITS (0x0000000AUL) /**< CRYPTO0 used bits */
+#define CRYPTO_MEM_BASE CRYPTO0_MEM_BASE /**< Alias for CRYPTO0_MEM_BASE */
+#define CRYPTO_MEM_SIZE CRYPTO0_MEM_SIZE /**< Alias for CRYPTO0_MEM_SIZE */
+#define CRYPTO_MEM_END CRYPTO0_MEM_END /**< Alias for CRYPTO0_MEM_END */
+#define CRYPTO_MEM_BITS CRYPTO0_MEM_BITS /**< Alias for CRYPTO0_MEM_BITS */
+#define PER_BITSET_MEM_BASE (0x46000000UL) /**< PER_BITSET base address */
+#define PER_BITSET_MEM_SIZE (0xF0000UL) /**< PER_BITSET available address space */
+#define PER_BITSET_MEM_END (0x460EFFFFUL) /**< PER_BITSET end address */
+#define PER_BITSET_MEM_BITS (0x00000014UL) /**< PER_BITSET used bits */
+#define PER_MEM_BASE (0x40000000UL) /**< PER base address */
+#define PER_MEM_SIZE (0xF0000UL) /**< PER available address space */
+#define PER_MEM_END (0x400EFFFFUL) /**< PER end address */
+#define PER_MEM_BITS (0x00000014UL) /**< PER used bits */
+#define RAM2_CODE_MEM_BASE (0x10040000UL) /**< RAM2_CODE base address */
+#define RAM2_CODE_MEM_SIZE (0x800UL) /**< RAM2_CODE available address space */
+#define RAM2_CODE_MEM_END (0x100407FFUL) /**< RAM2_CODE end address */
+#define RAM2_CODE_MEM_BITS (0x0000000BUL) /**< RAM2_CODE used bits */
+#define PER_BITCLR_MEM_BASE (0x44000000UL) /**< PER_BITCLR base address */
+#define PER_BITCLR_MEM_SIZE (0xF0000UL) /**< PER_BITCLR available address space */
+#define PER_BITCLR_MEM_END (0x440EFFFFUL) /**< PER_BITCLR end address */
+#define PER_BITCLR_MEM_BITS (0x00000014UL) /**< PER_BITCLR used bits */
/** Bit banding area */
#define BITBAND_PER_BASE (0x42000000UL) /**< Peripheral Address Space bit-band area */
@@ -1027,13 +1026,13 @@ typedef enum IRQn{
#define _WTIMER_LOCK_TIMERLOCKKEY_SHIFT 0 /**< Shift value for TIMER_TIMERLOCKKEY */
#define _WTIMER_LOCK_TIMERLOCKKEY_MASK 0xFFFFUL /**< Bit mask for TIMER_TIMERLOCKKEY */
#define _WTIMER_LOCK_TIMERLOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_LOCK */
-#define _WTIMER_LOCK_TIMERLOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for WTIMER_LOCK */
#define _WTIMER_LOCK_TIMERLOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for WTIMER_LOCK */
+#define _WTIMER_LOCK_TIMERLOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for WTIMER_LOCK */
#define _WTIMER_LOCK_TIMERLOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for WTIMER_LOCK */
#define _WTIMER_LOCK_TIMERLOCKKEY_UNLOCK 0x0000CE80UL /**< Mode UNLOCK for WTIMER_LOCK */
#define WTIMER_LOCK_TIMERLOCKKEY_DEFAULT (_WTIMER_LOCK_TIMERLOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_LOCK */
-#define WTIMER_LOCK_TIMERLOCKKEY_LOCK (_WTIMER_LOCK_TIMERLOCKKEY_LOCK << 0) /**< Shifted mode LOCK for WTIMER_LOCK */
#define WTIMER_LOCK_TIMERLOCKKEY_UNLOCKED (_WTIMER_LOCK_TIMERLOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for WTIMER_LOCK */
+#define WTIMER_LOCK_TIMERLOCKKEY_LOCK (_WTIMER_LOCK_TIMERLOCKKEY_LOCK << 0) /**< Shifted mode LOCK for WTIMER_LOCK */
#define WTIMER_LOCK_TIMERLOCKKEY_LOCKED (_WTIMER_LOCK_TIMERLOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for WTIMER_LOCK */
#define WTIMER_LOCK_TIMERLOCKKEY_UNLOCK (_WTIMER_LOCK_TIMERLOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for WTIMER_LOCK */
@@ -2014,13 +2013,13 @@ typedef enum IRQn{
#define _WTIMER_DTLOCK_LOCKKEY_SHIFT 0 /**< Shift value for TIMER_LOCKKEY */
#define _WTIMER_DTLOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for TIMER_LOCKKEY */
#define _WTIMER_DTLOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTLOCK */
-#define _WTIMER_DTLOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for WTIMER_DTLOCK */
#define _WTIMER_DTLOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for WTIMER_DTLOCK */
+#define _WTIMER_DTLOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for WTIMER_DTLOCK */
#define _WTIMER_DTLOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for WTIMER_DTLOCK */
#define _WTIMER_DTLOCK_LOCKKEY_UNLOCK 0x0000CE80UL /**< Mode UNLOCK for WTIMER_DTLOCK */
#define WTIMER_DTLOCK_LOCKKEY_DEFAULT (_WTIMER_DTLOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTLOCK */
-#define WTIMER_DTLOCK_LOCKKEY_LOCK (_WTIMER_DTLOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for WTIMER_DTLOCK */
#define WTIMER_DTLOCK_LOCKKEY_UNLOCKED (_WTIMER_DTLOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for WTIMER_DTLOCK */
+#define WTIMER_DTLOCK_LOCKKEY_LOCK (_WTIMER_DTLOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for WTIMER_DTLOCK */
#define WTIMER_DTLOCK_LOCKKEY_LOCKED (_WTIMER_DTLOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for WTIMER_DTLOCK */
#define WTIMER_DTLOCK_LOCKKEY_UNLOCK (_WTIMER_DTLOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for WTIMER_DTLOCK */
diff --git a/cpu/efm32/families/efr32mg12p/include/vendor/efr32mg12p_acmp.h b/cpu/efm32/families/efr32mg12p/include/vendor/efr32mg12p_acmp.h
index 98c22f8506..615899b12c 100644
--- a/cpu/efm32/families/efr32mg12p/include/vendor/efr32mg12p_acmp.h
+++ b/cpu/efm32/families/efr32mg12p/include/vendor/efr32mg12p_acmp.h
@@ -1,10 +1,9 @@
/***************************************************************************//**
* @file
* @brief EFR32MG12P_ACMP register and bit field definitions
- * @version 5.8.3
*******************************************************************************
* # License
- * Copyright 2019 Silicon Laboratories Inc. www.silabs.com
+ * Copyright 2020 Silicon Laboratories Inc. www.silabs.com
*******************************************************************************
*
* SPDX-License-Identifier: Zlib
@@ -325,6 +324,8 @@ typedef struct {
#define _ACMP_INPUTSEL_POSSEL_APORT4XCH11 0x0000008BUL /**< Mode APORT4XCH11 for ACMP_INPUTSEL */
#define _ACMP_INPUTSEL_POSSEL_APORT4YCH12 0x0000008CUL /**< Mode APORT4YCH12 for ACMP_INPUTSEL */
#define _ACMP_INPUTSEL_POSSEL_APORT4XCH13 0x0000008DUL /**< Mode APORT4XCH13 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_POSSEL_APORT4YCH14 0x0000008EUL /**< Mode APORT4YCH14 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_POSSEL_APORT4XCH15 0x0000008FUL /**< Mode APORT4XCH15 for ACMP_INPUTSEL */
#define _ACMP_INPUTSEL_POSSEL_APORT4YCH16 0x00000090UL /**< Mode APORT4YCH16 for ACMP_INPUTSEL */
#define _ACMP_INPUTSEL_POSSEL_APORT4XCH17 0x00000091UL /**< Mode APORT4XCH17 for ACMP_INPUTSEL */
#define _ACMP_INPUTSEL_POSSEL_APORT4YCH18 0x00000092UL /**< Mode APORT4YCH18 for ACMP_INPUTSEL */
@@ -340,8 +341,6 @@ typedef struct {
#define _ACMP_INPUTSEL_POSSEL_APORT4YCH28 0x0000009CUL /**< Mode APORT4YCH28 for ACMP_INPUTSEL */
#define _ACMP_INPUTSEL_POSSEL_APORT4XCH29 0x0000009DUL /**< Mode APORT4XCH29 for ACMP_INPUTSEL */
#define _ACMP_INPUTSEL_POSSEL_APORT4YCH30 0x0000009EUL /**< Mode APORT4YCH30 for ACMP_INPUTSEL */
-#define _ACMP_INPUTSEL_POSSEL_APORT4YCH14 0x0000009EUL /**< Mode APORT4YCH14 for ACMP_INPUTSEL */
-#define _ACMP_INPUTSEL_POSSEL_APORT4XCH15 0x0000009FUL /**< Mode APORT4XCH15 for ACMP_INPUTSEL */
#define _ACMP_INPUTSEL_POSSEL_APORT4XCH31 0x0000009FUL /**< Mode APORT4XCH31 for ACMP_INPUTSEL */
#define _ACMP_INPUTSEL_POSSEL_DACOUT0 0x000000F2UL /**< Mode DACOUT0 for ACMP_INPUTSEL */
#define _ACMP_INPUTSEL_POSSEL_DACOUT1 0x000000F3UL /**< Mode DACOUT1 for ACMP_INPUTSEL */
@@ -493,6 +492,8 @@ typedef struct {
#define ACMP_INPUTSEL_POSSEL_APORT4XCH11 (_ACMP_INPUTSEL_POSSEL_APORT4XCH11 << 0) /**< Shifted mode APORT4XCH11 for ACMP_INPUTSEL */
#define ACMP_INPUTSEL_POSSEL_APORT4YCH12 (_ACMP_INPUTSEL_POSSEL_APORT4YCH12 << 0) /**< Shifted mode APORT4YCH12 for ACMP_INPUTSEL */
#define ACMP_INPUTSEL_POSSEL_APORT4XCH13 (_ACMP_INPUTSEL_POSSEL_APORT4XCH13 << 0) /**< Shifted mode APORT4XCH13 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_POSSEL_APORT4YCH14 (_ACMP_INPUTSEL_POSSEL_APORT4YCH14 << 0) /**< Shifted mode APORT4YCH14 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_POSSEL_APORT4XCH15 (_ACMP_INPUTSEL_POSSEL_APORT4XCH15 << 0) /**< Shifted mode APORT4XCH15 for ACMP_INPUTSEL */
#define ACMP_INPUTSEL_POSSEL_APORT4YCH16 (_ACMP_INPUTSEL_POSSEL_APORT4YCH16 << 0) /**< Shifted mode APORT4YCH16 for ACMP_INPUTSEL */
#define ACMP_INPUTSEL_POSSEL_APORT4XCH17 (_ACMP_INPUTSEL_POSSEL_APORT4XCH17 << 0) /**< Shifted mode APORT4XCH17 for ACMP_INPUTSEL */
#define ACMP_INPUTSEL_POSSEL_APORT4YCH18 (_ACMP_INPUTSEL_POSSEL_APORT4YCH18 << 0) /**< Shifted mode APORT4YCH18 for ACMP_INPUTSEL */
@@ -508,8 +509,6 @@ typedef struct {
#define ACMP_INPUTSEL_POSSEL_APORT4YCH28 (_ACMP_INPUTSEL_POSSEL_APORT4YCH28 << 0) /**< Shifted mode APORT4YCH28 for ACMP_INPUTSEL */
#define ACMP_INPUTSEL_POSSEL_APORT4XCH29 (_ACMP_INPUTSEL_POSSEL_APORT4XCH29 << 0) /**< Shifted mode APORT4XCH29 for ACMP_INPUTSEL */
#define ACMP_INPUTSEL_POSSEL_APORT4YCH30 (_ACMP_INPUTSEL_POSSEL_APORT4YCH30 << 0) /**< Shifted mode APORT4YCH30 for ACMP_INPUTSEL */
-#define ACMP_INPUTSEL_POSSEL_APORT4YCH14 (_ACMP_INPUTSEL_POSSEL_APORT4YCH14 << 0) /**< Shifted mode APORT4YCH14 for ACMP_INPUTSEL */
-#define ACMP_INPUTSEL_POSSEL_APORT4XCH15 (_ACMP_INPUTSEL_POSSEL_APORT4XCH15 << 0) /**< Shifted mode APORT4XCH15 for ACMP_INPUTSEL */
#define ACMP_INPUTSEL_POSSEL_APORT4XCH31 (_ACMP_INPUTSEL_POSSEL_APORT4XCH31 << 0) /**< Shifted mode APORT4XCH31 for ACMP_INPUTSEL */
#define ACMP_INPUTSEL_POSSEL_DACOUT0 (_ACMP_INPUTSEL_POSSEL_DACOUT0 << 0) /**< Shifted mode DACOUT0 for ACMP_INPUTSEL */
#define ACMP_INPUTSEL_POSSEL_DACOUT1 (_ACMP_INPUTSEL_POSSEL_DACOUT1 << 0) /**< Shifted mode DACOUT1 for ACMP_INPUTSEL */
@@ -663,6 +662,8 @@ typedef struct {
#define _ACMP_INPUTSEL_NEGSEL_APORT4XCH11 0x0000008BUL /**< Mode APORT4XCH11 for ACMP_INPUTSEL */
#define _ACMP_INPUTSEL_NEGSEL_APORT4YCH12 0x0000008CUL /**< Mode APORT4YCH12 for ACMP_INPUTSEL */
#define _ACMP_INPUTSEL_NEGSEL_APORT4XCH13 0x0000008DUL /**< Mode APORT4XCH13 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_NEGSEL_APORT4YCH14 0x0000008EUL /**< Mode APORT4YCH14 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_NEGSEL_APORT4XCH15 0x0000008FUL /**< Mode APORT4XCH15 for ACMP_INPUTSEL */
#define _ACMP_INPUTSEL_NEGSEL_APORT4YCH16 0x00000090UL /**< Mode APORT4YCH16 for ACMP_INPUTSEL */
#define _ACMP_INPUTSEL_NEGSEL_APORT4XCH17 0x00000091UL /**< Mode APORT4XCH17 for ACMP_INPUTSEL */
#define _ACMP_INPUTSEL_NEGSEL_APORT4YCH18 0x00000092UL /**< Mode APORT4YCH18 for ACMP_INPUTSEL */
@@ -678,8 +679,6 @@ typedef struct {
#define _ACMP_INPUTSEL_NEGSEL_APORT4YCH28 0x0000009CUL /**< Mode APORT4YCH28 for ACMP_INPUTSEL */
#define _ACMP_INPUTSEL_NEGSEL_APORT4XCH29 0x0000009DUL /**< Mode APORT4XCH29 for ACMP_INPUTSEL */
#define _ACMP_INPUTSEL_NEGSEL_APORT4YCH30 0x0000009EUL /**< Mode APORT4YCH30 for ACMP_INPUTSEL */
-#define _ACMP_INPUTSEL_NEGSEL_APORT4YCH14 0x0000009EUL /**< Mode APORT4YCH14 for ACMP_INPUTSEL */
-#define _ACMP_INPUTSEL_NEGSEL_APORT4XCH15 0x0000009FUL /**< Mode APORT4XCH15 for ACMP_INPUTSEL */
#define _ACMP_INPUTSEL_NEGSEL_APORT4XCH31 0x0000009FUL /**< Mode APORT4XCH31 for ACMP_INPUTSEL */
#define _ACMP_INPUTSEL_NEGSEL_DACOUT0 0x000000F2UL /**< Mode DACOUT0 for ACMP_INPUTSEL */
#define _ACMP_INPUTSEL_NEGSEL_DACOUT1 0x000000F3UL /**< Mode DACOUT1 for ACMP_INPUTSEL */
@@ -831,6 +830,8 @@ typedef struct {
#define ACMP_INPUTSEL_NEGSEL_APORT4XCH11 (_ACMP_INPUTSEL_NEGSEL_APORT4XCH11 << 8) /**< Shifted mode APORT4XCH11 for ACMP_INPUTSEL */
#define ACMP_INPUTSEL_NEGSEL_APORT4YCH12 (_ACMP_INPUTSEL_NEGSEL_APORT4YCH12 << 8) /**< Shifted mode APORT4YCH12 for ACMP_INPUTSEL */
#define ACMP_INPUTSEL_NEGSEL_APORT4XCH13 (_ACMP_INPUTSEL_NEGSEL_APORT4XCH13 << 8) /**< Shifted mode APORT4XCH13 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_NEGSEL_APORT4YCH14 (_ACMP_INPUTSEL_NEGSEL_APORT4YCH14 << 8) /**< Shifted mode APORT4YCH14 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_NEGSEL_APORT4XCH15 (_ACMP_INPUTSEL_NEGSEL_APORT4XCH15 << 8) /**< Shifted mode APORT4XCH15 for ACMP_INPUTSEL */
#define ACMP_INPUTSEL_NEGSEL_APORT4YCH16 (_ACMP_INPUTSEL_NEGSEL_APORT4YCH16 << 8) /**< Shifted mode APORT4YCH16 for ACMP_INPUTSEL */
#define ACMP_INPUTSEL_NEGSEL_APORT4XCH17 (_ACMP_INPUTSEL_NEGSEL_APORT4XCH17 << 8) /**< Shifted mode APORT4XCH17 for ACMP_INPUTSEL */
#define ACMP_INPUTSEL_NEGSEL_APORT4YCH18 (_ACMP_INPUTSEL_NEGSEL_APORT4YCH18 << 8) /**< Shifted mode APORT4YCH18 for ACMP_INPUTSEL */
@@ -846,8 +847,6 @@ typedef struct {
#define ACMP_INPUTSEL_NEGSEL_APORT4YCH28 (_ACMP_INPUTSEL_NEGSEL_APORT4YCH28 << 8) /**< Shifted mode APORT4YCH28 for ACMP_INPUTSEL */
#define ACMP_INPUTSEL_NEGSEL_APORT4XCH29 (_ACMP_INPUTSEL_NEGSEL_APORT4XCH29 << 8) /**< Shifted mode APORT4XCH29 for ACMP_INPUTSEL */
#define ACMP_INPUTSEL_NEGSEL_APORT4YCH30 (_ACMP_INPUTSEL_NEGSEL_APORT4YCH30 << 8) /**< Shifted mode APORT4YCH30 for ACMP_INPUTSEL */
-#define ACMP_INPUTSEL_NEGSEL_APORT4YCH14 (_ACMP_INPUTSEL_NEGSEL_APORT4YCH14 << 8) /**< Shifted mode APORT4YCH14 for ACMP_INPUTSEL */
-#define ACMP_INPUTSEL_NEGSEL_APORT4XCH15 (_ACMP_INPUTSEL_NEGSEL_APORT4XCH15 << 8) /**< Shifted mode APORT4XCH15 for ACMP_INPUTSEL */
#define ACMP_INPUTSEL_NEGSEL_APORT4XCH31 (_ACMP_INPUTSEL_NEGSEL_APORT4XCH31 << 8) /**< Shifted mode APORT4XCH31 for ACMP_INPUTSEL */
#define ACMP_INPUTSEL_NEGSEL_DACOUT0 (_ACMP_INPUTSEL_NEGSEL_DACOUT0 << 8) /**< Shifted mode DACOUT0 for ACMP_INPUTSEL */
#define ACMP_INPUTSEL_NEGSEL_DACOUT1 (_ACMP_INPUTSEL_NEGSEL_DACOUT1 << 8) /**< Shifted mode DACOUT1 for ACMP_INPUTSEL */
diff --git a/cpu/efm32/families/efr32mg12p/include/vendor/efr32mg12p_adc.h b/cpu/efm32/families/efr32mg12p/include/vendor/efr32mg12p_adc.h
index 7b8561619b..cafc65b947 100644
--- a/cpu/efm32/families/efr32mg12p/include/vendor/efr32mg12p_adc.h
+++ b/cpu/efm32/families/efr32mg12p/include/vendor/efr32mg12p_adc.h
@@ -1,10 +1,9 @@
/***************************************************************************//**
* @file
* @brief EFR32MG12P_ADC register and bit field definitions
- * @version 5.8.3
*******************************************************************************
* # License
- * Copyright 2019 Silicon Laboratories Inc. www.silabs.com
+ * Copyright 2020 Silicon Laboratories Inc. www.silabs.com
*******************************************************************************
*
* SPDX-License-Identifier: Zlib
@@ -1383,133 +1382,133 @@ typedef struct {
#define _ADC_SCANMASK_SCANINPUTEN_SHIFT 0 /**< Shift value for ADC_SCANINPUTEN */
#define _ADC_SCANMASK_SCANINPUTEN_MASK 0xFFFFFFFFUL /**< Bit mask for ADC_SCANINPUTEN */
#define _ADC_SCANMASK_SCANINPUTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SCANMASK */
-#define _ADC_SCANMASK_SCANINPUTEN_INPUT0INPUT0NEGSEL 0x00000001UL /**< Mode INPUT0INPUT0NEGSEL for ADC_SCANMASK */
#define _ADC_SCANMASK_SCANINPUTEN_INPUT0 0x00000001UL /**< Mode INPUT0 for ADC_SCANMASK */
-#define _ADC_SCANMASK_SCANINPUTEN_INPUT1 0x00000002UL /**< Mode INPUT1 for ADC_SCANMASK */
+#define _ADC_SCANMASK_SCANINPUTEN_INPUT0INPUT0NEGSEL 0x00000001UL /**< Mode INPUT0INPUT0NEGSEL for ADC_SCANMASK */
#define _ADC_SCANMASK_SCANINPUTEN_INPUT1INPUT2 0x00000002UL /**< Mode INPUT1INPUT2 for ADC_SCANMASK */
+#define _ADC_SCANMASK_SCANINPUTEN_INPUT1 0x00000002UL /**< Mode INPUT1 for ADC_SCANMASK */
#define _ADC_SCANMASK_SCANINPUTEN_INPUT2 0x00000004UL /**< Mode INPUT2 for ADC_SCANMASK */
#define _ADC_SCANMASK_SCANINPUTEN_INPUT2INPUT2NEGSEL 0x00000004UL /**< Mode INPUT2INPUT2NEGSEL for ADC_SCANMASK */
-#define _ADC_SCANMASK_SCANINPUTEN_INPUT3 0x00000008UL /**< Mode INPUT3 for ADC_SCANMASK */
#define _ADC_SCANMASK_SCANINPUTEN_INPUT3INPUT4 0x00000008UL /**< Mode INPUT3INPUT4 for ADC_SCANMASK */
-#define _ADC_SCANMASK_SCANINPUTEN_INPUT4 0x00000010UL /**< Mode INPUT4 for ADC_SCANMASK */
+#define _ADC_SCANMASK_SCANINPUTEN_INPUT3 0x00000008UL /**< Mode INPUT3 for ADC_SCANMASK */
#define _ADC_SCANMASK_SCANINPUTEN_INPUT4INPUT4NEGSEL 0x00000010UL /**< Mode INPUT4INPUT4NEGSEL for ADC_SCANMASK */
+#define _ADC_SCANMASK_SCANINPUTEN_INPUT4 0x00000010UL /**< Mode INPUT4 for ADC_SCANMASK */
#define _ADC_SCANMASK_SCANINPUTEN_INPUT5INPUT6 0x00000020UL /**< Mode INPUT5INPUT6 for ADC_SCANMASK */
#define _ADC_SCANMASK_SCANINPUTEN_INPUT5 0x00000020UL /**< Mode INPUT5 for ADC_SCANMASK */
-#define _ADC_SCANMASK_SCANINPUTEN_INPUT6INPUT6NEGSEL 0x00000040UL /**< Mode INPUT6INPUT6NEGSEL for ADC_SCANMASK */
#define _ADC_SCANMASK_SCANINPUTEN_INPUT6 0x00000040UL /**< Mode INPUT6 for ADC_SCANMASK */
-#define _ADC_SCANMASK_SCANINPUTEN_INPUT7 0x00000080UL /**< Mode INPUT7 for ADC_SCANMASK */
+#define _ADC_SCANMASK_SCANINPUTEN_INPUT6INPUT6NEGSEL 0x00000040UL /**< Mode INPUT6INPUT6NEGSEL for ADC_SCANMASK */
#define _ADC_SCANMASK_SCANINPUTEN_INPUT7INPUT0 0x00000080UL /**< Mode INPUT7INPUT0 for ADC_SCANMASK */
-#define _ADC_SCANMASK_SCANINPUTEN_INPUT8INPUT9 0x00000100UL /**< Mode INPUT8INPUT9 for ADC_SCANMASK */
+#define _ADC_SCANMASK_SCANINPUTEN_INPUT7 0x00000080UL /**< Mode INPUT7 for ADC_SCANMASK */
#define _ADC_SCANMASK_SCANINPUTEN_INPUT8 0x00000100UL /**< Mode INPUT8 for ADC_SCANMASK */
-#define _ADC_SCANMASK_SCANINPUTEN_INPUT9 0x00000200UL /**< Mode INPUT9 for ADC_SCANMASK */
+#define _ADC_SCANMASK_SCANINPUTEN_INPUT8INPUT9 0x00000100UL /**< Mode INPUT8INPUT9 for ADC_SCANMASK */
#define _ADC_SCANMASK_SCANINPUTEN_INPUT9INPUT9NEGSEL 0x00000200UL /**< Mode INPUT9INPUT9NEGSEL for ADC_SCANMASK */
-#define _ADC_SCANMASK_SCANINPUTEN_INPUT10INPUT11 0x00000400UL /**< Mode INPUT10INPUT11 for ADC_SCANMASK */
+#define _ADC_SCANMASK_SCANINPUTEN_INPUT9 0x00000200UL /**< Mode INPUT9 for ADC_SCANMASK */
#define _ADC_SCANMASK_SCANINPUTEN_INPUT10 0x00000400UL /**< Mode INPUT10 for ADC_SCANMASK */
-#define _ADC_SCANMASK_SCANINPUTEN_INPUT11INPUT11NEGSEL 0x00000800UL /**< Mode INPUT11INPUT11NEGSEL for ADC_SCANMASK */
+#define _ADC_SCANMASK_SCANINPUTEN_INPUT10INPUT11 0x00000400UL /**< Mode INPUT10INPUT11 for ADC_SCANMASK */
#define _ADC_SCANMASK_SCANINPUTEN_INPUT11 0x00000800UL /**< Mode INPUT11 for ADC_SCANMASK */
-#define _ADC_SCANMASK_SCANINPUTEN_INPUT12INPUT13 0x00001000UL /**< Mode INPUT12INPUT13 for ADC_SCANMASK */
+#define _ADC_SCANMASK_SCANINPUTEN_INPUT11INPUT11NEGSEL 0x00000800UL /**< Mode INPUT11INPUT11NEGSEL for ADC_SCANMASK */
#define _ADC_SCANMASK_SCANINPUTEN_INPUT12 0x00001000UL /**< Mode INPUT12 for ADC_SCANMASK */
-#define _ADC_SCANMASK_SCANINPUTEN_INPUT13INPUT13NEGSEL 0x00002000UL /**< Mode INPUT13INPUT13NEGSEL for ADC_SCANMASK */
+#define _ADC_SCANMASK_SCANINPUTEN_INPUT12INPUT13 0x00001000UL /**< Mode INPUT12INPUT13 for ADC_SCANMASK */
#define _ADC_SCANMASK_SCANINPUTEN_INPUT13 0x00002000UL /**< Mode INPUT13 for ADC_SCANMASK */
-#define _ADC_SCANMASK_SCANINPUTEN_INPUT14INPUT15 0x00004000UL /**< Mode INPUT14INPUT15 for ADC_SCANMASK */
+#define _ADC_SCANMASK_SCANINPUTEN_INPUT13INPUT13NEGSEL 0x00002000UL /**< Mode INPUT13INPUT13NEGSEL for ADC_SCANMASK */
#define _ADC_SCANMASK_SCANINPUTEN_INPUT14 0x00004000UL /**< Mode INPUT14 for ADC_SCANMASK */
-#define _ADC_SCANMASK_SCANINPUTEN_INPUT15INPUT15NEGSEL 0x00008000UL /**< Mode INPUT15INPUT15NEGSEL for ADC_SCANMASK */
+#define _ADC_SCANMASK_SCANINPUTEN_INPUT14INPUT15 0x00004000UL /**< Mode INPUT14INPUT15 for ADC_SCANMASK */
#define _ADC_SCANMASK_SCANINPUTEN_INPUT15 0x00008000UL /**< Mode INPUT15 for ADC_SCANMASK */
-#define _ADC_SCANMASK_SCANINPUTEN_INPUT16INPUT17 0x00010000UL /**< Mode INPUT16INPUT17 for ADC_SCANMASK */
+#define _ADC_SCANMASK_SCANINPUTEN_INPUT15INPUT15NEGSEL 0x00008000UL /**< Mode INPUT15INPUT15NEGSEL for ADC_SCANMASK */
#define _ADC_SCANMASK_SCANINPUTEN_INPUT16 0x00010000UL /**< Mode INPUT16 for ADC_SCANMASK */
-#define _ADC_SCANMASK_SCANINPUTEN_INPUT17INPUT18 0x00020000UL /**< Mode INPUT17INPUT18 for ADC_SCANMASK */
+#define _ADC_SCANMASK_SCANINPUTEN_INPUT16INPUT17 0x00010000UL /**< Mode INPUT16INPUT17 for ADC_SCANMASK */
#define _ADC_SCANMASK_SCANINPUTEN_INPUT17 0x00020000UL /**< Mode INPUT17 for ADC_SCANMASK */
+#define _ADC_SCANMASK_SCANINPUTEN_INPUT17INPUT18 0x00020000UL /**< Mode INPUT17INPUT18 for ADC_SCANMASK */
#define _ADC_SCANMASK_SCANINPUTEN_INPUT18INPUT19 0x00040000UL /**< Mode INPUT18INPUT19 for ADC_SCANMASK */
#define _ADC_SCANMASK_SCANINPUTEN_INPUT18 0x00040000UL /**< Mode INPUT18 for ADC_SCANMASK */
#define _ADC_SCANMASK_SCANINPUTEN_INPUT19 0x00080000UL /**< Mode INPUT19 for ADC_SCANMASK */
#define _ADC_SCANMASK_SCANINPUTEN_INPUT19INPUT20 0x00080000UL /**< Mode INPUT19INPUT20 for ADC_SCANMASK */
#define _ADC_SCANMASK_SCANINPUTEN_INPUT20INPUT21 0x00100000UL /**< Mode INPUT20INPUT21 for ADC_SCANMASK */
#define _ADC_SCANMASK_SCANINPUTEN_INPUT20 0x00100000UL /**< Mode INPUT20 for ADC_SCANMASK */
-#define _ADC_SCANMASK_SCANINPUTEN_INPUT21 0x00200000UL /**< Mode INPUT21 for ADC_SCANMASK */
#define _ADC_SCANMASK_SCANINPUTEN_INPUT21INPUT22 0x00200000UL /**< Mode INPUT21INPUT22 for ADC_SCANMASK */
+#define _ADC_SCANMASK_SCANINPUTEN_INPUT21 0x00200000UL /**< Mode INPUT21 for ADC_SCANMASK */
#define _ADC_SCANMASK_SCANINPUTEN_INPUT22INPUT23 0x00400000UL /**< Mode INPUT22INPUT23 for ADC_SCANMASK */
#define _ADC_SCANMASK_SCANINPUTEN_INPUT22 0x00400000UL /**< Mode INPUT22 for ADC_SCANMASK */
-#define _ADC_SCANMASK_SCANINPUTEN_INPUT23INPUT16 0x00800000UL /**< Mode INPUT23INPUT16 for ADC_SCANMASK */
#define _ADC_SCANMASK_SCANINPUTEN_INPUT23 0x00800000UL /**< Mode INPUT23 for ADC_SCANMASK */
-#define _ADC_SCANMASK_SCANINPUTEN_INPUT24 0x01000000UL /**< Mode INPUT24 for ADC_SCANMASK */
+#define _ADC_SCANMASK_SCANINPUTEN_INPUT23INPUT16 0x00800000UL /**< Mode INPUT23INPUT16 for ADC_SCANMASK */
#define _ADC_SCANMASK_SCANINPUTEN_INPUT24INPUT25 0x01000000UL /**< Mode INPUT24INPUT25 for ADC_SCANMASK */
-#define _ADC_SCANMASK_SCANINPUTEN_INPUT25INPUT26 0x02000000UL /**< Mode INPUT25INPUT26 for ADC_SCANMASK */
+#define _ADC_SCANMASK_SCANINPUTEN_INPUT24 0x01000000UL /**< Mode INPUT24 for ADC_SCANMASK */
#define _ADC_SCANMASK_SCANINPUTEN_INPUT25 0x02000000UL /**< Mode INPUT25 for ADC_SCANMASK */
-#define _ADC_SCANMASK_SCANINPUTEN_INPUT26 0x04000000UL /**< Mode INPUT26 for ADC_SCANMASK */
+#define _ADC_SCANMASK_SCANINPUTEN_INPUT25INPUT26 0x02000000UL /**< Mode INPUT25INPUT26 for ADC_SCANMASK */
#define _ADC_SCANMASK_SCANINPUTEN_INPUT26INPUT27 0x04000000UL /**< Mode INPUT26INPUT27 for ADC_SCANMASK */
-#define _ADC_SCANMASK_SCANINPUTEN_INPUT27INPUT28 0x08000000UL /**< Mode INPUT27INPUT28 for ADC_SCANMASK */
+#define _ADC_SCANMASK_SCANINPUTEN_INPUT26 0x04000000UL /**< Mode INPUT26 for ADC_SCANMASK */
#define _ADC_SCANMASK_SCANINPUTEN_INPUT27 0x08000000UL /**< Mode INPUT27 for ADC_SCANMASK */
-#define _ADC_SCANMASK_SCANINPUTEN_INPUT28INPUT29 0x10000000UL /**< Mode INPUT28INPUT29 for ADC_SCANMASK */
+#define _ADC_SCANMASK_SCANINPUTEN_INPUT27INPUT28 0x08000000UL /**< Mode INPUT27INPUT28 for ADC_SCANMASK */
#define _ADC_SCANMASK_SCANINPUTEN_INPUT28 0x10000000UL /**< Mode INPUT28 for ADC_SCANMASK */
+#define _ADC_SCANMASK_SCANINPUTEN_INPUT28INPUT29 0x10000000UL /**< Mode INPUT28INPUT29 for ADC_SCANMASK */
#define _ADC_SCANMASK_SCANINPUTEN_INPUT29 0x20000000UL /**< Mode INPUT29 for ADC_SCANMASK */
#define _ADC_SCANMASK_SCANINPUTEN_INPUT29INPUT30 0x20000000UL /**< Mode INPUT29INPUT30 for ADC_SCANMASK */
-#define _ADC_SCANMASK_SCANINPUTEN_INPUT30 0x40000000UL /**< Mode INPUT30 for ADC_SCANMASK */
#define _ADC_SCANMASK_SCANINPUTEN_INPUT30INPUT31 0x40000000UL /**< Mode INPUT30INPUT31 for ADC_SCANMASK */
+#define _ADC_SCANMASK_SCANINPUTEN_INPUT30 0x40000000UL /**< Mode INPUT30 for ADC_SCANMASK */
#define _ADC_SCANMASK_SCANINPUTEN_INPUT31INPUT24 0x80000000UL /**< Mode INPUT31INPUT24 for ADC_SCANMASK */
#define _ADC_SCANMASK_SCANINPUTEN_INPUT31 0x80000000UL /**< Mode INPUT31 for ADC_SCANMASK */
#define ADC_SCANMASK_SCANINPUTEN_DEFAULT (_ADC_SCANMASK_SCANINPUTEN_DEFAULT << 0) /**< Shifted mode DEFAULT for ADC_SCANMASK */
-#define ADC_SCANMASK_SCANINPUTEN_INPUT0INPUT0NEGSEL (_ADC_SCANMASK_SCANINPUTEN_INPUT0INPUT0NEGSEL << 0) /**< Shifted mode INPUT0INPUT0NEGSEL for ADC_SCANMASK */
#define ADC_SCANMASK_SCANINPUTEN_INPUT0 (_ADC_SCANMASK_SCANINPUTEN_INPUT0 << 0) /**< Shifted mode INPUT0 for ADC_SCANMASK */
-#define ADC_SCANMASK_SCANINPUTEN_INPUT1 (_ADC_SCANMASK_SCANINPUTEN_INPUT1 << 0) /**< Shifted mode INPUT1 for ADC_SCANMASK */
+#define ADC_SCANMASK_SCANINPUTEN_INPUT0INPUT0NEGSEL (_ADC_SCANMASK_SCANINPUTEN_INPUT0INPUT0NEGSEL << 0) /**< Shifted mode INPUT0INPUT0NEGSEL for ADC_SCANMASK */
#define ADC_SCANMASK_SCANINPUTEN_INPUT1INPUT2 (_ADC_SCANMASK_SCANINPUTEN_INPUT1INPUT2 << 0) /**< Shifted mode INPUT1INPUT2 for ADC_SCANMASK */
+#define ADC_SCANMASK_SCANINPUTEN_INPUT1 (_ADC_SCANMASK_SCANINPUTEN_INPUT1 << 0) /**< Shifted mode INPUT1 for ADC_SCANMASK */
#define ADC_SCANMASK_SCANINPUTEN_INPUT2 (_ADC_SCANMASK_SCANINPUTEN_INPUT2 << 0) /**< Shifted mode INPUT2 for ADC_SCANMASK */
#define ADC_SCANMASK_SCANINPUTEN_INPUT2INPUT2NEGSEL (_ADC_SCANMASK_SCANINPUTEN_INPUT2INPUT2NEGSEL << 0) /**< Shifted mode INPUT2INPUT2NEGSEL for ADC_SCANMASK */
-#define ADC_SCANMASK_SCANINPUTEN_INPUT3 (_ADC_SCANMASK_SCANINPUTEN_INPUT3 << 0) /**< Shifted mode INPUT3 for ADC_SCANMASK */
#define ADC_SCANMASK_SCANINPUTEN_INPUT3INPUT4 (_ADC_SCANMASK_SCANINPUTEN_INPUT3INPUT4 << 0) /**< Shifted mode INPUT3INPUT4 for ADC_SCANMASK */
-#define ADC_SCANMASK_SCANINPUTEN_INPUT4 (_ADC_SCANMASK_SCANINPUTEN_INPUT4 << 0) /**< Shifted mode INPUT4 for ADC_SCANMASK */
+#define ADC_SCANMASK_SCANINPUTEN_INPUT3 (_ADC_SCANMASK_SCANINPUTEN_INPUT3 << 0) /**< Shifted mode INPUT3 for ADC_SCANMASK */
#define ADC_SCANMASK_SCANINPUTEN_INPUT4INPUT4NEGSEL (_ADC_SCANMASK_SCANINPUTEN_INPUT4INPUT4NEGSEL << 0) /**< Shifted mode INPUT4INPUT4NEGSEL for ADC_SCANMASK */
+#define ADC_SCANMASK_SCANINPUTEN_INPUT4 (_ADC_SCANMASK_SCANINPUTEN_INPUT4 << 0) /**< Shifted mode INPUT4 for ADC_SCANMASK */
#define ADC_SCANMASK_SCANINPUTEN_INPUT5INPUT6 (_ADC_SCANMASK_SCANINPUTEN_INPUT5INPUT6 << 0) /**< Shifted mode INPUT5INPUT6 for ADC_SCANMASK */
#define ADC_SCANMASK_SCANINPUTEN_INPUT5 (_ADC_SCANMASK_SCANINPUTEN_INPUT5 << 0) /**< Shifted mode INPUT5 for ADC_SCANMASK */
-#define ADC_SCANMASK_SCANINPUTEN_INPUT6INPUT6NEGSEL (_ADC_SCANMASK_SCANINPUTEN_INPUT6INPUT6NEGSEL << 0) /**< Shifted mode INPUT6INPUT6NEGSEL for ADC_SCANMASK */
#define ADC_SCANMASK_SCANINPUTEN_INPUT6 (_ADC_SCANMASK_SCANINPUTEN_INPUT6 << 0) /**< Shifted mode INPUT6 for ADC_SCANMASK */
-#define ADC_SCANMASK_SCANINPUTEN_INPUT7 (_ADC_SCANMASK_SCANINPUTEN_INPUT7 << 0) /**< Shifted mode INPUT7 for ADC_SCANMASK */
+#define ADC_SCANMASK_SCANINPUTEN_INPUT6INPUT6NEGSEL (_ADC_SCANMASK_SCANINPUTEN_INPUT6INPUT6NEGSEL << 0) /**< Shifted mode INPUT6INPUT6NEGSEL for ADC_SCANMASK */
#define ADC_SCANMASK_SCANINPUTEN_INPUT7INPUT0 (_ADC_SCANMASK_SCANINPUTEN_INPUT7INPUT0 << 0) /**< Shifted mode INPUT7INPUT0 for ADC_SCANMASK */
-#define ADC_SCANMASK_SCANINPUTEN_INPUT8INPUT9 (_ADC_SCANMASK_SCANINPUTEN_INPUT8INPUT9 << 0) /**< Shifted mode INPUT8INPUT9 for ADC_SCANMASK */
+#define ADC_SCANMASK_SCANINPUTEN_INPUT7 (_ADC_SCANMASK_SCANINPUTEN_INPUT7 << 0) /**< Shifted mode INPUT7 for ADC_SCANMASK */
#define ADC_SCANMASK_SCANINPUTEN_INPUT8 (_ADC_SCANMASK_SCANINPUTEN_INPUT8 << 0) /**< Shifted mode INPUT8 for ADC_SCANMASK */
-#define ADC_SCANMASK_SCANINPUTEN_INPUT9 (_ADC_SCANMASK_SCANINPUTEN_INPUT9 << 0) /**< Shifted mode INPUT9 for ADC_SCANMASK */
+#define ADC_SCANMASK_SCANINPUTEN_INPUT8INPUT9 (_ADC_SCANMASK_SCANINPUTEN_INPUT8INPUT9 << 0) /**< Shifted mode INPUT8INPUT9 for ADC_SCANMASK */
#define ADC_SCANMASK_SCANINPUTEN_INPUT9INPUT9NEGSEL (_ADC_SCANMASK_SCANINPUTEN_INPUT9INPUT9NEGSEL << 0) /**< Shifted mode INPUT9INPUT9NEGSEL for ADC_SCANMASK */
-#define ADC_SCANMASK_SCANINPUTEN_INPUT10INPUT11 (_ADC_SCANMASK_SCANINPUTEN_INPUT10INPUT11 << 0) /**< Shifted mode INPUT10INPUT11 for ADC_SCANMASK */
+#define ADC_SCANMASK_SCANINPUTEN_INPUT9 (_ADC_SCANMASK_SCANINPUTEN_INPUT9 << 0) /**< Shifted mode INPUT9 for ADC_SCANMASK */
#define ADC_SCANMASK_SCANINPUTEN_INPUT10 (_ADC_SCANMASK_SCANINPUTEN_INPUT10 << 0) /**< Shifted mode INPUT10 for ADC_SCANMASK */
-#define ADC_SCANMASK_SCANINPUTEN_INPUT11INPUT11NEGSEL (_ADC_SCANMASK_SCANINPUTEN_INPUT11INPUT11NEGSEL << 0) /**< Shifted mode INPUT11INPUT11NEGSEL for ADC_SCANMASK */
+#define ADC_SCANMASK_SCANINPUTEN_INPUT10INPUT11 (_ADC_SCANMASK_SCANINPUTEN_INPUT10INPUT11 << 0) /**< Shifted mode INPUT10INPUT11 for ADC_SCANMASK */
#define ADC_SCANMASK_SCANINPUTEN_INPUT11 (_ADC_SCANMASK_SCANINPUTEN_INPUT11 << 0) /**< Shifted mode INPUT11 for ADC_SCANMASK */
-#define ADC_SCANMASK_SCANINPUTEN_INPUT12INPUT13 (_ADC_SCANMASK_SCANINPUTEN_INPUT12INPUT13 << 0) /**< Shifted mode INPUT12INPUT13 for ADC_SCANMASK */
+#define ADC_SCANMASK_SCANINPUTEN_INPUT11INPUT11NEGSEL (_ADC_SCANMASK_SCANINPUTEN_INPUT11INPUT11NEGSEL << 0) /**< Shifted mode INPUT11INPUT11NEGSEL for ADC_SCANMASK */
#define ADC_SCANMASK_SCANINPUTEN_INPUT12 (_ADC_SCANMASK_SCANINPUTEN_INPUT12 << 0) /**< Shifted mode INPUT12 for ADC_SCANMASK */
-#define ADC_SCANMASK_SCANINPUTEN_INPUT13INPUT13NEGSEL (_ADC_SCANMASK_SCANINPUTEN_INPUT13INPUT13NEGSEL << 0) /**< Shifted mode INPUT13INPUT13NEGSEL for ADC_SCANMASK */
+#define ADC_SCANMASK_SCANINPUTEN_INPUT12INPUT13 (_ADC_SCANMASK_SCANINPUTEN_INPUT12INPUT13 << 0) /**< Shifted mode INPUT12INPUT13 for ADC_SCANMASK */
#define ADC_SCANMASK_SCANINPUTEN_INPUT13 (_ADC_SCANMASK_SCANINPUTEN_INPUT13 << 0) /**< Shifted mode INPUT13 for ADC_SCANMASK */
-#define ADC_SCANMASK_SCANINPUTEN_INPUT14INPUT15 (_ADC_SCANMASK_SCANINPUTEN_INPUT14INPUT15 << 0) /**< Shifted mode INPUT14INPUT15 for ADC_SCANMASK */
+#define ADC_SCANMASK_SCANINPUTEN_INPUT13INPUT13NEGSEL (_ADC_SCANMASK_SCANINPUTEN_INPUT13INPUT13NEGSEL << 0) /**< Shifted mode INPUT13INPUT13NEGSEL for ADC_SCANMASK */
#define ADC_SCANMASK_SCANINPUTEN_INPUT14 (_ADC_SCANMASK_SCANINPUTEN_INPUT14 << 0) /**< Shifted mode INPUT14 for ADC_SCANMASK */
-#define ADC_SCANMASK_SCANINPUTEN_INPUT15INPUT15NEGSEL (_ADC_SCANMASK_SCANINPUTEN_INPUT15INPUT15NEGSEL << 0) /**< Shifted mode INPUT15INPUT15NEGSEL for ADC_SCANMASK */
+#define ADC_SCANMASK_SCANINPUTEN_INPUT14INPUT15 (_ADC_SCANMASK_SCANINPUTEN_INPUT14INPUT15 << 0) /**< Shifted mode INPUT14INPUT15 for ADC_SCANMASK */
#define ADC_SCANMASK_SCANINPUTEN_INPUT15 (_ADC_SCANMASK_SCANINPUTEN_INPUT15 << 0) /**< Shifted mode INPUT15 for ADC_SCANMASK */
-#define ADC_SCANMASK_SCANINPUTEN_INPUT16INPUT17 (_ADC_SCANMASK_SCANINPUTEN_INPUT16INPUT17 << 0) /**< Shifted mode INPUT16INPUT17 for ADC_SCANMASK */
+#define ADC_SCANMASK_SCANINPUTEN_INPUT15INPUT15NEGSEL (_ADC_SCANMASK_SCANINPUTEN_INPUT15INPUT15NEGSEL << 0) /**< Shifted mode INPUT15INPUT15NEGSEL for ADC_SCANMASK */
#define ADC_SCANMASK_SCANINPUTEN_INPUT16 (_ADC_SCANMASK_SCANINPUTEN_INPUT16 << 0) /**< Shifted mode INPUT16 for ADC_SCANMASK */
-#define ADC_SCANMASK_SCANINPUTEN_INPUT17INPUT18 (_ADC_SCANMASK_SCANINPUTEN_INPUT17INPUT18 << 0) /**< Shifted mode INPUT17INPUT18 for ADC_SCANMASK */
+#define ADC_SCANMASK_SCANINPUTEN_INPUT16INPUT17 (_ADC_SCANMASK_SCANINPUTEN_INPUT16INPUT17 << 0) /**< Shifted mode INPUT16INPUT17 for ADC_SCANMASK */
#define ADC_SCANMASK_SCANINPUTEN_INPUT17 (_ADC_SCANMASK_SCANINPUTEN_INPUT17 << 0) /**< Shifted mode INPUT17 for ADC_SCANMASK */
+#define ADC_SCANMASK_SCANINPUTEN_INPUT17INPUT18 (_ADC_SCANMASK_SCANINPUTEN_INPUT17INPUT18 << 0) /**< Shifted mode INPUT17INPUT18 for ADC_SCANMASK */
#define ADC_SCANMASK_SCANINPUTEN_INPUT18INPUT19 (_ADC_SCANMASK_SCANINPUTEN_INPUT18INPUT19 << 0) /**< Shifted mode INPUT18INPUT19 for ADC_SCANMASK */
#define ADC_SCANMASK_SCANINPUTEN_INPUT18 (_ADC_SCANMASK_SCANINPUTEN_INPUT18 << 0) /**< Shifted mode INPUT18 for ADC_SCANMASK */
#define ADC_SCANMASK_SCANINPUTEN_INPUT19 (_ADC_SCANMASK_SCANINPUTEN_INPUT19 << 0) /**< Shifted mode INPUT19 for ADC_SCANMASK */
#define ADC_SCANMASK_SCANINPUTEN_INPUT19INPUT20 (_ADC_SCANMASK_SCANINPUTEN_INPUT19INPUT20 << 0) /**< Shifted mode INPUT19INPUT20 for ADC_SCANMASK */
#define ADC_SCANMASK_SCANINPUTEN_INPUT20INPUT21 (_ADC_SCANMASK_SCANINPUTEN_INPUT20INPUT21 << 0) /**< Shifted mode INPUT20INPUT21 for ADC_SCANMASK */
#define ADC_SCANMASK_SCANINPUTEN_INPUT20 (_ADC_SCANMASK_SCANINPUTEN_INPUT20 << 0) /**< Shifted mode INPUT20 for ADC_SCANMASK */
-#define ADC_SCANMASK_SCANINPUTEN_INPUT21 (_ADC_SCANMASK_SCANINPUTEN_INPUT21 << 0) /**< Shifted mode INPUT21 for ADC_SCANMASK */
#define ADC_SCANMASK_SCANINPUTEN_INPUT21INPUT22 (_ADC_SCANMASK_SCANINPUTEN_INPUT21INPUT22 << 0) /**< Shifted mode INPUT21INPUT22 for ADC_SCANMASK */
+#define ADC_SCANMASK_SCANINPUTEN_INPUT21 (_ADC_SCANMASK_SCANINPUTEN_INPUT21 << 0) /**< Shifted mode INPUT21 for ADC_SCANMASK */
#define ADC_SCANMASK_SCANINPUTEN_INPUT22INPUT23 (_ADC_SCANMASK_SCANINPUTEN_INPUT22INPUT23 << 0) /**< Shifted mode INPUT22INPUT23 for ADC_SCANMASK */
#define ADC_SCANMASK_SCANINPUTEN_INPUT22 (_ADC_SCANMASK_SCANINPUTEN_INPUT22 << 0) /**< Shifted mode INPUT22 for ADC_SCANMASK */
-#define ADC_SCANMASK_SCANINPUTEN_INPUT23INPUT16 (_ADC_SCANMASK_SCANINPUTEN_INPUT23INPUT16 << 0) /**< Shifted mode INPUT23INPUT16 for ADC_SCANMASK */
#define ADC_SCANMASK_SCANINPUTEN_INPUT23 (_ADC_SCANMASK_SCANINPUTEN_INPUT23 << 0) /**< Shifted mode INPUT23 for ADC_SCANMASK */
-#define ADC_SCANMASK_SCANINPUTEN_INPUT24 (_ADC_SCANMASK_SCANINPUTEN_INPUT24 << 0) /**< Shifted mode INPUT24 for ADC_SCANMASK */
+#define ADC_SCANMASK_SCANINPUTEN_INPUT23INPUT16 (_ADC_SCANMASK_SCANINPUTEN_INPUT23INPUT16 << 0) /**< Shifted mode INPUT23INPUT16 for ADC_SCANMASK */
#define ADC_SCANMASK_SCANINPUTEN_INPUT24INPUT25 (_ADC_SCANMASK_SCANINPUTEN_INPUT24INPUT25 << 0) /**< Shifted mode INPUT24INPUT25 for ADC_SCANMASK */
-#define ADC_SCANMASK_SCANINPUTEN_INPUT25INPUT26 (_ADC_SCANMASK_SCANINPUTEN_INPUT25INPUT26 << 0) /**< Shifted mode INPUT25INPUT26 for ADC_SCANMASK */
+#define ADC_SCANMASK_SCANINPUTEN_INPUT24 (_ADC_SCANMASK_SCANINPUTEN_INPUT24 << 0) /**< Shifted mode INPUT24 for ADC_SCANMASK */
#define ADC_SCANMASK_SCANINPUTEN_INPUT25 (_ADC_SCANMASK_SCANINPUTEN_INPUT25 << 0) /**< Shifted mode INPUT25 for ADC_SCANMASK */
-#define ADC_SCANMASK_SCANINPUTEN_INPUT26 (_ADC_SCANMASK_SCANINPUTEN_INPUT26 << 0) /**< Shifted mode INPUT26 for ADC_SCANMASK */
+#define ADC_SCANMASK_SCANINPUTEN_INPUT25INPUT26 (_ADC_SCANMASK_SCANINPUTEN_INPUT25INPUT26 << 0) /**< Shifted mode INPUT25INPUT26 for ADC_SCANMASK */
#define ADC_SCANMASK_SCANINPUTEN_INPUT26INPUT27 (_ADC_SCANMASK_SCANINPUTEN_INPUT26INPUT27 << 0) /**< Shifted mode INPUT26INPUT27 for ADC_SCANMASK */
-#define ADC_SCANMASK_SCANINPUTEN_INPUT27INPUT28 (_ADC_SCANMASK_SCANINPUTEN_INPUT27INPUT28 << 0) /**< Shifted mode INPUT27INPUT28 for ADC_SCANMASK */
+#define ADC_SCANMASK_SCANINPUTEN_INPUT26 (_ADC_SCANMASK_SCANINPUTEN_INPUT26 << 0) /**< Shifted mode INPUT26 for ADC_SCANMASK */
#define ADC_SCANMASK_SCANINPUTEN_INPUT27 (_ADC_SCANMASK_SCANINPUTEN_INPUT27 << 0) /**< Shifted mode INPUT27 for ADC_SCANMASK */
-#define ADC_SCANMASK_SCANINPUTEN_INPUT28INPUT29 (_ADC_SCANMASK_SCANINPUTEN_INPUT28INPUT29 << 0) /**< Shifted mode INPUT28INPUT29 for ADC_SCANMASK */
+#define ADC_SCANMASK_SCANINPUTEN_INPUT27INPUT28 (_ADC_SCANMASK_SCANINPUTEN_INPUT27INPUT28 << 0) /**< Shifted mode INPUT27INPUT28 for ADC_SCANMASK */
#define ADC_SCANMASK_SCANINPUTEN_INPUT28 (_ADC_SCANMASK_SCANINPUTEN_INPUT28 << 0) /**< Shifted mode INPUT28 for ADC_SCANMASK */
+#define ADC_SCANMASK_SCANINPUTEN_INPUT28INPUT29 (_ADC_SCANMASK_SCANINPUTEN_INPUT28INPUT29 << 0) /**< Shifted mode INPUT28INPUT29 for ADC_SCANMASK */
#define ADC_SCANMASK_SCANINPUTEN_INPUT29 (_ADC_SCANMASK_SCANINPUTEN_INPUT29 << 0) /**< Shifted mode INPUT29 for ADC_SCANMASK */
#define ADC_SCANMASK_SCANINPUTEN_INPUT29INPUT30 (_ADC_SCANMASK_SCANINPUTEN_INPUT29INPUT30 << 0) /**< Shifted mode INPUT29INPUT30 for ADC_SCANMASK */
-#define ADC_SCANMASK_SCANINPUTEN_INPUT30 (_ADC_SCANMASK_SCANINPUTEN_INPUT30 << 0) /**< Shifted mode INPUT30 for ADC_SCANMASK */
#define ADC_SCANMASK_SCANINPUTEN_INPUT30INPUT31 (_ADC_SCANMASK_SCANINPUTEN_INPUT30INPUT31 << 0) /**< Shifted mode INPUT30INPUT31 for ADC_SCANMASK */
+#define ADC_SCANMASK_SCANINPUTEN_INPUT30 (_ADC_SCANMASK_SCANINPUTEN_INPUT30 << 0) /**< Shifted mode INPUT30 for ADC_SCANMASK */
#define ADC_SCANMASK_SCANINPUTEN_INPUT31INPUT24 (_ADC_SCANMASK_SCANINPUTEN_INPUT31INPUT24 << 0) /**< Shifted mode INPUT31INPUT24 for ADC_SCANMASK */
#define ADC_SCANMASK_SCANINPUTEN_INPUT31 (_ADC_SCANMASK_SCANINPUTEN_INPUT31 << 0) /**< Shifted mode INPUT31 for ADC_SCANMASK */
diff --git a/cpu/efm32/families/efr32mg12p/include/vendor/efr32mg12p_af_pins.h b/cpu/efm32/families/efr32mg12p/include/vendor/efr32mg12p_af_pins.h
index 3503e8101c..82bb1be182 100644
--- a/cpu/efm32/families/efr32mg12p/include/vendor/efr32mg12p_af_pins.h
+++ b/cpu/efm32/families/efr32mg12p/include/vendor/efr32mg12p_af_pins.h
@@ -1,10 +1,9 @@
/***************************************************************************//**
* @file
* @brief EFR32MG12P_AF_PINS register and bit field definitions
- * @version 5.8.3
*******************************************************************************
* # License
- * Copyright 2019 Silicon Laboratories Inc. www.silabs.com
+ * Copyright 2020 Silicon Laboratories Inc. www.silabs.com
*******************************************************************************
*
* SPDX-License-Identifier: Zlib
diff --git a/cpu/efm32/families/efr32mg12p/include/vendor/efr32mg12p_af_ports.h b/cpu/efm32/families/efr32mg12p/include/vendor/efr32mg12p_af_ports.h
index 9cd3c1985f..bff634fed6 100644
--- a/cpu/efm32/families/efr32mg12p/include/vendor/efr32mg12p_af_ports.h
+++ b/cpu/efm32/families/efr32mg12p/include/vendor/efr32mg12p_af_ports.h
@@ -1,10 +1,9 @@
/***************************************************************************//**
* @file
* @brief EFR32MG12P_AF_PORTS register and bit field definitions
- * @version 5.8.3
*******************************************************************************
* # License
- * Copyright 2019 Silicon Laboratories Inc. www.silabs.com
+ * Copyright 2020 Silicon Laboratories Inc. www.silabs.com
*******************************************************************************
*
* SPDX-License-Identifier: Zlib
diff --git a/cpu/efm32/families/efr32mg12p/include/vendor/efr32mg12p_cmu.h b/cpu/efm32/families/efr32mg12p/include/vendor/efr32mg12p_cmu.h
index a968208af3..6659a6a7a1 100644
--- a/cpu/efm32/families/efr32mg12p/include/vendor/efr32mg12p_cmu.h
+++ b/cpu/efm32/families/efr32mg12p/include/vendor/efr32mg12p_cmu.h
@@ -1,10 +1,9 @@
/***************************************************************************//**
* @file
* @brief EFR32MG12P_CMU register and bit field definitions
- * @version 5.8.3
*******************************************************************************
* # License
- * Copyright 2019 Silicon Laboratories Inc. www.silabs.com
+ * Copyright 2020 Silicon Laboratories Inc. www.silabs.com
*******************************************************************************
*
* SPDX-License-Identifier: Zlib
@@ -2018,13 +2017,13 @@ typedef struct {
#define _CMU_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for CMU_LOCKKEY */
#define _CMU_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for CMU_LOCKKEY */
#define _CMU_LOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LOCK */
-#define _CMU_LOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for CMU_LOCK */
#define _CMU_LOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for CMU_LOCK */
+#define _CMU_LOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for CMU_LOCK */
#define _CMU_LOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for CMU_LOCK */
#define _CMU_LOCK_LOCKKEY_UNLOCK 0x0000580EUL /**< Mode UNLOCK for CMU_LOCK */
#define CMU_LOCK_LOCKKEY_DEFAULT (_CMU_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LOCK */
-#define CMU_LOCK_LOCKKEY_LOCK (_CMU_LOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for CMU_LOCK */
#define CMU_LOCK_LOCKKEY_UNLOCKED (_CMU_LOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for CMU_LOCK */
+#define CMU_LOCK_LOCKKEY_LOCK (_CMU_LOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for CMU_LOCK */
#define CMU_LOCK_LOCKKEY_LOCKED (_CMU_LOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for CMU_LOCK */
#define CMU_LOCK_LOCKKEY_UNLOCK (_CMU_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for CMU_LOCK */
diff --git a/cpu/efm32/families/efr32mg12p/include/vendor/efr32mg12p_cryotimer.h b/cpu/efm32/families/efr32mg12p/include/vendor/efr32mg12p_cryotimer.h
index 75079c701e..c9547600ee 100644
--- a/cpu/efm32/families/efr32mg12p/include/vendor/efr32mg12p_cryotimer.h
+++ b/cpu/efm32/families/efr32mg12p/include/vendor/efr32mg12p_cryotimer.h
@@ -1,10 +1,9 @@
/***************************************************************************//**
* @file
* @brief EFR32MG12P_CRYOTIMER register and bit field definitions
- * @version 5.8.3
*******************************************************************************
* # License
- * Copyright 2019 Silicon Laboratories Inc. www.silabs.com
+ * Copyright 2020 Silicon Laboratories Inc. www.silabs.com
*******************************************************************************
*
* SPDX-License-Identifier: Zlib
diff --git a/cpu/efm32/families/efr32mg12p/include/vendor/efr32mg12p_crypto.h b/cpu/efm32/families/efr32mg12p/include/vendor/efr32mg12p_crypto.h
index c87cf08037..e28d25c56a 100644
--- a/cpu/efm32/families/efr32mg12p/include/vendor/efr32mg12p_crypto.h
+++ b/cpu/efm32/families/efr32mg12p/include/vendor/efr32mg12p_crypto.h
@@ -1,10 +1,9 @@
/***************************************************************************//**
* @file
* @brief EFR32MG12P_CRYPTO register and bit field definitions
- * @version 5.8.3
*******************************************************************************
* # License
- * Copyright 2019 Silicon Laboratories Inc. www.silabs.com
+ * Copyright 2020 Silicon Laboratories Inc. www.silabs.com
*******************************************************************************
*
* SPDX-License-Identifier: Zlib
diff --git a/cpu/efm32/families/efr32mg12p/include/vendor/efr32mg12p_csen.h b/cpu/efm32/families/efr32mg12p/include/vendor/efr32mg12p_csen.h
index 7030b843e8..a54f5fad2c 100644
--- a/cpu/efm32/families/efr32mg12p/include/vendor/efr32mg12p_csen.h
+++ b/cpu/efm32/families/efr32mg12p/include/vendor/efr32mg12p_csen.h
@@ -1,10 +1,9 @@
/***************************************************************************//**
* @file
* @brief EFR32MG12P_CSEN register and bit field definitions
- * @version 5.8.3
*******************************************************************************
* # License
- * Copyright 2019 Silicon Laboratories Inc. www.silabs.com
+ * Copyright 2020 Silicon Laboratories Inc. www.silabs.com
*******************************************************************************
*
* SPDX-License-Identifier: Zlib
diff --git a/cpu/efm32/families/efr32mg12p/include/vendor/efr32mg12p_devinfo.h b/cpu/efm32/families/efr32mg12p/include/vendor/efr32mg12p_devinfo.h
index d3f8855548..59c02e85e7 100644
--- a/cpu/efm32/families/efr32mg12p/include/vendor/efr32mg12p_devinfo.h
+++ b/cpu/efm32/families/efr32mg12p/include/vendor/efr32mg12p_devinfo.h
@@ -1,10 +1,9 @@
/***************************************************************************//**
* @file
* @brief EFR32MG12P_DEVINFO register and bit field definitions
- * @version 5.8.3
*******************************************************************************
* # License
- * Copyright 2019 Silicon Laboratories Inc. www.silabs.com
+ * Copyright 2020 Silicon Laboratories Inc. www.silabs.com
*******************************************************************************
*
* SPDX-License-Identifier: Zlib
@@ -330,6 +329,8 @@ typedef struct {
#define _DEVINFO_PART_DEVICE_FAMILY_EFR32BG13B 0x0000002CUL /**< Mode EFR32BG13B for DEVINFO_PART */
#define _DEVINFO_PART_DEVICE_FAMILY_EFR32BG13V 0x0000002DUL /**< Mode EFR32BG13V for DEVINFO_PART */
#define _DEVINFO_PART_DEVICE_FAMILY_EFR32ZG13P 0x0000002EUL /**< Mode EFR32ZG13P for DEVINFO_PART */
+#define _DEVINFO_PART_DEVICE_FAMILY_EFR32ZG13L 0x0000002FUL /**< Mode EFR32ZG13L for DEVINFO_PART */
+#define _DEVINFO_PART_DEVICE_FAMILY_EFR32ZG13S 0x00000030UL /**< Mode EFR32ZG13S for DEVINFO_PART */
#define _DEVINFO_PART_DEVICE_FAMILY_EFR32FG13P 0x00000031UL /**< Mode EFR32FG13P for DEVINFO_PART */
#define _DEVINFO_PART_DEVICE_FAMILY_EFR32FG13B 0x00000032UL /**< Mode EFR32FG13B for DEVINFO_PART */
#define _DEVINFO_PART_DEVICE_FAMILY_EFR32FG13V 0x00000033UL /**< Mode EFR32FG13V for DEVINFO_PART */
@@ -347,16 +348,16 @@ typedef struct {
#define _DEVINFO_PART_DEVICE_FAMILY_G 0x00000047UL /**< Mode G for DEVINFO_PART */
#define _DEVINFO_PART_DEVICE_FAMILY_EFM32GG 0x00000048UL /**< Mode EFM32GG for DEVINFO_PART */
#define _DEVINFO_PART_DEVICE_FAMILY_GG 0x00000048UL /**< Mode GG for DEVINFO_PART */
-#define _DEVINFO_PART_DEVICE_FAMILY_TG 0x00000049UL /**< Mode TG for DEVINFO_PART */
#define _DEVINFO_PART_DEVICE_FAMILY_EFM32TG 0x00000049UL /**< Mode EFM32TG for DEVINFO_PART */
+#define _DEVINFO_PART_DEVICE_FAMILY_TG 0x00000049UL /**< Mode TG for DEVINFO_PART */
#define _DEVINFO_PART_DEVICE_FAMILY_EFM32LG 0x0000004AUL /**< Mode EFM32LG for DEVINFO_PART */
#define _DEVINFO_PART_DEVICE_FAMILY_LG 0x0000004AUL /**< Mode LG for DEVINFO_PART */
-#define _DEVINFO_PART_DEVICE_FAMILY_EFM32WG 0x0000004BUL /**< Mode EFM32WG for DEVINFO_PART */
#define _DEVINFO_PART_DEVICE_FAMILY_WG 0x0000004BUL /**< Mode WG for DEVINFO_PART */
+#define _DEVINFO_PART_DEVICE_FAMILY_EFM32WG 0x0000004BUL /**< Mode EFM32WG for DEVINFO_PART */
#define _DEVINFO_PART_DEVICE_FAMILY_ZG 0x0000004CUL /**< Mode ZG for DEVINFO_PART */
#define _DEVINFO_PART_DEVICE_FAMILY_EFM32ZG 0x0000004CUL /**< Mode EFM32ZG for DEVINFO_PART */
-#define _DEVINFO_PART_DEVICE_FAMILY_HG 0x0000004DUL /**< Mode HG for DEVINFO_PART */
#define _DEVINFO_PART_DEVICE_FAMILY_EFM32HG 0x0000004DUL /**< Mode EFM32HG for DEVINFO_PART */
+#define _DEVINFO_PART_DEVICE_FAMILY_HG 0x0000004DUL /**< Mode HG for DEVINFO_PART */
#define _DEVINFO_PART_DEVICE_FAMILY_EFM32PG1B 0x00000051UL /**< Mode EFM32PG1B for DEVINFO_PART */
#define _DEVINFO_PART_DEVICE_FAMILY_EFM32JG1B 0x00000053UL /**< Mode EFM32JG1B for DEVINFO_PART */
#define _DEVINFO_PART_DEVICE_FAMILY_EFM32PG12B 0x00000055UL /**< Mode EFM32PG12B for DEVINFO_PART */
@@ -392,6 +393,8 @@ typedef struct {
#define DEVINFO_PART_DEVICE_FAMILY_EFR32BG13B (_DEVINFO_PART_DEVICE_FAMILY_EFR32BG13B << 16) /**< Shifted mode EFR32BG13B for DEVINFO_PART */
#define DEVINFO_PART_DEVICE_FAMILY_EFR32BG13V (_DEVINFO_PART_DEVICE_FAMILY_EFR32BG13V << 16) /**< Shifted mode EFR32BG13V for DEVINFO_PART */
#define DEVINFO_PART_DEVICE_FAMILY_EFR32ZG13P (_DEVINFO_PART_DEVICE_FAMILY_EFR32ZG13P << 16) /**< Shifted mode EFR32ZG13P for DEVINFO_PART */
+#define DEVINFO_PART_DEVICE_FAMILY_EFR32ZG13L (_DEVINFO_PART_DEVICE_FAMILY_EFR32ZG13L << 16) /**< Shifted mode EFR32ZG13L for DEVINFO_PART */
+#define DEVINFO_PART_DEVICE_FAMILY_EFR32ZG13S (_DEVINFO_PART_DEVICE_FAMILY_EFR32ZG13S << 16) /**< Shifted mode EFR32ZG13S for DEVINFO_PART */
#define DEVINFO_PART_DEVICE_FAMILY_EFR32FG13P (_DEVINFO_PART_DEVICE_FAMILY_EFR32FG13P << 16) /**< Shifted mode EFR32FG13P for DEVINFO_PART */
#define DEVINFO_PART_DEVICE_FAMILY_EFR32FG13B (_DEVINFO_PART_DEVICE_FAMILY_EFR32FG13B << 16) /**< Shifted mode EFR32FG13B for DEVINFO_PART */
#define DEVINFO_PART_DEVICE_FAMILY_EFR32FG13V (_DEVINFO_PART_DEVICE_FAMILY_EFR32FG13V << 16) /**< Shifted mode EFR32FG13V for DEVINFO_PART */
@@ -409,16 +412,16 @@ typedef struct {
#define DEVINFO_PART_DEVICE_FAMILY_G (_DEVINFO_PART_DEVICE_FAMILY_G << 16) /**< Shifted mode G for DEVINFO_PART */
#define DEVINFO_PART_DEVICE_FAMILY_EFM32GG (_DEVINFO_PART_DEVICE_FAMILY_EFM32GG << 16) /**< Shifted mode EFM32GG for DEVINFO_PART */
#define DEVINFO_PART_DEVICE_FAMILY_GG (_DEVINFO_PART_DEVICE_FAMILY_GG << 16) /**< Shifted mode GG for DEVINFO_PART */
-#define DEVINFO_PART_DEVICE_FAMILY_TG (_DEVINFO_PART_DEVICE_FAMILY_TG << 16) /**< Shifted mode TG for DEVINFO_PART */
#define DEVINFO_PART_DEVICE_FAMILY_EFM32TG (_DEVINFO_PART_DEVICE_FAMILY_EFM32TG << 16) /**< Shifted mode EFM32TG for DEVINFO_PART */
+#define DEVINFO_PART_DEVICE_FAMILY_TG (_DEVINFO_PART_DEVICE_FAMILY_TG << 16) /**< Shifted mode TG for DEVINFO_PART */
#define DEVINFO_PART_DEVICE_FAMILY_EFM32LG (_DEVINFO_PART_DEVICE_FAMILY_EFM32LG << 16) /**< Shifted mode EFM32LG for DEVINFO_PART */
#define DEVINFO_PART_DEVICE_FAMILY_LG (_DEVINFO_PART_DEVICE_FAMILY_LG << 16) /**< Shifted mode LG for DEVINFO_PART */
-#define DEVINFO_PART_DEVICE_FAMILY_EFM32WG (_DEVINFO_PART_DEVICE_FAMILY_EFM32WG << 16) /**< Shifted mode EFM32WG for DEVINFO_PART */
#define DEVINFO_PART_DEVICE_FAMILY_WG (_DEVINFO_PART_DEVICE_FAMILY_WG << 16) /**< Shifted mode WG for DEVINFO_PART */
+#define DEVINFO_PART_DEVICE_FAMILY_EFM32WG (_DEVINFO_PART_DEVICE_FAMILY_EFM32WG << 16) /**< Shifted mode EFM32WG for DEVINFO_PART */
#define DEVINFO_PART_DEVICE_FAMILY_ZG (_DEVINFO_PART_DEVICE_FAMILY_ZG << 16) /**< Shifted mode ZG for DEVINFO_PART */
#define DEVINFO_PART_DEVICE_FAMILY_EFM32ZG (_DEVINFO_PART_DEVICE_FAMILY_EFM32ZG << 16) /**< Shifted mode EFM32ZG for DEVINFO_PART */
-#define DEVINFO_PART_DEVICE_FAMILY_HG (_DEVINFO_PART_DEVICE_FAMILY_HG << 16) /**< Shifted mode HG for DEVINFO_PART */
#define DEVINFO_PART_DEVICE_FAMILY_EFM32HG (_DEVINFO_PART_DEVICE_FAMILY_EFM32HG << 16) /**< Shifted mode EFM32HG for DEVINFO_PART */
+#define DEVINFO_PART_DEVICE_FAMILY_HG (_DEVINFO_PART_DEVICE_FAMILY_HG << 16) /**< Shifted mode HG for DEVINFO_PART */
#define DEVINFO_PART_DEVICE_FAMILY_EFM32PG1B (_DEVINFO_PART_DEVICE_FAMILY_EFM32PG1B << 16) /**< Shifted mode EFM32PG1B for DEVINFO_PART */
#define DEVINFO_PART_DEVICE_FAMILY_EFM32JG1B (_DEVINFO_PART_DEVICE_FAMILY_EFM32JG1B << 16) /**< Shifted mode EFM32JG1B for DEVINFO_PART */
#define DEVINFO_PART_DEVICE_FAMILY_EFM32PG12B (_DEVINFO_PART_DEVICE_FAMILY_EFM32PG12B << 16) /**< Shifted mode EFM32PG12B for DEVINFO_PART */
diff --git a/cpu/efm32/families/efr32mg12p/include/vendor/efr32mg12p_dma_descriptor.h b/cpu/efm32/families/efr32mg12p/include/vendor/efr32mg12p_dma_descriptor.h
index a3e002f158..abf3a97e55 100644
--- a/cpu/efm32/families/efr32mg12p/include/vendor/efr32mg12p_dma_descriptor.h
+++ b/cpu/efm32/families/efr32mg12p/include/vendor/efr32mg12p_dma_descriptor.h
@@ -1,10 +1,9 @@
/***************************************************************************//**
* @file
* @brief EFR32MG12P_DMA_DESCRIPTOR register and bit field definitions
- * @version 5.8.3
*******************************************************************************
* # License
- * Copyright 2019 Silicon Laboratories Inc. www.silabs.com
+ * Copyright 2020 Silicon Laboratories Inc. www.silabs.com
*******************************************************************************
*
* SPDX-License-Identifier: Zlib
diff --git a/cpu/efm32/families/efr32mg12p/include/vendor/efr32mg12p_dmareq.h b/cpu/efm32/families/efr32mg12p/include/vendor/efr32mg12p_dmareq.h
index 7d51485c1a..f5e43270a3 100644
--- a/cpu/efm32/families/efr32mg12p/include/vendor/efr32mg12p_dmareq.h
+++ b/cpu/efm32/families/efr32mg12p/include/vendor/efr32mg12p_dmareq.h
@@ -1,10 +1,9 @@
/***************************************************************************//**
* @file
* @brief EFR32MG12P_DMAREQ register and bit field definitions
- * @version 5.8.3
*******************************************************************************
* # License
- * Copyright 2019 Silicon Laboratories Inc. www.silabs.com
+ * Copyright 2020 Silicon Laboratories Inc. www.silabs.com
*******************************************************************************
*
* SPDX-License-Identifier: Zlib
diff --git a/cpu/efm32/families/efr32mg12p/include/vendor/efr32mg12p_emu.h b/cpu/efm32/families/efr32mg12p/include/vendor/efr32mg12p_emu.h
index f5398889c9..ffb1063926 100644
--- a/cpu/efm32/families/efr32mg12p/include/vendor/efr32mg12p_emu.h
+++ b/cpu/efm32/families/efr32mg12p/include/vendor/efr32mg12p_emu.h
@@ -1,10 +1,9 @@
/***************************************************************************//**
* @file
* @brief EFR32MG12P_EMU register and bit field definitions
- * @version 5.8.3
*******************************************************************************
* # License
- * Copyright 2019 Silicon Laboratories Inc. www.silabs.com
+ * Copyright 2020 Silicon Laboratories Inc. www.silabs.com
*******************************************************************************
*
* SPDX-License-Identifier: Zlib
@@ -226,13 +225,13 @@ typedef struct {
#define _EMU_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for EMU_LOCKKEY */
#define _EMU_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for EMU_LOCKKEY */
#define _EMU_LOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_LOCK */
-#define _EMU_LOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for EMU_LOCK */
#define _EMU_LOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for EMU_LOCK */
+#define _EMU_LOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for EMU_LOCK */
#define _EMU_LOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for EMU_LOCK */
#define _EMU_LOCK_LOCKKEY_UNLOCK 0x0000ADE8UL /**< Mode UNLOCK for EMU_LOCK */
#define EMU_LOCK_LOCKKEY_DEFAULT (_EMU_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_LOCK */
-#define EMU_LOCK_LOCKKEY_LOCK (_EMU_LOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for EMU_LOCK */
#define EMU_LOCK_LOCKKEY_UNLOCKED (_EMU_LOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for EMU_LOCK */
+#define EMU_LOCK_LOCKKEY_LOCK (_EMU_LOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for EMU_LOCK */
#define EMU_LOCK_LOCKKEY_LOCKED (_EMU_LOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for EMU_LOCK */
#define EMU_LOCK_LOCKKEY_UNLOCK (_EMU_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for EMU_LOCK */
@@ -762,13 +761,13 @@ typedef struct {
#define _EMU_PWRLOCK_LOCKKEY_SHIFT 0 /**< Shift value for EMU_LOCKKEY */
#define _EMU_PWRLOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for EMU_LOCKKEY */
#define _EMU_PWRLOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_PWRLOCK */
-#define _EMU_PWRLOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for EMU_PWRLOCK */
#define _EMU_PWRLOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for EMU_PWRLOCK */
+#define _EMU_PWRLOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for EMU_PWRLOCK */
#define _EMU_PWRLOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for EMU_PWRLOCK */
#define _EMU_PWRLOCK_LOCKKEY_UNLOCK 0x0000ADE8UL /**< Mode UNLOCK for EMU_PWRLOCK */
#define EMU_PWRLOCK_LOCKKEY_DEFAULT (_EMU_PWRLOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_PWRLOCK */
-#define EMU_PWRLOCK_LOCKKEY_LOCK (_EMU_PWRLOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for EMU_PWRLOCK */
#define EMU_PWRLOCK_LOCKKEY_UNLOCKED (_EMU_PWRLOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for EMU_PWRLOCK */
+#define EMU_PWRLOCK_LOCKKEY_LOCK (_EMU_PWRLOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for EMU_PWRLOCK */
#define EMU_PWRLOCK_LOCKKEY_LOCKED (_EMU_PWRLOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for EMU_PWRLOCK */
#define EMU_PWRLOCK_LOCKKEY_UNLOCK (_EMU_PWRLOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for EMU_PWRLOCK */
diff --git a/cpu/efm32/families/efr32mg12p/include/vendor/efr32mg12p_etm.h b/cpu/efm32/families/efr32mg12p/include/vendor/efr32mg12p_etm.h
index 11e53ad2c0..8c07d73d14 100644
--- a/cpu/efm32/families/efr32mg12p/include/vendor/efr32mg12p_etm.h
+++ b/cpu/efm32/families/efr32mg12p/include/vendor/efr32mg12p_etm.h
@@ -1,10 +1,9 @@
/***************************************************************************//**
* @file
* @brief EFR32MG12P_ETM register and bit field definitions
- * @version 5.8.3
*******************************************************************************
* # License
- * Copyright 2019 Silicon Laboratories Inc. www.silabs.com
+ * Copyright 2020 Silicon Laboratories Inc. www.silabs.com
*******************************************************************************
*
* SPDX-License-Identifier: Zlib
diff --git a/cpu/efm32/families/efr32mg12p/include/vendor/efr32mg12p_fpueh.h b/cpu/efm32/families/efr32mg12p/include/vendor/efr32mg12p_fpueh.h
index 4e57f395e3..4d4fb0083d 100644
--- a/cpu/efm32/families/efr32mg12p/include/vendor/efr32mg12p_fpueh.h
+++ b/cpu/efm32/families/efr32mg12p/include/vendor/efr32mg12p_fpueh.h
@@ -1,10 +1,9 @@
/***************************************************************************//**
* @file
* @brief EFR32MG12P_FPUEH register and bit field definitions
- * @version 5.8.3
*******************************************************************************
* # License
- * Copyright 2019 Silicon Laboratories Inc. www.silabs.com
+ * Copyright 2020 Silicon Laboratories Inc. www.silabs.com
*******************************************************************************
*
* SPDX-License-Identifier: Zlib
diff --git a/cpu/efm32/families/efr32mg12p/include/vendor/efr32mg12p_gpcrc.h b/cpu/efm32/families/efr32mg12p/include/vendor/efr32mg12p_gpcrc.h
index 524763f350..71398edb84 100644
--- a/cpu/efm32/families/efr32mg12p/include/vendor/efr32mg12p_gpcrc.h
+++ b/cpu/efm32/families/efr32mg12p/include/vendor/efr32mg12p_gpcrc.h
@@ -1,10 +1,9 @@
/***************************************************************************//**
* @file
* @brief EFR32MG12P_GPCRC register and bit field definitions
- * @version 5.8.3
*******************************************************************************
* # License
- * Copyright 2019 Silicon Laboratories Inc. www.silabs.com
+ * Copyright 2020 Silicon Laboratories Inc. www.silabs.com
*******************************************************************************
*
* SPDX-License-Identifier: Zlib
diff --git a/cpu/efm32/families/efr32mg12p/include/vendor/efr32mg12p_gpio.h b/cpu/efm32/families/efr32mg12p/include/vendor/efr32mg12p_gpio.h
index 2d5e8e23cb..2cf5ed5994 100644
--- a/cpu/efm32/families/efr32mg12p/include/vendor/efr32mg12p_gpio.h
+++ b/cpu/efm32/families/efr32mg12p/include/vendor/efr32mg12p_gpio.h
@@ -1,10 +1,9 @@
/***************************************************************************//**
* @file
* @brief EFR32MG12P_GPIO register and bit field definitions
- * @version 5.8.3
*******************************************************************************
* # License
- * Copyright 2019 Silicon Laboratories Inc. www.silabs.com
+ * Copyright 2020 Silicon Laboratories Inc. www.silabs.com
*******************************************************************************
*
* SPDX-License-Identifier: Zlib
@@ -1536,13 +1535,13 @@ typedef struct {
#define _GPIO_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for GPIO_LOCKKEY */
#define _GPIO_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for GPIO_LOCKKEY */
#define _GPIO_LOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_LOCK */
-#define _GPIO_LOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for GPIO_LOCK */
#define _GPIO_LOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for GPIO_LOCK */
+#define _GPIO_LOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for GPIO_LOCK */
#define _GPIO_LOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for GPIO_LOCK */
#define _GPIO_LOCK_LOCKKEY_UNLOCK 0x0000A534UL /**< Mode UNLOCK for GPIO_LOCK */
#define GPIO_LOCK_LOCKKEY_DEFAULT (_GPIO_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_LOCK */
-#define GPIO_LOCK_LOCKKEY_LOCK (_GPIO_LOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for GPIO_LOCK */
#define GPIO_LOCK_LOCKKEY_UNLOCKED (_GPIO_LOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for GPIO_LOCK */
+#define GPIO_LOCK_LOCKKEY_LOCK (_GPIO_LOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for GPIO_LOCK */
#define GPIO_LOCK_LOCKKEY_LOCKED (_GPIO_LOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for GPIO_LOCK */
#define GPIO_LOCK_LOCKKEY_UNLOCK (_GPIO_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for GPIO_LOCK */
diff --git a/cpu/efm32/families/efr32mg12p/include/vendor/efr32mg12p_gpio_p.h b/cpu/efm32/families/efr32mg12p/include/vendor/efr32mg12p_gpio_p.h
index 13bda82a09..c1b1268ade 100644
--- a/cpu/efm32/families/efr32mg12p/include/vendor/efr32mg12p_gpio_p.h
+++ b/cpu/efm32/families/efr32mg12p/include/vendor/efr32mg12p_gpio_p.h
@@ -1,10 +1,9 @@
/***************************************************************************//**
* @file
* @brief EFR32MG12P_GPIO_P register and bit field definitions
- * @version 5.8.3
*******************************************************************************
* # License
- * Copyright 2019 Silicon Laboratories Inc. www.silabs.com
+ * Copyright 2020 Silicon Laboratories Inc. www.silabs.com
*******************************************************************************
*
* SPDX-License-Identifier: Zlib
diff --git a/cpu/efm32/families/efr32mg12p/include/vendor/efr32mg12p_i2c.h b/cpu/efm32/families/efr32mg12p/include/vendor/efr32mg12p_i2c.h
index 412ad36eb7..545eb40197 100644
--- a/cpu/efm32/families/efr32mg12p/include/vendor/efr32mg12p_i2c.h
+++ b/cpu/efm32/families/efr32mg12p/include/vendor/efr32mg12p_i2c.h
@@ -1,10 +1,9 @@
/***************************************************************************//**
* @file
* @brief EFR32MG12P_I2C register and bit field definitions
- * @version 5.8.3
*******************************************************************************
* # License
- * Copyright 2019 Silicon Laboratories Inc. www.silabs.com
+ * Copyright 2020 Silicon Laboratories Inc. www.silabs.com
*******************************************************************************
*
* SPDX-License-Identifier: Zlib
diff --git a/cpu/efm32/families/efr32mg12p/include/vendor/efr32mg12p_idac.h b/cpu/efm32/families/efr32mg12p/include/vendor/efr32mg12p_idac.h
index cd57f96ea9..bbffe7634b 100644
--- a/cpu/efm32/families/efr32mg12p/include/vendor/efr32mg12p_idac.h
+++ b/cpu/efm32/families/efr32mg12p/include/vendor/efr32mg12p_idac.h
@@ -1,10 +1,9 @@
/***************************************************************************//**
* @file
* @brief EFR32MG12P_IDAC register and bit field definitions
- * @version 5.8.3
*******************************************************************************
* # License
- * Copyright 2019 Silicon Laboratories Inc. www.silabs.com
+ * Copyright 2020 Silicon Laboratories Inc. www.silabs.com
*******************************************************************************
*
* SPDX-License-Identifier: Zlib
diff --git a/cpu/efm32/families/efr32mg12p/include/vendor/efr32mg12p_ldma.h b/cpu/efm32/families/efr32mg12p/include/vendor/efr32mg12p_ldma.h
index 104a031605..fb1d2e54ef 100644
--- a/cpu/efm32/families/efr32mg12p/include/vendor/efr32mg12p_ldma.h
+++ b/cpu/efm32/families/efr32mg12p/include/vendor/efr32mg12p_ldma.h
@@ -1,10 +1,9 @@
/***************************************************************************//**
* @file
* @brief EFR32MG12P_LDMA register and bit field definitions
- * @version 5.8.3
*******************************************************************************
* # License
- * Copyright 2019 Silicon Laboratories Inc. www.silabs.com
+ * Copyright 2020 Silicon Laboratories Inc. www.silabs.com
*******************************************************************************
*
* SPDX-License-Identifier: Zlib
diff --git a/cpu/efm32/families/efr32mg12p/include/vendor/efr32mg12p_ldma_ch.h b/cpu/efm32/families/efr32mg12p/include/vendor/efr32mg12p_ldma_ch.h
index a7b4f2762c..62f4bf4728 100644
--- a/cpu/efm32/families/efr32mg12p/include/vendor/efr32mg12p_ldma_ch.h
+++ b/cpu/efm32/families/efr32mg12p/include/vendor/efr32mg12p_ldma_ch.h
@@ -1,10 +1,9 @@
/***************************************************************************//**
* @file
* @brief EFR32MG12P_LDMA_CH register and bit field definitions
- * @version 5.8.3
*******************************************************************************
* # License
- * Copyright 2019 Silicon Laboratories Inc. www.silabs.com
+ * Copyright 2020 Silicon Laboratories Inc. www.silabs.com
*******************************************************************************
*
* SPDX-License-Identifier: Zlib
diff --git a/cpu/efm32/families/efr32mg12p/include/vendor/efr32mg12p_lesense.h b/cpu/efm32/families/efr32mg12p/include/vendor/efr32mg12p_lesense.h
index d280ee0086..7d9826d31c 100644
--- a/cpu/efm32/families/efr32mg12p/include/vendor/efr32mg12p_lesense.h
+++ b/cpu/efm32/families/efr32mg12p/include/vendor/efr32mg12p_lesense.h
@@ -1,10 +1,9 @@
/***************************************************************************//**
* @file
* @brief EFR32MG12P_LESENSE register and bit field definitions
- * @version 5.8.3
*******************************************************************************
* # License
- * Copyright 2019 Silicon Laboratories Inc. www.silabs.com
+ * Copyright 2020 Silicon Laboratories Inc. www.silabs.com
*******************************************************************************
*
* SPDX-License-Identifier: Zlib
@@ -1657,27 +1656,27 @@ typedef struct {
#define _LESENSE_ST_TCONFA_PRSACT_MASK 0x70000UL /**< Bit mask for LESENSE_PRSACT */
#define _LESENSE_ST_TCONFA_PRSACT_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_ST_TCONFA */
#define _LESENSE_ST_TCONFA_PRSACT_NONE 0x00000000UL /**< Mode NONE for LESENSE_ST_TCONFA */
-#define _LESENSE_ST_TCONFA_PRSACT_UP 0x00000001UL /**< Mode UP for LESENSE_ST_TCONFA */
#define _LESENSE_ST_TCONFA_PRSACT_PRS0 0x00000001UL /**< Mode PRS0 for LESENSE_ST_TCONFA */
-#define _LESENSE_ST_TCONFA_PRSACT_PRS1 0x00000002UL /**< Mode PRS1 for LESENSE_ST_TCONFA */
+#define _LESENSE_ST_TCONFA_PRSACT_UP 0x00000001UL /**< Mode UP for LESENSE_ST_TCONFA */
#define _LESENSE_ST_TCONFA_PRSACT_DOWN 0x00000002UL /**< Mode DOWN for LESENSE_ST_TCONFA */
+#define _LESENSE_ST_TCONFA_PRSACT_PRS1 0x00000002UL /**< Mode PRS1 for LESENSE_ST_TCONFA */
#define _LESENSE_ST_TCONFA_PRSACT_PRS01 0x00000003UL /**< Mode PRS01 for LESENSE_ST_TCONFA */
#define _LESENSE_ST_TCONFA_PRSACT_PRS2 0x00000004UL /**< Mode PRS2 for LESENSE_ST_TCONFA */
-#define _LESENSE_ST_TCONFA_PRSACT_PRS02 0x00000005UL /**< Mode PRS02 for LESENSE_ST_TCONFA */
#define _LESENSE_ST_TCONFA_PRSACT_UPANDPRS2 0x00000005UL /**< Mode UPANDPRS2 for LESENSE_ST_TCONFA */
+#define _LESENSE_ST_TCONFA_PRSACT_PRS02 0x00000005UL /**< Mode PRS02 for LESENSE_ST_TCONFA */
#define _LESENSE_ST_TCONFA_PRSACT_PRS12 0x00000006UL /**< Mode PRS12 for LESENSE_ST_TCONFA */
#define _LESENSE_ST_TCONFA_PRSACT_DOWNANDPRS2 0x00000006UL /**< Mode DOWNANDPRS2 for LESENSE_ST_TCONFA */
#define _LESENSE_ST_TCONFA_PRSACT_PRS012 0x00000007UL /**< Mode PRS012 for LESENSE_ST_TCONFA */
#define LESENSE_ST_TCONFA_PRSACT_DEFAULT (_LESENSE_ST_TCONFA_PRSACT_DEFAULT << 16) /**< Shifted mode DEFAULT for LESENSE_ST_TCONFA */
#define LESENSE_ST_TCONFA_PRSACT_NONE (_LESENSE_ST_TCONFA_PRSACT_NONE << 16) /**< Shifted mode NONE for LESENSE_ST_TCONFA */
-#define LESENSE_ST_TCONFA_PRSACT_UP (_LESENSE_ST_TCONFA_PRSACT_UP << 16) /**< Shifted mode UP for LESENSE_ST_TCONFA */
#define LESENSE_ST_TCONFA_PRSACT_PRS0 (_LESENSE_ST_TCONFA_PRSACT_PRS0 << 16) /**< Shifted mode PRS0 for LESENSE_ST_TCONFA */
-#define LESENSE_ST_TCONFA_PRSACT_PRS1 (_LESENSE_ST_TCONFA_PRSACT_PRS1 << 16) /**< Shifted mode PRS1 for LESENSE_ST_TCONFA */
+#define LESENSE_ST_TCONFA_PRSACT_UP (_LESENSE_ST_TCONFA_PRSACT_UP << 16) /**< Shifted mode UP for LESENSE_ST_TCONFA */
#define LESENSE_ST_TCONFA_PRSACT_DOWN (_LESENSE_ST_TCONFA_PRSACT_DOWN << 16) /**< Shifted mode DOWN for LESENSE_ST_TCONFA */
+#define LESENSE_ST_TCONFA_PRSACT_PRS1 (_LESENSE_ST_TCONFA_PRSACT_PRS1 << 16) /**< Shifted mode PRS1 for LESENSE_ST_TCONFA */
#define LESENSE_ST_TCONFA_PRSACT_PRS01 (_LESENSE_ST_TCONFA_PRSACT_PRS01 << 16) /**< Shifted mode PRS01 for LESENSE_ST_TCONFA */
#define LESENSE_ST_TCONFA_PRSACT_PRS2 (_LESENSE_ST_TCONFA_PRSACT_PRS2 << 16) /**< Shifted mode PRS2 for LESENSE_ST_TCONFA */
-#define LESENSE_ST_TCONFA_PRSACT_PRS02 (_LESENSE_ST_TCONFA_PRSACT_PRS02 << 16) /**< Shifted mode PRS02 for LESENSE_ST_TCONFA */
#define LESENSE_ST_TCONFA_PRSACT_UPANDPRS2 (_LESENSE_ST_TCONFA_PRSACT_UPANDPRS2 << 16) /**< Shifted mode UPANDPRS2 for LESENSE_ST_TCONFA */
+#define LESENSE_ST_TCONFA_PRSACT_PRS02 (_LESENSE_ST_TCONFA_PRSACT_PRS02 << 16) /**< Shifted mode PRS02 for LESENSE_ST_TCONFA */
#define LESENSE_ST_TCONFA_PRSACT_PRS12 (_LESENSE_ST_TCONFA_PRSACT_PRS12 << 16) /**< Shifted mode PRS12 for LESENSE_ST_TCONFA */
#define LESENSE_ST_TCONFA_PRSACT_DOWNANDPRS2 (_LESENSE_ST_TCONFA_PRSACT_DOWNANDPRS2 << 16) /**< Shifted mode DOWNANDPRS2 for LESENSE_ST_TCONFA */
#define LESENSE_ST_TCONFA_PRSACT_PRS012 (_LESENSE_ST_TCONFA_PRSACT_PRS012 << 16) /**< Shifted mode PRS012 for LESENSE_ST_TCONFA */
@@ -1706,27 +1705,27 @@ typedef struct {
#define _LESENSE_ST_TCONFB_PRSACT_MASK 0x70000UL /**< Bit mask for LESENSE_PRSACT */
#define _LESENSE_ST_TCONFB_PRSACT_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_ST_TCONFB */
#define _LESENSE_ST_TCONFB_PRSACT_NONE 0x00000000UL /**< Mode NONE for LESENSE_ST_TCONFB */
-#define _LESENSE_ST_TCONFB_PRSACT_UP 0x00000001UL /**< Mode UP for LESENSE_ST_TCONFB */
#define _LESENSE_ST_TCONFB_PRSACT_PRS0 0x00000001UL /**< Mode PRS0 for LESENSE_ST_TCONFB */
-#define _LESENSE_ST_TCONFB_PRSACT_PRS1 0x00000002UL /**< Mode PRS1 for LESENSE_ST_TCONFB */
+#define _LESENSE_ST_TCONFB_PRSACT_UP 0x00000001UL /**< Mode UP for LESENSE_ST_TCONFB */
#define _LESENSE_ST_TCONFB_PRSACT_DOWN 0x00000002UL /**< Mode DOWN for LESENSE_ST_TCONFB */
+#define _LESENSE_ST_TCONFB_PRSACT_PRS1 0x00000002UL /**< Mode PRS1 for LESENSE_ST_TCONFB */
#define _LESENSE_ST_TCONFB_PRSACT_PRS01 0x00000003UL /**< Mode PRS01 for LESENSE_ST_TCONFB */
#define _LESENSE_ST_TCONFB_PRSACT_PRS2 0x00000004UL /**< Mode PRS2 for LESENSE_ST_TCONFB */
-#define _LESENSE_ST_TCONFB_PRSACT_PRS02 0x00000005UL /**< Mode PRS02 for LESENSE_ST_TCONFB */
#define _LESENSE_ST_TCONFB_PRSACT_UPANDPRS2 0x00000005UL /**< Mode UPANDPRS2 for LESENSE_ST_TCONFB */
+#define _LESENSE_ST_TCONFB_PRSACT_PRS02 0x00000005UL /**< Mode PRS02 for LESENSE_ST_TCONFB */
#define _LESENSE_ST_TCONFB_PRSACT_PRS12 0x00000006UL /**< Mode PRS12 for LESENSE_ST_TCONFB */
#define _LESENSE_ST_TCONFB_PRSACT_DOWNANDPRS2 0x00000006UL /**< Mode DOWNANDPRS2 for LESENSE_ST_TCONFB */
#define _LESENSE_ST_TCONFB_PRSACT_PRS012 0x00000007UL /**< Mode PRS012 for LESENSE_ST_TCONFB */
#define LESENSE_ST_TCONFB_PRSACT_DEFAULT (_LESENSE_ST_TCONFB_PRSACT_DEFAULT << 16) /**< Shifted mode DEFAULT for LESENSE_ST_TCONFB */
#define LESENSE_ST_TCONFB_PRSACT_NONE (_LESENSE_ST_TCONFB_PRSACT_NONE << 16) /**< Shifted mode NONE for LESENSE_ST_TCONFB */
-#define LESENSE_ST_TCONFB_PRSACT_UP (_LESENSE_ST_TCONFB_PRSACT_UP << 16) /**< Shifted mode UP for LESENSE_ST_TCONFB */
#define LESENSE_ST_TCONFB_PRSACT_PRS0 (_LESENSE_ST_TCONFB_PRSACT_PRS0 << 16) /**< Shifted mode PRS0 for LESENSE_ST_TCONFB */
-#define LESENSE_ST_TCONFB_PRSACT_PRS1 (_LESENSE_ST_TCONFB_PRSACT_PRS1 << 16) /**< Shifted mode PRS1 for LESENSE_ST_TCONFB */
+#define LESENSE_ST_TCONFB_PRSACT_UP (_LESENSE_ST_TCONFB_PRSACT_UP << 16) /**< Shifted mode UP for LESENSE_ST_TCONFB */
#define LESENSE_ST_TCONFB_PRSACT_DOWN (_LESENSE_ST_TCONFB_PRSACT_DOWN << 16) /**< Shifted mode DOWN for LESENSE_ST_TCONFB */
+#define LESENSE_ST_TCONFB_PRSACT_PRS1 (_LESENSE_ST_TCONFB_PRSACT_PRS1 << 16) /**< Shifted mode PRS1 for LESENSE_ST_TCONFB */
#define LESENSE_ST_TCONFB_PRSACT_PRS01 (_LESENSE_ST_TCONFB_PRSACT_PRS01 << 16) /**< Shifted mode PRS01 for LESENSE_ST_TCONFB */
#define LESENSE_ST_TCONFB_PRSACT_PRS2 (_LESENSE_ST_TCONFB_PRSACT_PRS2 << 16) /**< Shifted mode PRS2 for LESENSE_ST_TCONFB */
-#define LESENSE_ST_TCONFB_PRSACT_PRS02 (_LESENSE_ST_TCONFB_PRSACT_PRS02 << 16) /**< Shifted mode PRS02 for LESENSE_ST_TCONFB */
#define LESENSE_ST_TCONFB_PRSACT_UPANDPRS2 (_LESENSE_ST_TCONFB_PRSACT_UPANDPRS2 << 16) /**< Shifted mode UPANDPRS2 for LESENSE_ST_TCONFB */
+#define LESENSE_ST_TCONFB_PRSACT_PRS02 (_LESENSE_ST_TCONFB_PRSACT_PRS02 << 16) /**< Shifted mode PRS02 for LESENSE_ST_TCONFB */
#define LESENSE_ST_TCONFB_PRSACT_PRS12 (_LESENSE_ST_TCONFB_PRSACT_PRS12 << 16) /**< Shifted mode PRS12 for LESENSE_ST_TCONFB */
#define LESENSE_ST_TCONFB_PRSACT_DOWNANDPRS2 (_LESENSE_ST_TCONFB_PRSACT_DOWNANDPRS2 << 16) /**< Shifted mode DOWNANDPRS2 for LESENSE_ST_TCONFB */
#define LESENSE_ST_TCONFB_PRSACT_PRS012 (_LESENSE_ST_TCONFB_PRSACT_PRS012 << 16) /**< Shifted mode PRS012 for LESENSE_ST_TCONFB */
diff --git a/cpu/efm32/families/efr32mg12p/include/vendor/efr32mg12p_lesense_buf.h b/cpu/efm32/families/efr32mg12p/include/vendor/efr32mg12p_lesense_buf.h
index a3410bf4b5..74198a6b32 100644
--- a/cpu/efm32/families/efr32mg12p/include/vendor/efr32mg12p_lesense_buf.h
+++ b/cpu/efm32/families/efr32mg12p/include/vendor/efr32mg12p_lesense_buf.h
@@ -1,10 +1,9 @@
/***************************************************************************//**
* @file
* @brief EFR32MG12P_LESENSE_BUF register and bit field definitions
- * @version 5.8.3
*******************************************************************************
* # License
- * Copyright 2019 Silicon Laboratories Inc. www.silabs.com
+ * Copyright 2020 Silicon Laboratories Inc. www.silabs.com
*******************************************************************************
*
* SPDX-License-Identifier: Zlib
diff --git a/cpu/efm32/families/efr32mg12p/include/vendor/efr32mg12p_lesense_ch.h b/cpu/efm32/families/efr32mg12p/include/vendor/efr32mg12p_lesense_ch.h
index 9b5ad3e545..a8645a3d53 100644
--- a/cpu/efm32/families/efr32mg12p/include/vendor/efr32mg12p_lesense_ch.h
+++ b/cpu/efm32/families/efr32mg12p/include/vendor/efr32mg12p_lesense_ch.h
@@ -1,10 +1,9 @@
/***************************************************************************//**
* @file
* @brief EFR32MG12P_LESENSE_CH register and bit field definitions
- * @version 5.8.3
*******************************************************************************
* # License
- * Copyright 2019 Silicon Laboratories Inc. www.silabs.com
+ * Copyright 2020 Silicon Laboratories Inc. www.silabs.com
*******************************************************************************
*
* SPDX-License-Identifier: Zlib
diff --git a/cpu/efm32/families/efr32mg12p/include/vendor/efr32mg12p_lesense_st.h b/cpu/efm32/families/efr32mg12p/include/vendor/efr32mg12p_lesense_st.h
index 15a4e15abc..6de018b92b 100644
--- a/cpu/efm32/families/efr32mg12p/include/vendor/efr32mg12p_lesense_st.h
+++ b/cpu/efm32/families/efr32mg12p/include/vendor/efr32mg12p_lesense_st.h
@@ -1,10 +1,9 @@
/***************************************************************************//**
* @file
* @brief EFR32MG12P_LESENSE_ST register and bit field definitions
- * @version 5.8.3
*******************************************************************************
* # License
- * Copyright 2019 Silicon Laboratories Inc. www.silabs.com
+ * Copyright 2020 Silicon Laboratories Inc. www.silabs.com
*******************************************************************************
*
* SPDX-License-Identifier: Zlib
diff --git a/cpu/efm32/families/efr32mg12p/include/vendor/efr32mg12p_letimer.h b/cpu/efm32/families/efr32mg12p/include/vendor/efr32mg12p_letimer.h
index 24ccf6b55e..4972b5d40e 100644
--- a/cpu/efm32/families/efr32mg12p/include/vendor/efr32mg12p_letimer.h
+++ b/cpu/efm32/families/efr32mg12p/include/vendor/efr32mg12p_letimer.h
@@ -1,10 +1,9 @@
/***************************************************************************//**
* @file
* @brief EFR32MG12P_LETIMER register and bit field definitions
- * @version 5.8.3
*******************************************************************************
* # License
- * Copyright 2019 Silicon Laboratories Inc. www.silabs.com
+ * Copyright 2020 Silicon Laboratories Inc. www.silabs.com
*******************************************************************************
*
* SPDX-License-Identifier: Zlib
diff --git a/cpu/efm32/families/efr32mg12p/include/vendor/efr32mg12p_leuart.h b/cpu/efm32/families/efr32mg12p/include/vendor/efr32mg12p_leuart.h
index ac7e6777d9..729b4a8c5b 100644
--- a/cpu/efm32/families/efr32mg12p/include/vendor/efr32mg12p_leuart.h
+++ b/cpu/efm32/families/efr32mg12p/include/vendor/efr32mg12p_leuart.h
@@ -1,10 +1,9 @@
/***************************************************************************//**
* @file
* @brief EFR32MG12P_LEUART register and bit field definitions
- * @version 5.8.3
*******************************************************************************
* # License
- * Copyright 2019 Silicon Laboratories Inc. www.silabs.com
+ * Copyright 2020 Silicon Laboratories Inc. www.silabs.com
*******************************************************************************
*
* SPDX-License-Identifier: Zlib
diff --git a/cpu/efm32/families/efr32mg12p/include/vendor/efr32mg12p_msc.h b/cpu/efm32/families/efr32mg12p/include/vendor/efr32mg12p_msc.h
index abe906b75b..1e16400fd9 100644
--- a/cpu/efm32/families/efr32mg12p/include/vendor/efr32mg12p_msc.h
+++ b/cpu/efm32/families/efr32mg12p/include/vendor/efr32mg12p_msc.h
@@ -1,10 +1,9 @@
/***************************************************************************//**
* @file
* @brief EFR32MG12P_MSC register and bit field definitions
- * @version 5.8.3
*******************************************************************************
* # License
- * Copyright 2019 Silicon Laboratories Inc. www.silabs.com
+ * Copyright 2020 Silicon Laboratories Inc. www.silabs.com
*******************************************************************************
*
* SPDX-License-Identifier: Zlib
@@ -489,13 +488,13 @@ typedef struct {
#define _MSC_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for MSC_LOCKKEY */
#define _MSC_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for MSC_LOCKKEY */
#define _MSC_LOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_LOCK */
-#define _MSC_LOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for MSC_LOCK */
#define _MSC_LOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for MSC_LOCK */
+#define _MSC_LOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for MSC_LOCK */
#define _MSC_LOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for MSC_LOCK */
#define _MSC_LOCK_LOCKKEY_UNLOCK 0x00001B71UL /**< Mode UNLOCK for MSC_LOCK */
#define MSC_LOCK_LOCKKEY_DEFAULT (_MSC_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_LOCK */
-#define MSC_LOCK_LOCKKEY_LOCK (_MSC_LOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for MSC_LOCK */
#define MSC_LOCK_LOCKKEY_UNLOCKED (_MSC_LOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for MSC_LOCK */
+#define MSC_LOCK_LOCKKEY_LOCK (_MSC_LOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for MSC_LOCK */
#define MSC_LOCK_LOCKKEY_LOCKED (_MSC_LOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for MSC_LOCK */
#define MSC_LOCK_LOCKKEY_UNLOCK (_MSC_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for MSC_LOCK */
@@ -539,13 +538,13 @@ typedef struct {
#define _MSC_MASSLOCK_MASK 0x0000FFFFUL /**< Mask for MSC_MASSLOCK */
#define _MSC_MASSLOCK_LOCKKEY_SHIFT 0 /**< Shift value for MSC_LOCKKEY */
#define _MSC_MASSLOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for MSC_LOCKKEY */
-#define _MSC_MASSLOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for MSC_MASSLOCK */
#define _MSC_MASSLOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for MSC_MASSLOCK */
+#define _MSC_MASSLOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for MSC_MASSLOCK */
#define _MSC_MASSLOCK_LOCKKEY_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_MASSLOCK */
#define _MSC_MASSLOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for MSC_MASSLOCK */
#define _MSC_MASSLOCK_LOCKKEY_UNLOCK 0x0000631AUL /**< Mode UNLOCK for MSC_MASSLOCK */
-#define MSC_MASSLOCK_LOCKKEY_LOCK (_MSC_MASSLOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for MSC_MASSLOCK */
#define MSC_MASSLOCK_LOCKKEY_UNLOCKED (_MSC_MASSLOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for MSC_MASSLOCK */
+#define MSC_MASSLOCK_LOCKKEY_LOCK (_MSC_MASSLOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for MSC_MASSLOCK */
#define MSC_MASSLOCK_LOCKKEY_DEFAULT (_MSC_MASSLOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_MASSLOCK */
#define MSC_MASSLOCK_LOCKKEY_LOCKED (_MSC_MASSLOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for MSC_MASSLOCK */
#define MSC_MASSLOCK_LOCKKEY_UNLOCK (_MSC_MASSLOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for MSC_MASSLOCK */
@@ -586,13 +585,13 @@ typedef struct {
#define _MSC_BANKSWITCHLOCK_MASK 0x0000FFFFUL /**< Mask for MSC_BANKSWITCHLOCK */
#define _MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_SHIFT 0 /**< Shift value for MSC_BANKSWITCHLOCKKEY */
#define _MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_MASK 0xFFFFUL /**< Bit mask for MSC_BANKSWITCHLOCKKEY */
-#define _MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for MSC_BANKSWITCHLOCK */
#define _MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for MSC_BANKSWITCHLOCK */
+#define _MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for MSC_BANKSWITCHLOCK */
#define _MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_BANKSWITCHLOCK */
#define _MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for MSC_BANKSWITCHLOCK */
#define _MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_UNLOCK 0x00007C2BUL /**< Mode UNLOCK for MSC_BANKSWITCHLOCK */
-#define MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_LOCK (_MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_LOCK << 0) /**< Shifted mode LOCK for MSC_BANKSWITCHLOCK */
#define MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_UNLOCKED (_MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for MSC_BANKSWITCHLOCK */
+#define MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_LOCK (_MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_LOCK << 0) /**< Shifted mode LOCK for MSC_BANKSWITCHLOCK */
#define MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_DEFAULT (_MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_BANKSWITCHLOCK */
#define MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_LOCKED (_MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for MSC_BANKSWITCHLOCK */
#define MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_UNLOCK (_MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for MSC_BANKSWITCHLOCK */
diff --git a/cpu/efm32/families/efr32mg12p/include/vendor/efr32mg12p_pcnt.h b/cpu/efm32/families/efr32mg12p/include/vendor/efr32mg12p_pcnt.h
index 0244745cf1..7e3c7a8712 100644
--- a/cpu/efm32/families/efr32mg12p/include/vendor/efr32mg12p_pcnt.h
+++ b/cpu/efm32/families/efr32mg12p/include/vendor/efr32mg12p_pcnt.h
@@ -1,10 +1,9 @@
/***************************************************************************//**
* @file
* @brief EFR32MG12P_PCNT register and bit field definitions
- * @version 5.8.3
*******************************************************************************
* # License
- * Copyright 2019 Silicon Laboratories Inc. www.silabs.com
+ * Copyright 2020 Silicon Laboratories Inc. www.silabs.com
*******************************************************************************
*
* SPDX-License-Identifier: Zlib
diff --git a/cpu/efm32/families/efr32mg12p/include/vendor/efr32mg12p_prs.h b/cpu/efm32/families/efr32mg12p/include/vendor/efr32mg12p_prs.h
index 3f93c92679..2c3035526e 100644
--- a/cpu/efm32/families/efr32mg12p/include/vendor/efr32mg12p_prs.h
+++ b/cpu/efm32/families/efr32mg12p/include/vendor/efr32mg12p_prs.h
@@ -1,10 +1,9 @@
/***************************************************************************//**
* @file
* @brief EFR32MG12P_PRS register and bit field definitions
- * @version 5.8.3
*******************************************************************************
* # License
- * Copyright 2019 Silicon Laboratories Inc. www.silabs.com
+ * Copyright 2020 Silicon Laboratories Inc. www.silabs.com
*******************************************************************************
*
* SPDX-License-Identifier: Zlib
diff --git a/cpu/efm32/families/efr32mg12p/include/vendor/efr32mg12p_prs_ch.h b/cpu/efm32/families/efr32mg12p/include/vendor/efr32mg12p_prs_ch.h
index 7e748f8c77..9cc92be47b 100644
--- a/cpu/efm32/families/efr32mg12p/include/vendor/efr32mg12p_prs_ch.h
+++ b/cpu/efm32/families/efr32mg12p/include/vendor/efr32mg12p_prs_ch.h
@@ -1,10 +1,9 @@
/***************************************************************************//**
* @file
* @brief EFR32MG12P_PRS_CH register and bit field definitions
- * @version 5.8.3
*******************************************************************************
* # License
- * Copyright 2019 Silicon Laboratories Inc. www.silabs.com
+ * Copyright 2020 Silicon Laboratories Inc. www.silabs.com
*******************************************************************************
*
* SPDX-License-Identifier: Zlib
diff --git a/cpu/efm32/families/efr32mg12p/include/vendor/efr32mg12p_prs_signals.h b/cpu/efm32/families/efr32mg12p/include/vendor/efr32mg12p_prs_signals.h
index e988832c1b..d77d26f535 100644
--- a/cpu/efm32/families/efr32mg12p/include/vendor/efr32mg12p_prs_signals.h
+++ b/cpu/efm32/families/efr32mg12p/include/vendor/efr32mg12p_prs_signals.h
@@ -1,10 +1,9 @@
/***************************************************************************//**
* @file
* @brief EFR32MG12P_PRS_SIGNALS register and bit field definitions
- * @version 5.8.3
*******************************************************************************
* # License
- * Copyright 2019 Silicon Laboratories Inc. www.silabs.com
+ * Copyright 2020 Silicon Laboratories Inc. www.silabs.com
*******************************************************************************
*
* SPDX-License-Identifier: Zlib
diff --git a/cpu/efm32/families/efr32mg12p/include/vendor/efr32mg12p_rmu.h b/cpu/efm32/families/efr32mg12p/include/vendor/efr32mg12p_rmu.h
index 65b98dab01..abcf5aba6d 100644
--- a/cpu/efm32/families/efr32mg12p/include/vendor/efr32mg12p_rmu.h
+++ b/cpu/efm32/families/efr32mg12p/include/vendor/efr32mg12p_rmu.h
@@ -1,10 +1,9 @@
/***************************************************************************//**
* @file
* @brief EFR32MG12P_RMU register and bit field definitions
- * @version 5.8.3
*******************************************************************************
* # License
- * Copyright 2019 Silicon Laboratories Inc. www.silabs.com
+ * Copyright 2020 Silicon Laboratories Inc. www.silabs.com
*******************************************************************************
*
* SPDX-License-Identifier: Zlib
@@ -189,13 +188,13 @@ typedef struct {
#define _RMU_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for RMU_LOCKKEY */
#define _RMU_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for RMU_LOCKKEY */
#define _RMU_LOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for RMU_LOCK */
-#define _RMU_LOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for RMU_LOCK */
#define _RMU_LOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for RMU_LOCK */
+#define _RMU_LOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for RMU_LOCK */
#define _RMU_LOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for RMU_LOCK */
#define _RMU_LOCK_LOCKKEY_UNLOCK 0x0000E084UL /**< Mode UNLOCK for RMU_LOCK */
#define RMU_LOCK_LOCKKEY_DEFAULT (_RMU_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for RMU_LOCK */
-#define RMU_LOCK_LOCKKEY_LOCK (_RMU_LOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for RMU_LOCK */
#define RMU_LOCK_LOCKKEY_UNLOCKED (_RMU_LOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for RMU_LOCK */
+#define RMU_LOCK_LOCKKEY_LOCK (_RMU_LOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for RMU_LOCK */
#define RMU_LOCK_LOCKKEY_LOCKED (_RMU_LOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for RMU_LOCK */
#define RMU_LOCK_LOCKKEY_UNLOCK (_RMU_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for RMU_LOCK */
diff --git a/cpu/efm32/families/efr32mg12p/include/vendor/efr32mg12p_romtable.h b/cpu/efm32/families/efr32mg12p/include/vendor/efr32mg12p_romtable.h
index ff59b976f6..04dd3fcfd3 100644
--- a/cpu/efm32/families/efr32mg12p/include/vendor/efr32mg12p_romtable.h
+++ b/cpu/efm32/families/efr32mg12p/include/vendor/efr32mg12p_romtable.h
@@ -1,10 +1,9 @@
/***************************************************************************//**
* @file
* @brief EFR32MG12P_ROMTABLE register and bit field definitions
- * @version 5.8.3
*******************************************************************************
* # License
- * Copyright 2019 Silicon Laboratories Inc. www.silabs.com
+ * Copyright 2020 Silicon Laboratories Inc. www.silabs.com
*******************************************************************************
*
* SPDX-License-Identifier: Zlib
diff --git a/cpu/efm32/families/efr32mg12p/include/vendor/efr32mg12p_rtcc.h b/cpu/efm32/families/efr32mg12p/include/vendor/efr32mg12p_rtcc.h
index c97cde7568..3e45e5d4fc 100644
--- a/cpu/efm32/families/efr32mg12p/include/vendor/efr32mg12p_rtcc.h
+++ b/cpu/efm32/families/efr32mg12p/include/vendor/efr32mg12p_rtcc.h
@@ -1,10 +1,9 @@
/***************************************************************************//**
* @file
* @brief EFR32MG12P_RTCC register and bit field definitions
- * @version 5.8.3
*******************************************************************************
* # License
- * Copyright 2019 Silicon Laboratories Inc. www.silabs.com
+ * Copyright 2020 Silicon Laboratories Inc. www.silabs.com
*******************************************************************************
*
* SPDX-License-Identifier: Zlib
@@ -531,13 +530,13 @@ typedef struct {
#define _RTCC_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for RTCC_LOCKKEY */
#define _RTCC_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for RTCC_LOCKKEY */
#define _RTCC_LOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_LOCK */
-#define _RTCC_LOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for RTCC_LOCK */
#define _RTCC_LOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for RTCC_LOCK */
+#define _RTCC_LOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for RTCC_LOCK */
#define _RTCC_LOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for RTCC_LOCK */
#define _RTCC_LOCK_LOCKKEY_UNLOCK 0x0000AEE8UL /**< Mode UNLOCK for RTCC_LOCK */
#define RTCC_LOCK_LOCKKEY_DEFAULT (_RTCC_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for RTCC_LOCK */
-#define RTCC_LOCK_LOCKKEY_LOCK (_RTCC_LOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for RTCC_LOCK */
#define RTCC_LOCK_LOCKKEY_UNLOCKED (_RTCC_LOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for RTCC_LOCK */
+#define RTCC_LOCK_LOCKKEY_LOCK (_RTCC_LOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for RTCC_LOCK */
#define RTCC_LOCK_LOCKKEY_LOCKED (_RTCC_LOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for RTCC_LOCK */
#define RTCC_LOCK_LOCKKEY_UNLOCK (_RTCC_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for RTCC_LOCK */
diff --git a/cpu/efm32/families/efr32mg12p/include/vendor/efr32mg12p_rtcc_cc.h b/cpu/efm32/families/efr32mg12p/include/vendor/efr32mg12p_rtcc_cc.h
index 4d3f20accc..4204106faf 100644
--- a/cpu/efm32/families/efr32mg12p/include/vendor/efr32mg12p_rtcc_cc.h
+++ b/cpu/efm32/families/efr32mg12p/include/vendor/efr32mg12p_rtcc_cc.h
@@ -1,10 +1,9 @@
/***************************************************************************//**
* @file
* @brief EFR32MG12P_RTCC_CC register and bit field definitions
- * @version 5.8.3
*******************************************************************************
* # License
- * Copyright 2019 Silicon Laboratories Inc. www.silabs.com
+ * Copyright 2020 Silicon Laboratories Inc. www.silabs.com
*******************************************************************************
*
* SPDX-License-Identifier: Zlib
diff --git a/cpu/efm32/families/efr32mg12p/include/vendor/efr32mg12p_rtcc_ret.h b/cpu/efm32/families/efr32mg12p/include/vendor/efr32mg12p_rtcc_ret.h
index 53643b042f..19815d511b 100644
--- a/cpu/efm32/families/efr32mg12p/include/vendor/efr32mg12p_rtcc_ret.h
+++ b/cpu/efm32/families/efr32mg12p/include/vendor/efr32mg12p_rtcc_ret.h
@@ -1,10 +1,9 @@
/***************************************************************************//**
* @file
* @brief EFR32MG12P_RTCC_RET register and bit field definitions
- * @version 5.8.3
*******************************************************************************
* # License
- * Copyright 2019 Silicon Laboratories Inc. www.silabs.com
+ * Copyright 2020 Silicon Laboratories Inc. www.silabs.com
*******************************************************************************
*
* SPDX-License-Identifier: Zlib
diff --git a/cpu/efm32/families/efr32mg12p/include/vendor/efr32mg12p_smu.h b/cpu/efm32/families/efr32mg12p/include/vendor/efr32mg12p_smu.h
index 9b566895b2..5c3ed5fb35 100644
--- a/cpu/efm32/families/efr32mg12p/include/vendor/efr32mg12p_smu.h
+++ b/cpu/efm32/families/efr32mg12p/include/vendor/efr32mg12p_smu.h
@@ -1,10 +1,9 @@
/***************************************************************************//**
* @file
* @brief EFR32MG12P_SMU register and bit field definitions
- * @version 5.8.3
*******************************************************************************
* # License
- * Copyright 2019 Silicon Laboratories Inc. www.silabs.com
+ * Copyright 2020 Silicon Laboratories Inc. www.silabs.com
*******************************************************************************
*
* SPDX-License-Identifier: Zlib
diff --git a/cpu/efm32/families/efr32mg12p/include/vendor/efr32mg12p_timer.h b/cpu/efm32/families/efr32mg12p/include/vendor/efr32mg12p_timer.h
index 82af4ff18e..ee559195c5 100644
--- a/cpu/efm32/families/efr32mg12p/include/vendor/efr32mg12p_timer.h
+++ b/cpu/efm32/families/efr32mg12p/include/vendor/efr32mg12p_timer.h
@@ -1,10 +1,9 @@
/***************************************************************************//**
* @file
* @brief EFR32MG12P_TIMER register and bit field definitions
- * @version 5.8.3
*******************************************************************************
* # License
- * Copyright 2019 Silicon Laboratories Inc. www.silabs.com
+ * Copyright 2020 Silicon Laboratories Inc. www.silabs.com
*******************************************************************************
*
* SPDX-License-Identifier: Zlib
@@ -586,13 +585,13 @@ typedef struct {
#define _TIMER_LOCK_TIMERLOCKKEY_SHIFT 0 /**< Shift value for TIMER_TIMERLOCKKEY */
#define _TIMER_LOCK_TIMERLOCKKEY_MASK 0xFFFFUL /**< Bit mask for TIMER_TIMERLOCKKEY */
#define _TIMER_LOCK_TIMERLOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_LOCK */
-#define _TIMER_LOCK_TIMERLOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for TIMER_LOCK */
#define _TIMER_LOCK_TIMERLOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for TIMER_LOCK */
+#define _TIMER_LOCK_TIMERLOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for TIMER_LOCK */
#define _TIMER_LOCK_TIMERLOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for TIMER_LOCK */
#define _TIMER_LOCK_TIMERLOCKKEY_UNLOCK 0x0000CE80UL /**< Mode UNLOCK for TIMER_LOCK */
#define TIMER_LOCK_TIMERLOCKKEY_DEFAULT (_TIMER_LOCK_TIMERLOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_LOCK */
-#define TIMER_LOCK_TIMERLOCKKEY_LOCK (_TIMER_LOCK_TIMERLOCKKEY_LOCK << 0) /**< Shifted mode LOCK for TIMER_LOCK */
#define TIMER_LOCK_TIMERLOCKKEY_UNLOCKED (_TIMER_LOCK_TIMERLOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for TIMER_LOCK */
+#define TIMER_LOCK_TIMERLOCKKEY_LOCK (_TIMER_LOCK_TIMERLOCKKEY_LOCK << 0) /**< Shifted mode LOCK for TIMER_LOCK */
#define TIMER_LOCK_TIMERLOCKKEY_LOCKED (_TIMER_LOCK_TIMERLOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for TIMER_LOCK */
#define TIMER_LOCK_TIMERLOCKKEY_UNLOCK (_TIMER_LOCK_TIMERLOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for TIMER_LOCK */
@@ -1573,13 +1572,13 @@ typedef struct {
#define _TIMER_DTLOCK_LOCKKEY_SHIFT 0 /**< Shift value for TIMER_LOCKKEY */
#define _TIMER_DTLOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for TIMER_LOCKKEY */
#define _TIMER_DTLOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTLOCK */
-#define _TIMER_DTLOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for TIMER_DTLOCK */
#define _TIMER_DTLOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for TIMER_DTLOCK */
+#define _TIMER_DTLOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for TIMER_DTLOCK */
#define _TIMER_DTLOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for TIMER_DTLOCK */
#define _TIMER_DTLOCK_LOCKKEY_UNLOCK 0x0000CE80UL /**< Mode UNLOCK for TIMER_DTLOCK */
#define TIMER_DTLOCK_LOCKKEY_DEFAULT (_TIMER_DTLOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_DTLOCK */
-#define TIMER_DTLOCK_LOCKKEY_LOCK (_TIMER_DTLOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for TIMER_DTLOCK */
#define TIMER_DTLOCK_LOCKKEY_UNLOCKED (_TIMER_DTLOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for TIMER_DTLOCK */
+#define TIMER_DTLOCK_LOCKKEY_LOCK (_TIMER_DTLOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for TIMER_DTLOCK */
#define TIMER_DTLOCK_LOCKKEY_LOCKED (_TIMER_DTLOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for TIMER_DTLOCK */
#define TIMER_DTLOCK_LOCKKEY_UNLOCK (_TIMER_DTLOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for TIMER_DTLOCK */
diff --git a/cpu/efm32/families/efr32mg12p/include/vendor/efr32mg12p_timer_cc.h b/cpu/efm32/families/efr32mg12p/include/vendor/efr32mg12p_timer_cc.h
index ef234634ab..d59f38cf54 100644
--- a/cpu/efm32/families/efr32mg12p/include/vendor/efr32mg12p_timer_cc.h
+++ b/cpu/efm32/families/efr32mg12p/include/vendor/efr32mg12p_timer_cc.h
@@ -1,10 +1,9 @@
/***************************************************************************//**
* @file
* @brief EFR32MG12P_TIMER_CC register and bit field definitions
- * @version 5.8.3
*******************************************************************************
* # License
- * Copyright 2019 Silicon Laboratories Inc. www.silabs.com
+ * Copyright 2020 Silicon Laboratories Inc. www.silabs.com
*******************************************************************************
*
* SPDX-License-Identifier: Zlib
diff --git a/cpu/efm32/families/efr32mg12p/include/vendor/efr32mg12p_trng.h b/cpu/efm32/families/efr32mg12p/include/vendor/efr32mg12p_trng.h
index 9c92a3a0d8..7522ff9fb7 100644
--- a/cpu/efm32/families/efr32mg12p/include/vendor/efr32mg12p_trng.h
+++ b/cpu/efm32/families/efr32mg12p/include/vendor/efr32mg12p_trng.h
@@ -1,10 +1,9 @@
/***************************************************************************//**
* @file
* @brief EFR32MG12P_TRNG register and bit field definitions
- * @version 5.8.3
*******************************************************************************
* # License
- * Copyright 2019 Silicon Laboratories Inc. www.silabs.com
+ * Copyright 2020 Silicon Laboratories Inc. www.silabs.com
*******************************************************************************
*
* SPDX-License-Identifier: Zlib
diff --git a/cpu/efm32/families/efr32mg12p/include/vendor/efr32mg12p_usart.h b/cpu/efm32/families/efr32mg12p/include/vendor/efr32mg12p_usart.h
index 36a7838c60..ec13dada52 100644
--- a/cpu/efm32/families/efr32mg12p/include/vendor/efr32mg12p_usart.h
+++ b/cpu/efm32/families/efr32mg12p/include/vendor/efr32mg12p_usart.h
@@ -1,10 +1,9 @@
/***************************************************************************//**
* @file
* @brief EFR32MG12P_USART register and bit field definitions
- * @version 5.8.3
*******************************************************************************
* # License
- * Copyright 2019 Silicon Laboratories Inc. www.silabs.com
+ * Copyright 2020 Silicon Laboratories Inc. www.silabs.com
*******************************************************************************
*
* SPDX-License-Identifier: Zlib
diff --git a/cpu/efm32/families/efr32mg12p/include/vendor/efr32mg12p_vdac.h b/cpu/efm32/families/efr32mg12p/include/vendor/efr32mg12p_vdac.h
index 3aef190a9a..1c2a444b24 100644
--- a/cpu/efm32/families/efr32mg12p/include/vendor/efr32mg12p_vdac.h
+++ b/cpu/efm32/families/efr32mg12p/include/vendor/efr32mg12p_vdac.h
@@ -1,10 +1,9 @@
/***************************************************************************//**
* @file
* @brief EFR32MG12P_VDAC register and bit field definitions
- * @version 5.8.3
*******************************************************************************
* # License
- * Copyright 2019 Silicon Laboratories Inc. www.silabs.com
+ * Copyright 2020 Silicon Laboratories Inc. www.silabs.com
*******************************************************************************
*
* SPDX-License-Identifier: Zlib
diff --git a/cpu/efm32/families/efr32mg12p/include/vendor/efr32mg12p_vdac_opa.h b/cpu/efm32/families/efr32mg12p/include/vendor/efr32mg12p_vdac_opa.h
index 5edc0f440a..ebf52b17a9 100644
--- a/cpu/efm32/families/efr32mg12p/include/vendor/efr32mg12p_vdac_opa.h
+++ b/cpu/efm32/families/efr32mg12p/include/vendor/efr32mg12p_vdac_opa.h
@@ -1,10 +1,9 @@
/***************************************************************************//**
* @file
* @brief EFR32MG12P_VDAC_OPA register and bit field definitions
- * @version 5.8.3
*******************************************************************************
* # License
- * Copyright 2019 Silicon Laboratories Inc. www.silabs.com
+ * Copyright 2020 Silicon Laboratories Inc. www.silabs.com
*******************************************************************************
*
* SPDX-License-Identifier: Zlib
diff --git a/cpu/efm32/families/efr32mg12p/include/vendor/efr32mg12p_wdog.h b/cpu/efm32/families/efr32mg12p/include/vendor/efr32mg12p_wdog.h
index 817212c48b..55319b9a92 100644
--- a/cpu/efm32/families/efr32mg12p/include/vendor/efr32mg12p_wdog.h
+++ b/cpu/efm32/families/efr32mg12p/include/vendor/efr32mg12p_wdog.h
@@ -1,10 +1,9 @@
/***************************************************************************//**
* @file
* @brief EFR32MG12P_WDOG register and bit field definitions
- * @version 5.8.3
*******************************************************************************
* # License
- * Copyright 2019 Silicon Laboratories Inc. www.silabs.com
+ * Copyright 2020 Silicon Laboratories Inc. www.silabs.com
*******************************************************************************
*
* SPDX-License-Identifier: Zlib
diff --git a/cpu/efm32/families/efr32mg12p/include/vendor/efr32mg12p_wdog_pch.h b/cpu/efm32/families/efr32mg12p/include/vendor/efr32mg12p_wdog_pch.h
index 4e75f54c9f..3fa4fec9c2 100644
--- a/cpu/efm32/families/efr32mg12p/include/vendor/efr32mg12p_wdog_pch.h
+++ b/cpu/efm32/families/efr32mg12p/include/vendor/efr32mg12p_wdog_pch.h
@@ -1,10 +1,9 @@
/***************************************************************************//**
* @file
* @brief EFR32MG12P_WDOG_PCH register and bit field definitions
- * @version 5.8.3
*******************************************************************************
* # License
- * Copyright 2019 Silicon Laboratories Inc. www.silabs.com
+ * Copyright 2020 Silicon Laboratories Inc. www.silabs.com
*******************************************************************************
*
* SPDX-License-Identifier: Zlib
diff --git a/cpu/efm32/families/efr32mg12p/include/vendor/em_device.h b/cpu/efm32/families/efr32mg12p/include/vendor/em_device.h
index e097d7965c..e698ff61c5 100644
--- a/cpu/efm32/families/efr32mg12p/include/vendor/em_device.h
+++ b/cpu/efm32/families/efr32mg12p/include/vendor/em_device.h
@@ -11,10 +11,9 @@
* Add "#include "em_device.h" to your source files
* @endverbatim
*
- * @version 5.8.3
*******************************************************************************
* # License
- * Copyright 2019 Silicon Laboratories Inc. www.silabs.com
+ * Copyright 2020 Silicon Laboratories Inc. www.silabs.com
*******************************************************************************
*
* SPDX-License-Identifier: Zlib
diff --git a/cpu/efm32/families/efr32mg12p/include/vendor/system_efr32mg12p.h b/cpu/efm32/families/efr32mg12p/include/vendor/system_efr32mg12p.h
index 9938edaebb..4cb09cb0d5 100644
--- a/cpu/efm32/families/efr32mg12p/include/vendor/system_efr32mg12p.h
+++ b/cpu/efm32/families/efr32mg12p/include/vendor/system_efr32mg12p.h
@@ -1,10 +1,9 @@
/***************************************************************************//**
* @file
* @brief CMSIS Cortex-M3/M4 System Layer for EFR32 devices.
- * @version 5.8.3
*******************************************************************************
* # License
- * Copyright 2019 Silicon Laboratories Inc. www.silabs.com
+ * Copyright 2020 Silicon Laboratories Inc. www.silabs.com
*******************************************************************************
*
* SPDX-License-Identifier: Zlib
@@ -47,12 +46,29 @@ extern "C" {
* @{
******************************************************************************/
+/*******************************************************************************
+ ****************************** TYPEDEFS ***********************************
+ ******************************************************************************/
+
+/* Interrupt vectortable entry */
+typedef union {
+ void (*pFunc)(void);
+ void *topOfStack;
+} tVectorEntry;
+
/*******************************************************************************
************************** GLOBAL VARIABLES *******************************
******************************************************************************/
-extern uint32_t SystemCoreClock; /**< System Clock Frequency (Core Clock) */
-extern uint32_t SystemHfrcoFreq; /**< System HFRCO frequency */
+extern uint32_t SystemCoreClock; /**< System Clock Frequency (Core Clock) */
+extern uint32_t SystemHfrcoFreq; /**< System HFRCO frequency */
+
+#if defined(__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+#if defined(__ICCARM__) /* IAR requires the __vector_table symbol */
+#define __Vectors __vector_table
+#endif
+extern const tVectorEntry __Vectors[];
+#endif
/*******************************************************************************
***************************** PROTOTYPES **********************************
diff --git a/cpu/efm32/families/efr32mg12p/system.c b/cpu/efm32/families/efr32mg12p/system.c
index d536d23dfc..f8341d0972 100644
--- a/cpu/efm32/families/efr32mg12p/system.c
+++ b/cpu/efm32/families/efr32mg12p/system.c
@@ -1,10 +1,9 @@
/***************************************************************************//**
* @file
* @brief CMSIS Cortex-M3/M4 System Layer for EFR32 devices.
- * @version 5.8.3
*******************************************************************************
* # License
- * Copyright 2019 Silicon Laboratories Inc. www.silabs.com
+ * Copyright 2020 Silicon Laboratories Inc. www.silabs.com
*******************************************************************************
*
* SPDX-License-Identifier: Zlib
@@ -117,13 +116,6 @@ uint32_t SystemHfrcoFreq = EFR32_HFRCO_STARTUP_FREQ;
************************** GLOBAL FUNCTIONS *******************************
******************************************************************************/
-#if defined(__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
-#if defined(__ICCARM__) /* IAR requires the __vector_table symbol */
-#define __Vectors __vector_table
-#endif
-extern uint32_t __Vectors;
-#endif
-
/***************************************************************************//**
* @brief
* Get the current core clock frequency.
@@ -215,6 +207,10 @@ uint32_t SystemHFClockGet(void)
#endif
break;
+ case CMU_HFCLKSTATUS_SELECTED_HFRCODIV2:
+ ret = SystemHfrcoFreq / 2;
+ break;
+
default: /* CMU_HFCLKSTATUS_SELECTED_HFRCO */
ret = SystemHfrcoFreq;
break;
diff --git a/cpu/efm32/families/efr32mg1p/include/vendor/efr32mg1p132f256gm32.h b/cpu/efm32/families/efr32mg1p/include/vendor/efr32mg1p132f256gm32.h
index 991e2953ab..43d6a666f8 100644
--- a/cpu/efm32/families/efr32mg1p/include/vendor/efr32mg1p132f256gm32.h
+++ b/cpu/efm32/families/efr32mg1p/include/vendor/efr32mg1p132f256gm32.h
@@ -2,10 +2,9 @@
* @file
* @brief CMSIS Cortex-M Peripheral Access Layer Header File
* for EFR32MG1P132F256GM32
- * @version 5.8.3
*******************************************************************************
* # License
- * Copyright 2019 Silicon Laboratories Inc. www.silabs.com
+ * Copyright 2020 Silicon Laboratories Inc. www.silabs.com
*******************************************************************************
*
* SPDX-License-Identifier: Zlib
@@ -149,42 +148,42 @@ typedef enum IRQn{
#define PART_NUMBER "EFR32MG1P132F256GM32" /**< Part Number */
/** Memory Base addresses and limits */
-#define FLASH_MEM_BASE (0x00000000UL) /**< FLASH base address */
-#define FLASH_MEM_SIZE (0x10000000UL) /**< FLASH available address space */
-#define FLASH_MEM_END (0x0FFFFFFFUL) /**< FLASH end address */
-#define FLASH_MEM_BITS (0x0000001CUL) /**< FLASH used bits */
-#define RAM_CODE_MEM_BASE (0x10000000UL) /**< RAM_CODE base address */
-#define RAM_CODE_MEM_SIZE (0x7C00UL) /**< RAM_CODE available address space */
-#define RAM_CODE_MEM_END (0x10007BFFUL) /**< RAM_CODE end address */
-#define RAM_CODE_MEM_BITS (0x0000000FUL) /**< RAM_CODE used bits */
-#define PER_BITCLR_MEM_BASE (0x44000000UL) /**< PER_BITCLR base address */
-#define PER_BITCLR_MEM_SIZE (0xE8000UL) /**< PER_BITCLR available address space */
-#define PER_BITCLR_MEM_END (0x440E7FFFUL) /**< PER_BITCLR end address */
-#define PER_BITCLR_MEM_BITS (0x00000014UL) /**< PER_BITCLR used bits */
-#define CRYPTO_BITSET_MEM_BASE (0x460F0000UL) /**< CRYPTO_BITSET base address */
-#define CRYPTO_BITSET_MEM_SIZE (0x400UL) /**< CRYPTO_BITSET available address space */
-#define CRYPTO_BITSET_MEM_END (0x460F03FFUL) /**< CRYPTO_BITSET end address */
-#define CRYPTO_BITSET_MEM_BITS (0x0000000AUL) /**< CRYPTO_BITSET used bits */
#define CRYPTO_MEM_BASE (0x400F0000UL) /**< CRYPTO base address */
#define CRYPTO_MEM_SIZE (0x400UL) /**< CRYPTO available address space */
#define CRYPTO_MEM_END (0x400F03FFUL) /**< CRYPTO end address */
#define CRYPTO_MEM_BITS (0x0000000AUL) /**< CRYPTO used bits */
-#define CRYPTO_BITCLR_MEM_BASE (0x440F0000UL) /**< CRYPTO_BITCLR base address */
-#define CRYPTO_BITCLR_MEM_SIZE (0x400UL) /**< CRYPTO_BITCLR available address space */
-#define CRYPTO_BITCLR_MEM_END (0x440F03FFUL) /**< CRYPTO_BITCLR end address */
-#define CRYPTO_BITCLR_MEM_BITS (0x0000000AUL) /**< CRYPTO_BITCLR used bits */
-#define PER_BITSET_MEM_BASE (0x46000000UL) /**< PER_BITSET base address */
-#define PER_BITSET_MEM_SIZE (0xE8000UL) /**< PER_BITSET available address space */
-#define PER_BITSET_MEM_END (0x460E7FFFUL) /**< PER_BITSET end address */
-#define PER_BITSET_MEM_BITS (0x00000014UL) /**< PER_BITSET used bits */
-#define PER_MEM_BASE (0x40000000UL) /**< PER base address */
-#define PER_MEM_SIZE (0xE8000UL) /**< PER available address space */
-#define PER_MEM_END (0x400E7FFFUL) /**< PER end address */
-#define PER_MEM_BITS (0x00000014UL) /**< PER used bits */
#define RAM_MEM_BASE (0x20000000UL) /**< RAM base address */
#define RAM_MEM_SIZE (0x7C00UL) /**< RAM available address space */
#define RAM_MEM_END (0x20007BFFUL) /**< RAM end address */
#define RAM_MEM_BITS (0x0000000FUL) /**< RAM used bits */
+#define PER_BITSET_MEM_BASE (0x46000000UL) /**< PER_BITSET base address */
+#define PER_BITSET_MEM_SIZE (0xE8000UL) /**< PER_BITSET available address space */
+#define PER_BITSET_MEM_END (0x460E7FFFUL) /**< PER_BITSET end address */
+#define PER_BITSET_MEM_BITS (0x00000014UL) /**< PER_BITSET used bits */
+#define CRYPTO_BITSET_MEM_BASE (0x460F0000UL) /**< CRYPTO_BITSET base address */
+#define CRYPTO_BITSET_MEM_SIZE (0x400UL) /**< CRYPTO_BITSET available address space */
+#define CRYPTO_BITSET_MEM_END (0x460F03FFUL) /**< CRYPTO_BITSET end address */
+#define CRYPTO_BITSET_MEM_BITS (0x0000000AUL) /**< CRYPTO_BITSET used bits */
+#define PER_MEM_BASE (0x40000000UL) /**< PER base address */
+#define PER_MEM_SIZE (0xE8000UL) /**< PER available address space */
+#define PER_MEM_END (0x400E7FFFUL) /**< PER end address */
+#define PER_MEM_BITS (0x00000014UL) /**< PER used bits */
+#define CRYPTO_BITCLR_MEM_BASE (0x440F0000UL) /**< CRYPTO_BITCLR base address */
+#define CRYPTO_BITCLR_MEM_SIZE (0x400UL) /**< CRYPTO_BITCLR available address space */
+#define CRYPTO_BITCLR_MEM_END (0x440F03FFUL) /**< CRYPTO_BITCLR end address */
+#define CRYPTO_BITCLR_MEM_BITS (0x0000000AUL) /**< CRYPTO_BITCLR used bits */
+#define RAM_CODE_MEM_BASE (0x10000000UL) /**< RAM_CODE base address */
+#define RAM_CODE_MEM_SIZE (0x7C00UL) /**< RAM_CODE available address space */
+#define RAM_CODE_MEM_END (0x10007BFFUL) /**< RAM_CODE end address */
+#define RAM_CODE_MEM_BITS (0x0000000FUL) /**< RAM_CODE used bits */
+#define FLASH_MEM_BASE (0x00000000UL) /**< FLASH base address */
+#define FLASH_MEM_SIZE (0x10000000UL) /**< FLASH available address space */
+#define FLASH_MEM_END (0x0FFFFFFFUL) /**< FLASH end address */
+#define FLASH_MEM_BITS (0x0000001CUL) /**< FLASH used bits */
+#define PER_BITCLR_MEM_BASE (0x44000000UL) /**< PER_BITCLR base address */
+#define PER_BITCLR_MEM_SIZE (0xE8000UL) /**< PER_BITCLR available address space */
+#define PER_BITCLR_MEM_END (0x440E7FFFUL) /**< PER_BITCLR end address */
+#define PER_BITCLR_MEM_BITS (0x00000014UL) /**< PER_BITCLR used bits */
/** Bit banding area */
#define BITBAND_PER_BASE (0x42000000UL) /**< Peripheral Address Space bit-band area */
diff --git a/cpu/efm32/families/efr32mg1p/include/vendor/efr32mg1p132f256gm48.h b/cpu/efm32/families/efr32mg1p/include/vendor/efr32mg1p132f256gm48.h
index f41d360eb3..4271a8eeaa 100644
--- a/cpu/efm32/families/efr32mg1p/include/vendor/efr32mg1p132f256gm48.h
+++ b/cpu/efm32/families/efr32mg1p/include/vendor/efr32mg1p132f256gm48.h
@@ -2,10 +2,9 @@
* @file
* @brief CMSIS Cortex-M Peripheral Access Layer Header File
* for EFR32MG1P132F256GM48
- * @version 5.8.3
*******************************************************************************
* # License
- * Copyright 2019 Silicon Laboratories Inc. www.silabs.com
+ * Copyright 2020 Silicon Laboratories Inc. www.silabs.com
*******************************************************************************
*
* SPDX-License-Identifier: Zlib
@@ -149,42 +148,42 @@ typedef enum IRQn{
#define PART_NUMBER "EFR32MG1P132F256GM48" /**< Part Number */
/** Memory Base addresses and limits */
-#define FLASH_MEM_BASE (0x00000000UL) /**< FLASH base address */
-#define FLASH_MEM_SIZE (0x10000000UL) /**< FLASH available address space */
-#define FLASH_MEM_END (0x0FFFFFFFUL) /**< FLASH end address */
-#define FLASH_MEM_BITS (0x0000001CUL) /**< FLASH used bits */
-#define RAM_CODE_MEM_BASE (0x10000000UL) /**< RAM_CODE base address */
-#define RAM_CODE_MEM_SIZE (0x7C00UL) /**< RAM_CODE available address space */
-#define RAM_CODE_MEM_END (0x10007BFFUL) /**< RAM_CODE end address */
-#define RAM_CODE_MEM_BITS (0x0000000FUL) /**< RAM_CODE used bits */
-#define PER_BITCLR_MEM_BASE (0x44000000UL) /**< PER_BITCLR base address */
-#define PER_BITCLR_MEM_SIZE (0xE8000UL) /**< PER_BITCLR available address space */
-#define PER_BITCLR_MEM_END (0x440E7FFFUL) /**< PER_BITCLR end address */
-#define PER_BITCLR_MEM_BITS (0x00000014UL) /**< PER_BITCLR used bits */
-#define CRYPTO_BITSET_MEM_BASE (0x460F0000UL) /**< CRYPTO_BITSET base address */
-#define CRYPTO_BITSET_MEM_SIZE (0x400UL) /**< CRYPTO_BITSET available address space */
-#define CRYPTO_BITSET_MEM_END (0x460F03FFUL) /**< CRYPTO_BITSET end address */
-#define CRYPTO_BITSET_MEM_BITS (0x0000000AUL) /**< CRYPTO_BITSET used bits */
#define CRYPTO_MEM_BASE (0x400F0000UL) /**< CRYPTO base address */
#define CRYPTO_MEM_SIZE (0x400UL) /**< CRYPTO available address space */
#define CRYPTO_MEM_END (0x400F03FFUL) /**< CRYPTO end address */
#define CRYPTO_MEM_BITS (0x0000000AUL) /**< CRYPTO used bits */
-#define CRYPTO_BITCLR_MEM_BASE (0x440F0000UL) /**< CRYPTO_BITCLR base address */
-#define CRYPTO_BITCLR_MEM_SIZE (0x400UL) /**< CRYPTO_BITCLR available address space */
-#define CRYPTO_BITCLR_MEM_END (0x440F03FFUL) /**< CRYPTO_BITCLR end address */
-#define CRYPTO_BITCLR_MEM_BITS (0x0000000AUL) /**< CRYPTO_BITCLR used bits */
-#define PER_BITSET_MEM_BASE (0x46000000UL) /**< PER_BITSET base address */
-#define PER_BITSET_MEM_SIZE (0xE8000UL) /**< PER_BITSET available address space */
-#define PER_BITSET_MEM_END (0x460E7FFFUL) /**< PER_BITSET end address */
-#define PER_BITSET_MEM_BITS (0x00000014UL) /**< PER_BITSET used bits */
-#define PER_MEM_BASE (0x40000000UL) /**< PER base address */
-#define PER_MEM_SIZE (0xE8000UL) /**< PER available address space */
-#define PER_MEM_END (0x400E7FFFUL) /**< PER end address */
-#define PER_MEM_BITS (0x00000014UL) /**< PER used bits */
#define RAM_MEM_BASE (0x20000000UL) /**< RAM base address */
#define RAM_MEM_SIZE (0x7C00UL) /**< RAM available address space */
#define RAM_MEM_END (0x20007BFFUL) /**< RAM end address */
#define RAM_MEM_BITS (0x0000000FUL) /**< RAM used bits */
+#define PER_BITSET_MEM_BASE (0x46000000UL) /**< PER_BITSET base address */
+#define PER_BITSET_MEM_SIZE (0xE8000UL) /**< PER_BITSET available address space */
+#define PER_BITSET_MEM_END (0x460E7FFFUL) /**< PER_BITSET end address */
+#define PER_BITSET_MEM_BITS (0x00000014UL) /**< PER_BITSET used bits */
+#define CRYPTO_BITSET_MEM_BASE (0x460F0000UL) /**< CRYPTO_BITSET base address */
+#define CRYPTO_BITSET_MEM_SIZE (0x400UL) /**< CRYPTO_BITSET available address space */
+#define CRYPTO_BITSET_MEM_END (0x460F03FFUL) /**< CRYPTO_BITSET end address */
+#define CRYPTO_BITSET_MEM_BITS (0x0000000AUL) /**< CRYPTO_BITSET used bits */
+#define PER_MEM_BASE (0x40000000UL) /**< PER base address */
+#define PER_MEM_SIZE (0xE8000UL) /**< PER available address space */
+#define PER_MEM_END (0x400E7FFFUL) /**< PER end address */
+#define PER_MEM_BITS (0x00000014UL) /**< PER used bits */
+#define CRYPTO_BITCLR_MEM_BASE (0x440F0000UL) /**< CRYPTO_BITCLR base address */
+#define CRYPTO_BITCLR_MEM_SIZE (0x400UL) /**< CRYPTO_BITCLR available address space */
+#define CRYPTO_BITCLR_MEM_END (0x440F03FFUL) /**< CRYPTO_BITCLR end address */
+#define CRYPTO_BITCLR_MEM_BITS (0x0000000AUL) /**< CRYPTO_BITCLR used bits */
+#define RAM_CODE_MEM_BASE (0x10000000UL) /**< RAM_CODE base address */
+#define RAM_CODE_MEM_SIZE (0x7C00UL) /**< RAM_CODE available address space */
+#define RAM_CODE_MEM_END (0x10007BFFUL) /**< RAM_CODE end address */
+#define RAM_CODE_MEM_BITS (0x0000000FUL) /**< RAM_CODE used bits */
+#define FLASH_MEM_BASE (0x00000000UL) /**< FLASH base address */
+#define FLASH_MEM_SIZE (0x10000000UL) /**< FLASH available address space */
+#define FLASH_MEM_END (0x0FFFFFFFUL) /**< FLASH end address */
+#define FLASH_MEM_BITS (0x0000001CUL) /**< FLASH used bits */
+#define PER_BITCLR_MEM_BASE (0x44000000UL) /**< PER_BITCLR base address */
+#define PER_BITCLR_MEM_SIZE (0xE8000UL) /**< PER_BITCLR available address space */
+#define PER_BITCLR_MEM_END (0x440E7FFFUL) /**< PER_BITCLR end address */
+#define PER_BITCLR_MEM_BITS (0x00000014UL) /**< PER_BITCLR used bits */
/** Bit banding area */
#define BITBAND_PER_BASE (0x42000000UL) /**< Peripheral Address Space bit-band area */
diff --git a/cpu/efm32/families/efr32mg1p/include/vendor/efr32mg1p233f256gm48.h b/cpu/efm32/families/efr32mg1p/include/vendor/efr32mg1p233f256gm48.h
index 0e6f3ed9ae..dd26da3b6b 100644
--- a/cpu/efm32/families/efr32mg1p/include/vendor/efr32mg1p233f256gm48.h
+++ b/cpu/efm32/families/efr32mg1p/include/vendor/efr32mg1p233f256gm48.h
@@ -2,10 +2,9 @@
* @file
* @brief CMSIS Cortex-M Peripheral Access Layer Header File
* for EFR32MG1P233F256GM48
- * @version 5.8.3
*******************************************************************************
* # License
- * Copyright 2019 Silicon Laboratories Inc. www.silabs.com
+ * Copyright 2020 Silicon Laboratories Inc. www.silabs.com
*******************************************************************************
*
* SPDX-License-Identifier: Zlib
@@ -149,42 +148,42 @@ typedef enum IRQn{
#define PART_NUMBER "EFR32MG1P233F256GM48" /**< Part Number */
/** Memory Base addresses and limits */
-#define FLASH_MEM_BASE (0x00000000UL) /**< FLASH base address */
-#define FLASH_MEM_SIZE (0x10000000UL) /**< FLASH available address space */
-#define FLASH_MEM_END (0x0FFFFFFFUL) /**< FLASH end address */
-#define FLASH_MEM_BITS (0x0000001CUL) /**< FLASH used bits */
-#define RAM_CODE_MEM_BASE (0x10000000UL) /**< RAM_CODE base address */
-#define RAM_CODE_MEM_SIZE (0x7C00UL) /**< RAM_CODE available address space */
-#define RAM_CODE_MEM_END (0x10007BFFUL) /**< RAM_CODE end address */
-#define RAM_CODE_MEM_BITS (0x0000000FUL) /**< RAM_CODE used bits */
-#define PER_BITCLR_MEM_BASE (0x44000000UL) /**< PER_BITCLR base address */
-#define PER_BITCLR_MEM_SIZE (0xE8000UL) /**< PER_BITCLR available address space */
-#define PER_BITCLR_MEM_END (0x440E7FFFUL) /**< PER_BITCLR end address */
-#define PER_BITCLR_MEM_BITS (0x00000014UL) /**< PER_BITCLR used bits */
-#define CRYPTO_BITSET_MEM_BASE (0x460F0000UL) /**< CRYPTO_BITSET base address */
-#define CRYPTO_BITSET_MEM_SIZE (0x400UL) /**< CRYPTO_BITSET available address space */
-#define CRYPTO_BITSET_MEM_END (0x460F03FFUL) /**< CRYPTO_BITSET end address */
-#define CRYPTO_BITSET_MEM_BITS (0x0000000AUL) /**< CRYPTO_BITSET used bits */
#define CRYPTO_MEM_BASE (0x400F0000UL) /**< CRYPTO base address */
#define CRYPTO_MEM_SIZE (0x400UL) /**< CRYPTO available address space */
#define CRYPTO_MEM_END (0x400F03FFUL) /**< CRYPTO end address */
#define CRYPTO_MEM_BITS (0x0000000AUL) /**< CRYPTO used bits */
-#define CRYPTO_BITCLR_MEM_BASE (0x440F0000UL) /**< CRYPTO_BITCLR base address */
-#define CRYPTO_BITCLR_MEM_SIZE (0x400UL) /**< CRYPTO_BITCLR available address space */
-#define CRYPTO_BITCLR_MEM_END (0x440F03FFUL) /**< CRYPTO_BITCLR end address */
-#define CRYPTO_BITCLR_MEM_BITS (0x0000000AUL) /**< CRYPTO_BITCLR used bits */
-#define PER_BITSET_MEM_BASE (0x46000000UL) /**< PER_BITSET base address */
-#define PER_BITSET_MEM_SIZE (0xE8000UL) /**< PER_BITSET available address space */
-#define PER_BITSET_MEM_END (0x460E7FFFUL) /**< PER_BITSET end address */
-#define PER_BITSET_MEM_BITS (0x00000014UL) /**< PER_BITSET used bits */
-#define PER_MEM_BASE (0x40000000UL) /**< PER base address */
-#define PER_MEM_SIZE (0xE8000UL) /**< PER available address space */
-#define PER_MEM_END (0x400E7FFFUL) /**< PER end address */
-#define PER_MEM_BITS (0x00000014UL) /**< PER used bits */
#define RAM_MEM_BASE (0x20000000UL) /**< RAM base address */
#define RAM_MEM_SIZE (0x7C00UL) /**< RAM available address space */
#define RAM_MEM_END (0x20007BFFUL) /**< RAM end address */
#define RAM_MEM_BITS (0x0000000FUL) /**< RAM used bits */
+#define PER_BITSET_MEM_BASE (0x46000000UL) /**< PER_BITSET base address */
+#define PER_BITSET_MEM_SIZE (0xE8000UL) /**< PER_BITSET available address space */
+#define PER_BITSET_MEM_END (0x460E7FFFUL) /**< PER_BITSET end address */
+#define PER_BITSET_MEM_BITS (0x00000014UL) /**< PER_BITSET used bits */
+#define CRYPTO_BITSET_MEM_BASE (0x460F0000UL) /**< CRYPTO_BITSET base address */
+#define CRYPTO_BITSET_MEM_SIZE (0x400UL) /**< CRYPTO_BITSET available address space */
+#define CRYPTO_BITSET_MEM_END (0x460F03FFUL) /**< CRYPTO_BITSET end address */
+#define CRYPTO_BITSET_MEM_BITS (0x0000000AUL) /**< CRYPTO_BITSET used bits */
+#define PER_MEM_BASE (0x40000000UL) /**< PER base address */
+#define PER_MEM_SIZE (0xE8000UL) /**< PER available address space */
+#define PER_MEM_END (0x400E7FFFUL) /**< PER end address */
+#define PER_MEM_BITS (0x00000014UL) /**< PER used bits */
+#define CRYPTO_BITCLR_MEM_BASE (0x440F0000UL) /**< CRYPTO_BITCLR base address */
+#define CRYPTO_BITCLR_MEM_SIZE (0x400UL) /**< CRYPTO_BITCLR available address space */
+#define CRYPTO_BITCLR_MEM_END (0x440F03FFUL) /**< CRYPTO_BITCLR end address */
+#define CRYPTO_BITCLR_MEM_BITS (0x0000000AUL) /**< CRYPTO_BITCLR used bits */
+#define RAM_CODE_MEM_BASE (0x10000000UL) /**< RAM_CODE base address */
+#define RAM_CODE_MEM_SIZE (0x7C00UL) /**< RAM_CODE available address space */
+#define RAM_CODE_MEM_END (0x10007BFFUL) /**< RAM_CODE end address */
+#define RAM_CODE_MEM_BITS (0x0000000FUL) /**< RAM_CODE used bits */
+#define FLASH_MEM_BASE (0x00000000UL) /**< FLASH base address */
+#define FLASH_MEM_SIZE (0x10000000UL) /**< FLASH available address space */
+#define FLASH_MEM_END (0x0FFFFFFFUL) /**< FLASH end address */
+#define FLASH_MEM_BITS (0x0000001CUL) /**< FLASH used bits */
+#define PER_BITCLR_MEM_BASE (0x44000000UL) /**< PER_BITCLR base address */
+#define PER_BITCLR_MEM_SIZE (0xE8000UL) /**< PER_BITCLR available address space */
+#define PER_BITCLR_MEM_END (0x440E7FFFUL) /**< PER_BITCLR end address */
+#define PER_BITCLR_MEM_BITS (0x00000014UL) /**< PER_BITCLR used bits */
/** Bit banding area */
#define BITBAND_PER_BASE (0x42000000UL) /**< Peripheral Address Space bit-band area */
diff --git a/cpu/efm32/families/efr32mg1p/include/vendor/efr32mg1p_acmp.h b/cpu/efm32/families/efr32mg1p/include/vendor/efr32mg1p_acmp.h
index 5e133ff282..5b5ad7e52d 100644
--- a/cpu/efm32/families/efr32mg1p/include/vendor/efr32mg1p_acmp.h
+++ b/cpu/efm32/families/efr32mg1p/include/vendor/efr32mg1p_acmp.h
@@ -1,10 +1,9 @@
/***************************************************************************//**
* @file
* @brief EFR32MG1P_ACMP register and bit field definitions
- * @version 5.8.3
*******************************************************************************
* # License
- * Copyright 2019 Silicon Laboratories Inc. www.silabs.com
+ * Copyright 2020 Silicon Laboratories Inc. www.silabs.com
*******************************************************************************
*
* SPDX-License-Identifier: Zlib
@@ -324,6 +323,8 @@ typedef struct {
#define _ACMP_INPUTSEL_POSSEL_APORT4XCH11 0x0000008BUL /**< Mode APORT4XCH11 for ACMP_INPUTSEL */
#define _ACMP_INPUTSEL_POSSEL_APORT4YCH12 0x0000008CUL /**< Mode APORT4YCH12 for ACMP_INPUTSEL */
#define _ACMP_INPUTSEL_POSSEL_APORT4XCH13 0x0000008DUL /**< Mode APORT4XCH13 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_POSSEL_APORT4YCH14 0x0000008EUL /**< Mode APORT4YCH14 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_POSSEL_APORT4XCH15 0x0000008FUL /**< Mode APORT4XCH15 for ACMP_INPUTSEL */
#define _ACMP_INPUTSEL_POSSEL_APORT4YCH16 0x00000090UL /**< Mode APORT4YCH16 for ACMP_INPUTSEL */
#define _ACMP_INPUTSEL_POSSEL_APORT4XCH17 0x00000091UL /**< Mode APORT4XCH17 for ACMP_INPUTSEL */
#define _ACMP_INPUTSEL_POSSEL_APORT4YCH18 0x00000092UL /**< Mode APORT4YCH18 for ACMP_INPUTSEL */
@@ -339,8 +340,6 @@ typedef struct {
#define _ACMP_INPUTSEL_POSSEL_APORT4YCH28 0x0000009CUL /**< Mode APORT4YCH28 for ACMP_INPUTSEL */
#define _ACMP_INPUTSEL_POSSEL_APORT4XCH29 0x0000009DUL /**< Mode APORT4XCH29 for ACMP_INPUTSEL */
#define _ACMP_INPUTSEL_POSSEL_APORT4YCH30 0x0000009EUL /**< Mode APORT4YCH30 for ACMP_INPUTSEL */
-#define _ACMP_INPUTSEL_POSSEL_APORT4YCH14 0x0000009EUL /**< Mode APORT4YCH14 for ACMP_INPUTSEL */
-#define _ACMP_INPUTSEL_POSSEL_APORT4XCH15 0x0000009FUL /**< Mode APORT4XCH15 for ACMP_INPUTSEL */
#define _ACMP_INPUTSEL_POSSEL_APORT4XCH31 0x0000009FUL /**< Mode APORT4XCH31 for ACMP_INPUTSEL */
#define _ACMP_INPUTSEL_POSSEL_VLP 0x000000FBUL /**< Mode VLP for ACMP_INPUTSEL */
#define _ACMP_INPUTSEL_POSSEL_VBDIV 0x000000FCUL /**< Mode VBDIV for ACMP_INPUTSEL */
@@ -490,6 +489,8 @@ typedef struct {
#define ACMP_INPUTSEL_POSSEL_APORT4XCH11 (_ACMP_INPUTSEL_POSSEL_APORT4XCH11 << 0) /**< Shifted mode APORT4XCH11 for ACMP_INPUTSEL */
#define ACMP_INPUTSEL_POSSEL_APORT4YCH12 (_ACMP_INPUTSEL_POSSEL_APORT4YCH12 << 0) /**< Shifted mode APORT4YCH12 for ACMP_INPUTSEL */
#define ACMP_INPUTSEL_POSSEL_APORT4XCH13 (_ACMP_INPUTSEL_POSSEL_APORT4XCH13 << 0) /**< Shifted mode APORT4XCH13 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_POSSEL_APORT4YCH14 (_ACMP_INPUTSEL_POSSEL_APORT4YCH14 << 0) /**< Shifted mode APORT4YCH14 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_POSSEL_APORT4XCH15 (_ACMP_INPUTSEL_POSSEL_APORT4XCH15 << 0) /**< Shifted mode APORT4XCH15 for ACMP_INPUTSEL */
#define ACMP_INPUTSEL_POSSEL_APORT4YCH16 (_ACMP_INPUTSEL_POSSEL_APORT4YCH16 << 0) /**< Shifted mode APORT4YCH16 for ACMP_INPUTSEL */
#define ACMP_INPUTSEL_POSSEL_APORT4XCH17 (_ACMP_INPUTSEL_POSSEL_APORT4XCH17 << 0) /**< Shifted mode APORT4XCH17 for ACMP_INPUTSEL */
#define ACMP_INPUTSEL_POSSEL_APORT4YCH18 (_ACMP_INPUTSEL_POSSEL_APORT4YCH18 << 0) /**< Shifted mode APORT4YCH18 for ACMP_INPUTSEL */
@@ -505,8 +506,6 @@ typedef struct {
#define ACMP_INPUTSEL_POSSEL_APORT4YCH28 (_ACMP_INPUTSEL_POSSEL_APORT4YCH28 << 0) /**< Shifted mode APORT4YCH28 for ACMP_INPUTSEL */
#define ACMP_INPUTSEL_POSSEL_APORT4XCH29 (_ACMP_INPUTSEL_POSSEL_APORT4XCH29 << 0) /**< Shifted mode APORT4XCH29 for ACMP_INPUTSEL */
#define ACMP_INPUTSEL_POSSEL_APORT4YCH30 (_ACMP_INPUTSEL_POSSEL_APORT4YCH30 << 0) /**< Shifted mode APORT4YCH30 for ACMP_INPUTSEL */
-#define ACMP_INPUTSEL_POSSEL_APORT4YCH14 (_ACMP_INPUTSEL_POSSEL_APORT4YCH14 << 0) /**< Shifted mode APORT4YCH14 for ACMP_INPUTSEL */
-#define ACMP_INPUTSEL_POSSEL_APORT4XCH15 (_ACMP_INPUTSEL_POSSEL_APORT4XCH15 << 0) /**< Shifted mode APORT4XCH15 for ACMP_INPUTSEL */
#define ACMP_INPUTSEL_POSSEL_APORT4XCH31 (_ACMP_INPUTSEL_POSSEL_APORT4XCH31 << 0) /**< Shifted mode APORT4XCH31 for ACMP_INPUTSEL */
#define ACMP_INPUTSEL_POSSEL_VLP (_ACMP_INPUTSEL_POSSEL_VLP << 0) /**< Shifted mode VLP for ACMP_INPUTSEL */
#define ACMP_INPUTSEL_POSSEL_VBDIV (_ACMP_INPUTSEL_POSSEL_VBDIV << 0) /**< Shifted mode VBDIV for ACMP_INPUTSEL */
@@ -658,6 +657,8 @@ typedef struct {
#define _ACMP_INPUTSEL_NEGSEL_APORT4XCH11 0x0000008BUL /**< Mode APORT4XCH11 for ACMP_INPUTSEL */
#define _ACMP_INPUTSEL_NEGSEL_APORT4YCH12 0x0000008CUL /**< Mode APORT4YCH12 for ACMP_INPUTSEL */
#define _ACMP_INPUTSEL_NEGSEL_APORT4XCH13 0x0000008DUL /**< Mode APORT4XCH13 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_NEGSEL_APORT4YCH14 0x0000008EUL /**< Mode APORT4YCH14 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_NEGSEL_APORT4XCH15 0x0000008FUL /**< Mode APORT4XCH15 for ACMP_INPUTSEL */
#define _ACMP_INPUTSEL_NEGSEL_APORT4YCH16 0x00000090UL /**< Mode APORT4YCH16 for ACMP_INPUTSEL */
#define _ACMP_INPUTSEL_NEGSEL_APORT4XCH17 0x00000091UL /**< Mode APORT4XCH17 for ACMP_INPUTSEL */
#define _ACMP_INPUTSEL_NEGSEL_APORT4YCH18 0x00000092UL /**< Mode APORT4YCH18 for ACMP_INPUTSEL */
@@ -673,8 +674,6 @@ typedef struct {
#define _ACMP_INPUTSEL_NEGSEL_APORT4YCH28 0x0000009CUL /**< Mode APORT4YCH28 for ACMP_INPUTSEL */
#define _ACMP_INPUTSEL_NEGSEL_APORT4XCH29 0x0000009DUL /**< Mode APORT4XCH29 for ACMP_INPUTSEL */
#define _ACMP_INPUTSEL_NEGSEL_APORT4YCH30 0x0000009EUL /**< Mode APORT4YCH30 for ACMP_INPUTSEL */
-#define _ACMP_INPUTSEL_NEGSEL_APORT4YCH14 0x0000009EUL /**< Mode APORT4YCH14 for ACMP_INPUTSEL */
-#define _ACMP_INPUTSEL_NEGSEL_APORT4XCH15 0x0000009FUL /**< Mode APORT4XCH15 for ACMP_INPUTSEL */
#define _ACMP_INPUTSEL_NEGSEL_APORT4XCH31 0x0000009FUL /**< Mode APORT4XCH31 for ACMP_INPUTSEL */
#define _ACMP_INPUTSEL_NEGSEL_VLP 0x000000FBUL /**< Mode VLP for ACMP_INPUTSEL */
#define _ACMP_INPUTSEL_NEGSEL_VBDIV 0x000000FCUL /**< Mode VBDIV for ACMP_INPUTSEL */
@@ -824,6 +823,8 @@ typedef struct {
#define ACMP_INPUTSEL_NEGSEL_APORT4XCH11 (_ACMP_INPUTSEL_NEGSEL_APORT4XCH11 << 8) /**< Shifted mode APORT4XCH11 for ACMP_INPUTSEL */
#define ACMP_INPUTSEL_NEGSEL_APORT4YCH12 (_ACMP_INPUTSEL_NEGSEL_APORT4YCH12 << 8) /**< Shifted mode APORT4YCH12 for ACMP_INPUTSEL */
#define ACMP_INPUTSEL_NEGSEL_APORT4XCH13 (_ACMP_INPUTSEL_NEGSEL_APORT4XCH13 << 8) /**< Shifted mode APORT4XCH13 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_NEGSEL_APORT4YCH14 (_ACMP_INPUTSEL_NEGSEL_APORT4YCH14 << 8) /**< Shifted mode APORT4YCH14 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_NEGSEL_APORT4XCH15 (_ACMP_INPUTSEL_NEGSEL_APORT4XCH15 << 8) /**< Shifted mode APORT4XCH15 for ACMP_INPUTSEL */
#define ACMP_INPUTSEL_NEGSEL_APORT4YCH16 (_ACMP_INPUTSEL_NEGSEL_APORT4YCH16 << 8) /**< Shifted mode APORT4YCH16 for ACMP_INPUTSEL */
#define ACMP_INPUTSEL_NEGSEL_APORT4XCH17 (_ACMP_INPUTSEL_NEGSEL_APORT4XCH17 << 8) /**< Shifted mode APORT4XCH17 for ACMP_INPUTSEL */
#define ACMP_INPUTSEL_NEGSEL_APORT4YCH18 (_ACMP_INPUTSEL_NEGSEL_APORT4YCH18 << 8) /**< Shifted mode APORT4YCH18 for ACMP_INPUTSEL */
@@ -839,8 +840,6 @@ typedef struct {
#define ACMP_INPUTSEL_NEGSEL_APORT4YCH28 (_ACMP_INPUTSEL_NEGSEL_APORT4YCH28 << 8) /**< Shifted mode APORT4YCH28 for ACMP_INPUTSEL */
#define ACMP_INPUTSEL_NEGSEL_APORT4XCH29 (_ACMP_INPUTSEL_NEGSEL_APORT4XCH29 << 8) /**< Shifted mode APORT4XCH29 for ACMP_INPUTSEL */
#define ACMP_INPUTSEL_NEGSEL_APORT4YCH30 (_ACMP_INPUTSEL_NEGSEL_APORT4YCH30 << 8) /**< Shifted mode APORT4YCH30 for ACMP_INPUTSEL */
-#define ACMP_INPUTSEL_NEGSEL_APORT4YCH14 (_ACMP_INPUTSEL_NEGSEL_APORT4YCH14 << 8) /**< Shifted mode APORT4YCH14 for ACMP_INPUTSEL */
-#define ACMP_INPUTSEL_NEGSEL_APORT4XCH15 (_ACMP_INPUTSEL_NEGSEL_APORT4XCH15 << 8) /**< Shifted mode APORT4XCH15 for ACMP_INPUTSEL */
#define ACMP_INPUTSEL_NEGSEL_APORT4XCH31 (_ACMP_INPUTSEL_NEGSEL_APORT4XCH31 << 8) /**< Shifted mode APORT4XCH31 for ACMP_INPUTSEL */
#define ACMP_INPUTSEL_NEGSEL_VLP (_ACMP_INPUTSEL_NEGSEL_VLP << 8) /**< Shifted mode VLP for ACMP_INPUTSEL */
#define ACMP_INPUTSEL_NEGSEL_VBDIV (_ACMP_INPUTSEL_NEGSEL_VBDIV << 8) /**< Shifted mode VBDIV for ACMP_INPUTSEL */
diff --git a/cpu/efm32/families/efr32mg1p/include/vendor/efr32mg1p_adc.h b/cpu/efm32/families/efr32mg1p/include/vendor/efr32mg1p_adc.h
index 520b9e0215..fc6780f138 100644
--- a/cpu/efm32/families/efr32mg1p/include/vendor/efr32mg1p_adc.h
+++ b/cpu/efm32/families/efr32mg1p/include/vendor/efr32mg1p_adc.h
@@ -1,10 +1,9 @@
/***************************************************************************//**
* @file
* @brief EFR32MG1P_ADC register and bit field definitions
- * @version 5.8.3
*******************************************************************************
* # License
- * Copyright 2019 Silicon Laboratories Inc. www.silabs.com
+ * Copyright 2020 Silicon Laboratories Inc. www.silabs.com
*******************************************************************************
*
* SPDX-License-Identifier: Zlib
@@ -1323,133 +1322,133 @@ typedef struct {
#define _ADC_SCANMASK_SCANINPUTEN_SHIFT 0 /**< Shift value for ADC_SCANINPUTEN */
#define _ADC_SCANMASK_SCANINPUTEN_MASK 0xFFFFFFFFUL /**< Bit mask for ADC_SCANINPUTEN */
#define _ADC_SCANMASK_SCANINPUTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SCANMASK */
-#define _ADC_SCANMASK_SCANINPUTEN_INPUT0INPUT0NEGSEL 0x00000001UL /**< Mode INPUT0INPUT0NEGSEL for ADC_SCANMASK */
#define _ADC_SCANMASK_SCANINPUTEN_INPUT0 0x00000001UL /**< Mode INPUT0 for ADC_SCANMASK */
-#define _ADC_SCANMASK_SCANINPUTEN_INPUT1 0x00000002UL /**< Mode INPUT1 for ADC_SCANMASK */
+#define _ADC_SCANMASK_SCANINPUTEN_INPUT0INPUT0NEGSEL 0x00000001UL /**< Mode INPUT0INPUT0NEGSEL for ADC_SCANMASK */
#define _ADC_SCANMASK_SCANINPUTEN_INPUT1INPUT2 0x00000002UL /**< Mode INPUT1INPUT2 for ADC_SCANMASK */
+#define _ADC_SCANMASK_SCANINPUTEN_INPUT1 0x00000002UL /**< Mode INPUT1 for ADC_SCANMASK */
#define _ADC_SCANMASK_SCANINPUTEN_INPUT2 0x00000004UL /**< Mode INPUT2 for ADC_SCANMASK */
#define _ADC_SCANMASK_SCANINPUTEN_INPUT2INPUT2NEGSEL 0x00000004UL /**< Mode INPUT2INPUT2NEGSEL for ADC_SCANMASK */
-#define _ADC_SCANMASK_SCANINPUTEN_INPUT3 0x00000008UL /**< Mode INPUT3 for ADC_SCANMASK */
#define _ADC_SCANMASK_SCANINPUTEN_INPUT3INPUT4 0x00000008UL /**< Mode INPUT3INPUT4 for ADC_SCANMASK */
-#define _ADC_SCANMASK_SCANINPUTEN_INPUT4 0x00000010UL /**< Mode INPUT4 for ADC_SCANMASK */
+#define _ADC_SCANMASK_SCANINPUTEN_INPUT3 0x00000008UL /**< Mode INPUT3 for ADC_SCANMASK */
#define _ADC_SCANMASK_SCANINPUTEN_INPUT4INPUT4NEGSEL 0x00000010UL /**< Mode INPUT4INPUT4NEGSEL for ADC_SCANMASK */
+#define _ADC_SCANMASK_SCANINPUTEN_INPUT4 0x00000010UL /**< Mode INPUT4 for ADC_SCANMASK */
#define _ADC_SCANMASK_SCANINPUTEN_INPUT5INPUT6 0x00000020UL /**< Mode INPUT5INPUT6 for ADC_SCANMASK */
#define _ADC_SCANMASK_SCANINPUTEN_INPUT5 0x00000020UL /**< Mode INPUT5 for ADC_SCANMASK */
-#define _ADC_SCANMASK_SCANINPUTEN_INPUT6INPUT6NEGSEL 0x00000040UL /**< Mode INPUT6INPUT6NEGSEL for ADC_SCANMASK */
#define _ADC_SCANMASK_SCANINPUTEN_INPUT6 0x00000040UL /**< Mode INPUT6 for ADC_SCANMASK */
-#define _ADC_SCANMASK_SCANINPUTEN_INPUT7 0x00000080UL /**< Mode INPUT7 for ADC_SCANMASK */
+#define _ADC_SCANMASK_SCANINPUTEN_INPUT6INPUT6NEGSEL 0x00000040UL /**< Mode INPUT6INPUT6NEGSEL for ADC_SCANMASK */
#define _ADC_SCANMASK_SCANINPUTEN_INPUT7INPUT0 0x00000080UL /**< Mode INPUT7INPUT0 for ADC_SCANMASK */
-#define _ADC_SCANMASK_SCANINPUTEN_INPUT8INPUT9 0x00000100UL /**< Mode INPUT8INPUT9 for ADC_SCANMASK */
+#define _ADC_SCANMASK_SCANINPUTEN_INPUT7 0x00000080UL /**< Mode INPUT7 for ADC_SCANMASK */
#define _ADC_SCANMASK_SCANINPUTEN_INPUT8 0x00000100UL /**< Mode INPUT8 for ADC_SCANMASK */
-#define _ADC_SCANMASK_SCANINPUTEN_INPUT9 0x00000200UL /**< Mode INPUT9 for ADC_SCANMASK */
+#define _ADC_SCANMASK_SCANINPUTEN_INPUT8INPUT9 0x00000100UL /**< Mode INPUT8INPUT9 for ADC_SCANMASK */
#define _ADC_SCANMASK_SCANINPUTEN_INPUT9INPUT9NEGSEL 0x00000200UL /**< Mode INPUT9INPUT9NEGSEL for ADC_SCANMASK */
-#define _ADC_SCANMASK_SCANINPUTEN_INPUT10INPUT11 0x00000400UL /**< Mode INPUT10INPUT11 for ADC_SCANMASK */
+#define _ADC_SCANMASK_SCANINPUTEN_INPUT9 0x00000200UL /**< Mode INPUT9 for ADC_SCANMASK */
#define _ADC_SCANMASK_SCANINPUTEN_INPUT10 0x00000400UL /**< Mode INPUT10 for ADC_SCANMASK */
-#define _ADC_SCANMASK_SCANINPUTEN_INPUT11INPUT11NEGSEL 0x00000800UL /**< Mode INPUT11INPUT11NEGSEL for ADC_SCANMASK */
+#define _ADC_SCANMASK_SCANINPUTEN_INPUT10INPUT11 0x00000400UL /**< Mode INPUT10INPUT11 for ADC_SCANMASK */
#define _ADC_SCANMASK_SCANINPUTEN_INPUT11 0x00000800UL /**< Mode INPUT11 for ADC_SCANMASK */
-#define _ADC_SCANMASK_SCANINPUTEN_INPUT12INPUT13 0x00001000UL /**< Mode INPUT12INPUT13 for ADC_SCANMASK */
+#define _ADC_SCANMASK_SCANINPUTEN_INPUT11INPUT11NEGSEL 0x00000800UL /**< Mode INPUT11INPUT11NEGSEL for ADC_SCANMASK */
#define _ADC_SCANMASK_SCANINPUTEN_INPUT12 0x00001000UL /**< Mode INPUT12 for ADC_SCANMASK */
-#define _ADC_SCANMASK_SCANINPUTEN_INPUT13INPUT13NEGSEL 0x00002000UL /**< Mode INPUT13INPUT13NEGSEL for ADC_SCANMASK */
+#define _ADC_SCANMASK_SCANINPUTEN_INPUT12INPUT13 0x00001000UL /**< Mode INPUT12INPUT13 for ADC_SCANMASK */
#define _ADC_SCANMASK_SCANINPUTEN_INPUT13 0x00002000UL /**< Mode INPUT13 for ADC_SCANMASK */
-#define _ADC_SCANMASK_SCANINPUTEN_INPUT14INPUT15 0x00004000UL /**< Mode INPUT14INPUT15 for ADC_SCANMASK */
+#define _ADC_SCANMASK_SCANINPUTEN_INPUT13INPUT13NEGSEL 0x00002000UL /**< Mode INPUT13INPUT13NEGSEL for ADC_SCANMASK */
#define _ADC_SCANMASK_SCANINPUTEN_INPUT14 0x00004000UL /**< Mode INPUT14 for ADC_SCANMASK */
-#define _ADC_SCANMASK_SCANINPUTEN_INPUT15INPUT15NEGSEL 0x00008000UL /**< Mode INPUT15INPUT15NEGSEL for ADC_SCANMASK */
+#define _ADC_SCANMASK_SCANINPUTEN_INPUT14INPUT15 0x00004000UL /**< Mode INPUT14INPUT15 for ADC_SCANMASK */
#define _ADC_SCANMASK_SCANINPUTEN_INPUT15 0x00008000UL /**< Mode INPUT15 for ADC_SCANMASK */
-#define _ADC_SCANMASK_SCANINPUTEN_INPUT16INPUT17 0x00010000UL /**< Mode INPUT16INPUT17 for ADC_SCANMASK */
+#define _ADC_SCANMASK_SCANINPUTEN_INPUT15INPUT15NEGSEL 0x00008000UL /**< Mode INPUT15INPUT15NEGSEL for ADC_SCANMASK */
#define _ADC_SCANMASK_SCANINPUTEN_INPUT16 0x00010000UL /**< Mode INPUT16 for ADC_SCANMASK */
-#define _ADC_SCANMASK_SCANINPUTEN_INPUT17INPUT18 0x00020000UL /**< Mode INPUT17INPUT18 for ADC_SCANMASK */
+#define _ADC_SCANMASK_SCANINPUTEN_INPUT16INPUT17 0x00010000UL /**< Mode INPUT16INPUT17 for ADC_SCANMASK */
#define _ADC_SCANMASK_SCANINPUTEN_INPUT17 0x00020000UL /**< Mode INPUT17 for ADC_SCANMASK */
+#define _ADC_SCANMASK_SCANINPUTEN_INPUT17INPUT18 0x00020000UL /**< Mode INPUT17INPUT18 for ADC_SCANMASK */
#define _ADC_SCANMASK_SCANINPUTEN_INPUT18INPUT19 0x00040000UL /**< Mode INPUT18INPUT19 for ADC_SCANMASK */
#define _ADC_SCANMASK_SCANINPUTEN_INPUT18 0x00040000UL /**< Mode INPUT18 for ADC_SCANMASK */
#define _ADC_SCANMASK_SCANINPUTEN_INPUT19 0x00080000UL /**< Mode INPUT19 for ADC_SCANMASK */
#define _ADC_SCANMASK_SCANINPUTEN_INPUT19INPUT20 0x00080000UL /**< Mode INPUT19INPUT20 for ADC_SCANMASK */
#define _ADC_SCANMASK_SCANINPUTEN_INPUT20INPUT21 0x00100000UL /**< Mode INPUT20INPUT21 for ADC_SCANMASK */
#define _ADC_SCANMASK_SCANINPUTEN_INPUT20 0x00100000UL /**< Mode INPUT20 for ADC_SCANMASK */
-#define _ADC_SCANMASK_SCANINPUTEN_INPUT21 0x00200000UL /**< Mode INPUT21 for ADC_SCANMASK */
#define _ADC_SCANMASK_SCANINPUTEN_INPUT21INPUT22 0x00200000UL /**< Mode INPUT21INPUT22 for ADC_SCANMASK */
+#define _ADC_SCANMASK_SCANINPUTEN_INPUT21 0x00200000UL /**< Mode INPUT21 for ADC_SCANMASK */
#define _ADC_SCANMASK_SCANINPUTEN_INPUT22INPUT23 0x00400000UL /**< Mode INPUT22INPUT23 for ADC_SCANMASK */
#define _ADC_SCANMASK_SCANINPUTEN_INPUT22 0x00400000UL /**< Mode INPUT22 for ADC_SCANMASK */
-#define _ADC_SCANMASK_SCANINPUTEN_INPUT23INPUT16 0x00800000UL /**< Mode INPUT23INPUT16 for ADC_SCANMASK */
#define _ADC_SCANMASK_SCANINPUTEN_INPUT23 0x00800000UL /**< Mode INPUT23 for ADC_SCANMASK */
-#define _ADC_SCANMASK_SCANINPUTEN_INPUT24 0x01000000UL /**< Mode INPUT24 for ADC_SCANMASK */
+#define _ADC_SCANMASK_SCANINPUTEN_INPUT23INPUT16 0x00800000UL /**< Mode INPUT23INPUT16 for ADC_SCANMASK */
#define _ADC_SCANMASK_SCANINPUTEN_INPUT24INPUT25 0x01000000UL /**< Mode INPUT24INPUT25 for ADC_SCANMASK */
-#define _ADC_SCANMASK_SCANINPUTEN_INPUT25INPUT26 0x02000000UL /**< Mode INPUT25INPUT26 for ADC_SCANMASK */
+#define _ADC_SCANMASK_SCANINPUTEN_INPUT24 0x01000000UL /**< Mode INPUT24 for ADC_SCANMASK */
#define _ADC_SCANMASK_SCANINPUTEN_INPUT25 0x02000000UL /**< Mode INPUT25 for ADC_SCANMASK */
-#define _ADC_SCANMASK_SCANINPUTEN_INPUT26 0x04000000UL /**< Mode INPUT26 for ADC_SCANMASK */
+#define _ADC_SCANMASK_SCANINPUTEN_INPUT25INPUT26 0x02000000UL /**< Mode INPUT25INPUT26 for ADC_SCANMASK */
#define _ADC_SCANMASK_SCANINPUTEN_INPUT26INPUT27 0x04000000UL /**< Mode INPUT26INPUT27 for ADC_SCANMASK */
-#define _ADC_SCANMASK_SCANINPUTEN_INPUT27INPUT28 0x08000000UL /**< Mode INPUT27INPUT28 for ADC_SCANMASK */
+#define _ADC_SCANMASK_SCANINPUTEN_INPUT26 0x04000000UL /**< Mode INPUT26 for ADC_SCANMASK */
#define _ADC_SCANMASK_SCANINPUTEN_INPUT27 0x08000000UL /**< Mode INPUT27 for ADC_SCANMASK */
-#define _ADC_SCANMASK_SCANINPUTEN_INPUT28INPUT29 0x10000000UL /**< Mode INPUT28INPUT29 for ADC_SCANMASK */
+#define _ADC_SCANMASK_SCANINPUTEN_INPUT27INPUT28 0x08000000UL /**< Mode INPUT27INPUT28 for ADC_SCANMASK */
#define _ADC_SCANMASK_SCANINPUTEN_INPUT28 0x10000000UL /**< Mode INPUT28 for ADC_SCANMASK */
+#define _ADC_SCANMASK_SCANINPUTEN_INPUT28INPUT29 0x10000000UL /**< Mode INPUT28INPUT29 for ADC_SCANMASK */
#define _ADC_SCANMASK_SCANINPUTEN_INPUT29 0x20000000UL /**< Mode INPUT29 for ADC_SCANMASK */
#define _ADC_SCANMASK_SCANINPUTEN_INPUT29INPUT30 0x20000000UL /**< Mode INPUT29INPUT30 for ADC_SCANMASK */
-#define _ADC_SCANMASK_SCANINPUTEN_INPUT30 0x40000000UL /**< Mode INPUT30 for ADC_SCANMASK */
#define _ADC_SCANMASK_SCANINPUTEN_INPUT30INPUT31 0x40000000UL /**< Mode INPUT30INPUT31 for ADC_SCANMASK */
+#define _ADC_SCANMASK_SCANINPUTEN_INPUT30 0x40000000UL /**< Mode INPUT30 for ADC_SCANMASK */
#define _ADC_SCANMASK_SCANINPUTEN_INPUT31INPUT24 0x80000000UL /**< Mode INPUT31INPUT24 for ADC_SCANMASK */
#define _ADC_SCANMASK_SCANINPUTEN_INPUT31 0x80000000UL /**< Mode INPUT31 for ADC_SCANMASK */
#define ADC_SCANMASK_SCANINPUTEN_DEFAULT (_ADC_SCANMASK_SCANINPUTEN_DEFAULT << 0) /**< Shifted mode DEFAULT for ADC_SCANMASK */
-#define ADC_SCANMASK_SCANINPUTEN_INPUT0INPUT0NEGSEL (_ADC_SCANMASK_SCANINPUTEN_INPUT0INPUT0NEGSEL << 0) /**< Shifted mode INPUT0INPUT0NEGSEL for ADC_SCANMASK */
#define ADC_SCANMASK_SCANINPUTEN_INPUT0 (_ADC_SCANMASK_SCANINPUTEN_INPUT0 << 0) /**< Shifted mode INPUT0 for ADC_SCANMASK */
-#define ADC_SCANMASK_SCANINPUTEN_INPUT1 (_ADC_SCANMASK_SCANINPUTEN_INPUT1 << 0) /**< Shifted mode INPUT1 for ADC_SCANMASK */
+#define ADC_SCANMASK_SCANINPUTEN_INPUT0INPUT0NEGSEL (_ADC_SCANMASK_SCANINPUTEN_INPUT0INPUT0NEGSEL << 0) /**< Shifted mode INPUT0INPUT0NEGSEL for ADC_SCANMASK */
#define ADC_SCANMASK_SCANINPUTEN_INPUT1INPUT2 (_ADC_SCANMASK_SCANINPUTEN_INPUT1INPUT2 << 0) /**< Shifted mode INPUT1INPUT2 for ADC_SCANMASK */
+#define ADC_SCANMASK_SCANINPUTEN_INPUT1 (_ADC_SCANMASK_SCANINPUTEN_INPUT1 << 0) /**< Shifted mode INPUT1 for ADC_SCANMASK */
#define ADC_SCANMASK_SCANINPUTEN_INPUT2 (_ADC_SCANMASK_SCANINPUTEN_INPUT2 << 0) /**< Shifted mode INPUT2 for ADC_SCANMASK */
#define ADC_SCANMASK_SCANINPUTEN_INPUT2INPUT2NEGSEL (_ADC_SCANMASK_SCANINPUTEN_INPUT2INPUT2NEGSEL << 0) /**< Shifted mode INPUT2INPUT2NEGSEL for ADC_SCANMASK */
-#define ADC_SCANMASK_SCANINPUTEN_INPUT3 (_ADC_SCANMASK_SCANINPUTEN_INPUT3 << 0) /**< Shifted mode INPUT3 for ADC_SCANMASK */
#define ADC_SCANMASK_SCANINPUTEN_INPUT3INPUT4 (_ADC_SCANMASK_SCANINPUTEN_INPUT3INPUT4 << 0) /**< Shifted mode INPUT3INPUT4 for ADC_SCANMASK */
-#define ADC_SCANMASK_SCANINPUTEN_INPUT4 (_ADC_SCANMASK_SCANINPUTEN_INPUT4 << 0) /**< Shifted mode INPUT4 for ADC_SCANMASK */
+#define ADC_SCANMASK_SCANINPUTEN_INPUT3 (_ADC_SCANMASK_SCANINPUTEN_INPUT3 << 0) /**< Shifted mode INPUT3 for ADC_SCANMASK */
#define ADC_SCANMASK_SCANINPUTEN_INPUT4INPUT4NEGSEL (_ADC_SCANMASK_SCANINPUTEN_INPUT4INPUT4NEGSEL << 0) /**< Shifted mode INPUT4INPUT4NEGSEL for ADC_SCANMASK */
+#define ADC_SCANMASK_SCANINPUTEN_INPUT4 (_ADC_SCANMASK_SCANINPUTEN_INPUT4 << 0) /**< Shifted mode INPUT4 for ADC_SCANMASK */
#define ADC_SCANMASK_SCANINPUTEN_INPUT5INPUT6 (_ADC_SCANMASK_SCANINPUTEN_INPUT5INPUT6 << 0) /**< Shifted mode INPUT5INPUT6 for ADC_SCANMASK */
#define ADC_SCANMASK_SCANINPUTEN_INPUT5 (_ADC_SCANMASK_SCANINPUTEN_INPUT5 << 0) /**< Shifted mode INPUT5 for ADC_SCANMASK */
-#define ADC_SCANMASK_SCANINPUTEN_INPUT6INPUT6NEGSEL (_ADC_SCANMASK_SCANINPUTEN_INPUT6INPUT6NEGSEL << 0) /**< Shifted mode INPUT6INPUT6NEGSEL for ADC_SCANMASK */
#define ADC_SCANMASK_SCANINPUTEN_INPUT6 (_ADC_SCANMASK_SCANINPUTEN_INPUT6 << 0) /**< Shifted mode INPUT6 for ADC_SCANMASK */
-#define ADC_SCANMASK_SCANINPUTEN_INPUT7 (_ADC_SCANMASK_SCANINPUTEN_INPUT7 << 0) /**< Shifted mode INPUT7 for ADC_SCANMASK */
+#define ADC_SCANMASK_SCANINPUTEN_INPUT6INPUT6NEGSEL (_ADC_SCANMASK_SCANINPUTEN_INPUT6INPUT6NEGSEL << 0) /**< Shifted mode INPUT6INPUT6NEGSEL for ADC_SCANMASK */
#define ADC_SCANMASK_SCANINPUTEN_INPUT7INPUT0 (_ADC_SCANMASK_SCANINPUTEN_INPUT7INPUT0 << 0) /**< Shifted mode INPUT7INPUT0 for ADC_SCANMASK */
-#define ADC_SCANMASK_SCANINPUTEN_INPUT8INPUT9 (_ADC_SCANMASK_SCANINPUTEN_INPUT8INPUT9 << 0) /**< Shifted mode INPUT8INPUT9 for ADC_SCANMASK */
+#define ADC_SCANMASK_SCANINPUTEN_INPUT7 (_ADC_SCANMASK_SCANINPUTEN_INPUT7 << 0) /**< Shifted mode INPUT7 for ADC_SCANMASK */
#define ADC_SCANMASK_SCANINPUTEN_INPUT8 (_ADC_SCANMASK_SCANINPUTEN_INPUT8 << 0) /**< Shifted mode INPUT8 for ADC_SCANMASK */
-#define ADC_SCANMASK_SCANINPUTEN_INPUT9 (_ADC_SCANMASK_SCANINPUTEN_INPUT9 << 0) /**< Shifted mode INPUT9 for ADC_SCANMASK */
+#define ADC_SCANMASK_SCANINPUTEN_INPUT8INPUT9 (_ADC_SCANMASK_SCANINPUTEN_INPUT8INPUT9 << 0) /**< Shifted mode INPUT8INPUT9 for ADC_SCANMASK */
#define ADC_SCANMASK_SCANINPUTEN_INPUT9INPUT9NEGSEL (_ADC_SCANMASK_SCANINPUTEN_INPUT9INPUT9NEGSEL << 0) /**< Shifted mode INPUT9INPUT9NEGSEL for ADC_SCANMASK */
-#define ADC_SCANMASK_SCANINPUTEN_INPUT10INPUT11 (_ADC_SCANMASK_SCANINPUTEN_INPUT10INPUT11 << 0) /**< Shifted mode INPUT10INPUT11 for ADC_SCANMASK */
+#define ADC_SCANMASK_SCANINPUTEN_INPUT9 (_ADC_SCANMASK_SCANINPUTEN_INPUT9 << 0) /**< Shifted mode INPUT9 for ADC_SCANMASK */
#define ADC_SCANMASK_SCANINPUTEN_INPUT10 (_ADC_SCANMASK_SCANINPUTEN_INPUT10 << 0) /**< Shifted mode INPUT10 for ADC_SCANMASK */
-#define ADC_SCANMASK_SCANINPUTEN_INPUT11INPUT11NEGSEL (_ADC_SCANMASK_SCANINPUTEN_INPUT11INPUT11NEGSEL << 0) /**< Shifted mode INPUT11INPUT11NEGSEL for ADC_SCANMASK */
+#define ADC_SCANMASK_SCANINPUTEN_INPUT10INPUT11 (_ADC_SCANMASK_SCANINPUTEN_INPUT10INPUT11 << 0) /**< Shifted mode INPUT10INPUT11 for ADC_SCANMASK */
#define ADC_SCANMASK_SCANINPUTEN_INPUT11 (_ADC_SCANMASK_SCANINPUTEN_INPUT11 << 0) /**< Shifted mode INPUT11 for ADC_SCANMASK */
-#define ADC_SCANMASK_SCANINPUTEN_INPUT12INPUT13 (_ADC_SCANMASK_SCANINPUTEN_INPUT12INPUT13 << 0) /**< Shifted mode INPUT12INPUT13 for ADC_SCANMASK */
+#define ADC_SCANMASK_SCANINPUTEN_INPUT11INPUT11NEGSEL (_ADC_SCANMASK_SCANINPUTEN_INPUT11INPUT11NEGSEL << 0) /**< Shifted mode INPUT11INPUT11NEGSEL for ADC_SCANMASK */
#define ADC_SCANMASK_SCANINPUTEN_INPUT12 (_ADC_SCANMASK_SCANINPUTEN_INPUT12 << 0) /**< Shifted mode INPUT12 for ADC_SCANMASK */
-#define ADC_SCANMASK_SCANINPUTEN_INPUT13INPUT13NEGSEL (_ADC_SCANMASK_SCANINPUTEN_INPUT13INPUT13NEGSEL << 0) /**< Shifted mode INPUT13INPUT13NEGSEL for ADC_SCANMASK */
+#define ADC_SCANMASK_SCANINPUTEN_INPUT12INPUT13 (_ADC_SCANMASK_SCANINPUTEN_INPUT12INPUT13 << 0) /**< Shifted mode INPUT12INPUT13 for ADC_SCANMASK */
#define ADC_SCANMASK_SCANINPUTEN_INPUT13 (_ADC_SCANMASK_SCANINPUTEN_INPUT13 << 0) /**< Shifted mode INPUT13 for ADC_SCANMASK */
-#define ADC_SCANMASK_SCANINPUTEN_INPUT14INPUT15 (_ADC_SCANMASK_SCANINPUTEN_INPUT14INPUT15 << 0) /**< Shifted mode INPUT14INPUT15 for ADC_SCANMASK */
+#define ADC_SCANMASK_SCANINPUTEN_INPUT13INPUT13NEGSEL (_ADC_SCANMASK_SCANINPUTEN_INPUT13INPUT13NEGSEL << 0) /**< Shifted mode INPUT13INPUT13NEGSEL for ADC_SCANMASK */
#define ADC_SCANMASK_SCANINPUTEN_INPUT14 (_ADC_SCANMASK_SCANINPUTEN_INPUT14 << 0) /**< Shifted mode INPUT14 for ADC_SCANMASK */
-#define ADC_SCANMASK_SCANINPUTEN_INPUT15INPUT15NEGSEL (_ADC_SCANMASK_SCANINPUTEN_INPUT15INPUT15NEGSEL << 0) /**< Shifted mode INPUT15INPUT15NEGSEL for ADC_SCANMASK */
+#define ADC_SCANMASK_SCANINPUTEN_INPUT14INPUT15 (_ADC_SCANMASK_SCANINPUTEN_INPUT14INPUT15 << 0) /**< Shifted mode INPUT14INPUT15 for ADC_SCANMASK */
#define ADC_SCANMASK_SCANINPUTEN_INPUT15 (_ADC_SCANMASK_SCANINPUTEN_INPUT15 << 0) /**< Shifted mode INPUT15 for ADC_SCANMASK */
-#define ADC_SCANMASK_SCANINPUTEN_INPUT16INPUT17 (_ADC_SCANMASK_SCANINPUTEN_INPUT16INPUT17 << 0) /**< Shifted mode INPUT16INPUT17 for ADC_SCANMASK */
+#define ADC_SCANMASK_SCANINPUTEN_INPUT15INPUT15NEGSEL (_ADC_SCANMASK_SCANINPUTEN_INPUT15INPUT15NEGSEL << 0) /**< Shifted mode INPUT15INPUT15NEGSEL for ADC_SCANMASK */
#define ADC_SCANMASK_SCANINPUTEN_INPUT16 (_ADC_SCANMASK_SCANINPUTEN_INPUT16 << 0) /**< Shifted mode INPUT16 for ADC_SCANMASK */
-#define ADC_SCANMASK_SCANINPUTEN_INPUT17INPUT18 (_ADC_SCANMASK_SCANINPUTEN_INPUT17INPUT18 << 0) /**< Shifted mode INPUT17INPUT18 for ADC_SCANMASK */
+#define ADC_SCANMASK_SCANINPUTEN_INPUT16INPUT17 (_ADC_SCANMASK_SCANINPUTEN_INPUT16INPUT17 << 0) /**< Shifted mode INPUT16INPUT17 for ADC_SCANMASK */
#define ADC_SCANMASK_SCANINPUTEN_INPUT17 (_ADC_SCANMASK_SCANINPUTEN_INPUT17 << 0) /**< Shifted mode INPUT17 for ADC_SCANMASK */
+#define ADC_SCANMASK_SCANINPUTEN_INPUT17INPUT18 (_ADC_SCANMASK_SCANINPUTEN_INPUT17INPUT18 << 0) /**< Shifted mode INPUT17INPUT18 for ADC_SCANMASK */
#define ADC_SCANMASK_SCANINPUTEN_INPUT18INPUT19 (_ADC_SCANMASK_SCANINPUTEN_INPUT18INPUT19 << 0) /**< Shifted mode INPUT18INPUT19 for ADC_SCANMASK */
#define ADC_SCANMASK_SCANINPUTEN_INPUT18 (_ADC_SCANMASK_SCANINPUTEN_INPUT18 << 0) /**< Shifted mode INPUT18 for ADC_SCANMASK */
#define ADC_SCANMASK_SCANINPUTEN_INPUT19 (_ADC_SCANMASK_SCANINPUTEN_INPUT19 << 0) /**< Shifted mode INPUT19 for ADC_SCANMASK */
#define ADC_SCANMASK_SCANINPUTEN_INPUT19INPUT20 (_ADC_SCANMASK_SCANINPUTEN_INPUT19INPUT20 << 0) /**< Shifted mode INPUT19INPUT20 for ADC_SCANMASK */
#define ADC_SCANMASK_SCANINPUTEN_INPUT20INPUT21 (_ADC_SCANMASK_SCANINPUTEN_INPUT20INPUT21 << 0) /**< Shifted mode INPUT20INPUT21 for ADC_SCANMASK */
#define ADC_SCANMASK_SCANINPUTEN_INPUT20 (_ADC_SCANMASK_SCANINPUTEN_INPUT20 << 0) /**< Shifted mode INPUT20 for ADC_SCANMASK */
-#define ADC_SCANMASK_SCANINPUTEN_INPUT21 (_ADC_SCANMASK_SCANINPUTEN_INPUT21 << 0) /**< Shifted mode INPUT21 for ADC_SCANMASK */
#define ADC_SCANMASK_SCANINPUTEN_INPUT21INPUT22 (_ADC_SCANMASK_SCANINPUTEN_INPUT21INPUT22 << 0) /**< Shifted mode INPUT21INPUT22 for ADC_SCANMASK */
+#define ADC_SCANMASK_SCANINPUTEN_INPUT21 (_ADC_SCANMASK_SCANINPUTEN_INPUT21 << 0) /**< Shifted mode INPUT21 for ADC_SCANMASK */
#define ADC_SCANMASK_SCANINPUTEN_INPUT22INPUT23 (_ADC_SCANMASK_SCANINPUTEN_INPUT22INPUT23 << 0) /**< Shifted mode INPUT22INPUT23 for ADC_SCANMASK */
#define ADC_SCANMASK_SCANINPUTEN_INPUT22 (_ADC_SCANMASK_SCANINPUTEN_INPUT22 << 0) /**< Shifted mode INPUT22 for ADC_SCANMASK */
-#define ADC_SCANMASK_SCANINPUTEN_INPUT23INPUT16 (_ADC_SCANMASK_SCANINPUTEN_INPUT23INPUT16 << 0) /**< Shifted mode INPUT23INPUT16 for ADC_SCANMASK */
#define ADC_SCANMASK_SCANINPUTEN_INPUT23 (_ADC_SCANMASK_SCANINPUTEN_INPUT23 << 0) /**< Shifted mode INPUT23 for ADC_SCANMASK */
-#define ADC_SCANMASK_SCANINPUTEN_INPUT24 (_ADC_SCANMASK_SCANINPUTEN_INPUT24 << 0) /**< Shifted mode INPUT24 for ADC_SCANMASK */
+#define ADC_SCANMASK_SCANINPUTEN_INPUT23INPUT16 (_ADC_SCANMASK_SCANINPUTEN_INPUT23INPUT16 << 0) /**< Shifted mode INPUT23INPUT16 for ADC_SCANMASK */
#define ADC_SCANMASK_SCANINPUTEN_INPUT24INPUT25 (_ADC_SCANMASK_SCANINPUTEN_INPUT24INPUT25 << 0) /**< Shifted mode INPUT24INPUT25 for ADC_SCANMASK */
-#define ADC_SCANMASK_SCANINPUTEN_INPUT25INPUT26 (_ADC_SCANMASK_SCANINPUTEN_INPUT25INPUT26 << 0) /**< Shifted mode INPUT25INPUT26 for ADC_SCANMASK */
+#define ADC_SCANMASK_SCANINPUTEN_INPUT24 (_ADC_SCANMASK_SCANINPUTEN_INPUT24 << 0) /**< Shifted mode INPUT24 for ADC_SCANMASK */
#define ADC_SCANMASK_SCANINPUTEN_INPUT25 (_ADC_SCANMASK_SCANINPUTEN_INPUT25 << 0) /**< Shifted mode INPUT25 for ADC_SCANMASK */
-#define ADC_SCANMASK_SCANINPUTEN_INPUT26 (_ADC_SCANMASK_SCANINPUTEN_INPUT26 << 0) /**< Shifted mode INPUT26 for ADC_SCANMASK */
+#define ADC_SCANMASK_SCANINPUTEN_INPUT25INPUT26 (_ADC_SCANMASK_SCANINPUTEN_INPUT25INPUT26 << 0) /**< Shifted mode INPUT25INPUT26 for ADC_SCANMASK */
#define ADC_SCANMASK_SCANINPUTEN_INPUT26INPUT27 (_ADC_SCANMASK_SCANINPUTEN_INPUT26INPUT27 << 0) /**< Shifted mode INPUT26INPUT27 for ADC_SCANMASK */
-#define ADC_SCANMASK_SCANINPUTEN_INPUT27INPUT28 (_ADC_SCANMASK_SCANINPUTEN_INPUT27INPUT28 << 0) /**< Shifted mode INPUT27INPUT28 for ADC_SCANMASK */
+#define ADC_SCANMASK_SCANINPUTEN_INPUT26 (_ADC_SCANMASK_SCANINPUTEN_INPUT26 << 0) /**< Shifted mode INPUT26 for ADC_SCANMASK */
#define ADC_SCANMASK_SCANINPUTEN_INPUT27 (_ADC_SCANMASK_SCANINPUTEN_INPUT27 << 0) /**< Shifted mode INPUT27 for ADC_SCANMASK */
-#define ADC_SCANMASK_SCANINPUTEN_INPUT28INPUT29 (_ADC_SCANMASK_SCANINPUTEN_INPUT28INPUT29 << 0) /**< Shifted mode INPUT28INPUT29 for ADC_SCANMASK */
+#define ADC_SCANMASK_SCANINPUTEN_INPUT27INPUT28 (_ADC_SCANMASK_SCANINPUTEN_INPUT27INPUT28 << 0) /**< Shifted mode INPUT27INPUT28 for ADC_SCANMASK */
#define ADC_SCANMASK_SCANINPUTEN_INPUT28 (_ADC_SCANMASK_SCANINPUTEN_INPUT28 << 0) /**< Shifted mode INPUT28 for ADC_SCANMASK */
+#define ADC_SCANMASK_SCANINPUTEN_INPUT28INPUT29 (_ADC_SCANMASK_SCANINPUTEN_INPUT28INPUT29 << 0) /**< Shifted mode INPUT28INPUT29 for ADC_SCANMASK */
#define ADC_SCANMASK_SCANINPUTEN_INPUT29 (_ADC_SCANMASK_SCANINPUTEN_INPUT29 << 0) /**< Shifted mode INPUT29 for ADC_SCANMASK */
#define ADC_SCANMASK_SCANINPUTEN_INPUT29INPUT30 (_ADC_SCANMASK_SCANINPUTEN_INPUT29INPUT30 << 0) /**< Shifted mode INPUT29INPUT30 for ADC_SCANMASK */
-#define ADC_SCANMASK_SCANINPUTEN_INPUT30 (_ADC_SCANMASK_SCANINPUTEN_INPUT30 << 0) /**< Shifted mode INPUT30 for ADC_SCANMASK */
#define ADC_SCANMASK_SCANINPUTEN_INPUT30INPUT31 (_ADC_SCANMASK_SCANINPUTEN_INPUT30INPUT31 << 0) /**< Shifted mode INPUT30INPUT31 for ADC_SCANMASK */
+#define ADC_SCANMASK_SCANINPUTEN_INPUT30 (_ADC_SCANMASK_SCANINPUTEN_INPUT30 << 0) /**< Shifted mode INPUT30 for ADC_SCANMASK */
#define ADC_SCANMASK_SCANINPUTEN_INPUT31INPUT24 (_ADC_SCANMASK_SCANINPUTEN_INPUT31INPUT24 << 0) /**< Shifted mode INPUT31INPUT24 for ADC_SCANMASK */
#define ADC_SCANMASK_SCANINPUTEN_INPUT31 (_ADC_SCANMASK_SCANINPUTEN_INPUT31 << 0) /**< Shifted mode INPUT31 for ADC_SCANMASK */
diff --git a/cpu/efm32/families/efr32mg1p/include/vendor/efr32mg1p_af_pins.h b/cpu/efm32/families/efr32mg1p/include/vendor/efr32mg1p_af_pins.h
index 714cd29ae3..cf5f718f18 100644
--- a/cpu/efm32/families/efr32mg1p/include/vendor/efr32mg1p_af_pins.h
+++ b/cpu/efm32/families/efr32mg1p/include/vendor/efr32mg1p_af_pins.h
@@ -1,10 +1,9 @@
/***************************************************************************//**
* @file
* @brief EFR32MG1P_AF_PINS register and bit field definitions
- * @version 5.8.3
*******************************************************************************
* # License
- * Copyright 2019 Silicon Laboratories Inc. www.silabs.com
+ * Copyright 2020 Silicon Laboratories Inc. www.silabs.com
*******************************************************************************
*
* SPDX-License-Identifier: Zlib
diff --git a/cpu/efm32/families/efr32mg1p/include/vendor/efr32mg1p_af_ports.h b/cpu/efm32/families/efr32mg1p/include/vendor/efr32mg1p_af_ports.h
index 67464a4234..1e0726e52d 100644
--- a/cpu/efm32/families/efr32mg1p/include/vendor/efr32mg1p_af_ports.h
+++ b/cpu/efm32/families/efr32mg1p/include/vendor/efr32mg1p_af_ports.h
@@ -1,10 +1,9 @@
/***************************************************************************//**
* @file
* @brief EFR32MG1P_AF_PORTS register and bit field definitions
- * @version 5.8.3
*******************************************************************************
* # License
- * Copyright 2019 Silicon Laboratories Inc. www.silabs.com
+ * Copyright 2020 Silicon Laboratories Inc. www.silabs.com
*******************************************************************************
*
* SPDX-License-Identifier: Zlib
diff --git a/cpu/efm32/families/efr32mg1p/include/vendor/efr32mg1p_cmu.h b/cpu/efm32/families/efr32mg1p/include/vendor/efr32mg1p_cmu.h
index 1078fa2375..cf10385fd6 100644
--- a/cpu/efm32/families/efr32mg1p/include/vendor/efr32mg1p_cmu.h
+++ b/cpu/efm32/families/efr32mg1p/include/vendor/efr32mg1p_cmu.h
@@ -1,10 +1,9 @@
/***************************************************************************//**
* @file
* @brief EFR32MG1P_CMU register and bit field definitions
- * @version 5.8.3
*******************************************************************************
* # License
- * Copyright 2019 Silicon Laboratories Inc. www.silabs.com
+ * Copyright 2020 Silicon Laboratories Inc. www.silabs.com
*******************************************************************************
*
* SPDX-License-Identifier: Zlib
@@ -1774,13 +1773,13 @@ typedef struct {
#define _CMU_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for CMU_LOCKKEY */
#define _CMU_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for CMU_LOCKKEY */
#define _CMU_LOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LOCK */
-#define _CMU_LOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for CMU_LOCK */
#define _CMU_LOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for CMU_LOCK */
+#define _CMU_LOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for CMU_LOCK */
#define _CMU_LOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for CMU_LOCK */
#define _CMU_LOCK_LOCKKEY_UNLOCK 0x0000580EUL /**< Mode UNLOCK for CMU_LOCK */
#define CMU_LOCK_LOCKKEY_DEFAULT (_CMU_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LOCK */
-#define CMU_LOCK_LOCKKEY_LOCK (_CMU_LOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for CMU_LOCK */
#define CMU_LOCK_LOCKKEY_UNLOCKED (_CMU_LOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for CMU_LOCK */
+#define CMU_LOCK_LOCKKEY_LOCK (_CMU_LOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for CMU_LOCK */
#define CMU_LOCK_LOCKKEY_LOCKED (_CMU_LOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for CMU_LOCK */
#define CMU_LOCK_LOCKKEY_UNLOCK (_CMU_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for CMU_LOCK */
diff --git a/cpu/efm32/families/efr32mg1p/include/vendor/efr32mg1p_cryotimer.h b/cpu/efm32/families/efr32mg1p/include/vendor/efr32mg1p_cryotimer.h
index 6139f7a8da..ae714ebfd7 100644
--- a/cpu/efm32/families/efr32mg1p/include/vendor/efr32mg1p_cryotimer.h
+++ b/cpu/efm32/families/efr32mg1p/include/vendor/efr32mg1p_cryotimer.h
@@ -1,10 +1,9 @@
/***************************************************************************//**
* @file
* @brief EFR32MG1P_CRYOTIMER register and bit field definitions
- * @version 5.8.3
*******************************************************************************
* # License
- * Copyright 2019 Silicon Laboratories Inc. www.silabs.com
+ * Copyright 2020 Silicon Laboratories Inc. www.silabs.com
*******************************************************************************
*
* SPDX-License-Identifier: Zlib
diff --git a/cpu/efm32/families/efr32mg1p/include/vendor/efr32mg1p_crypto.h b/cpu/efm32/families/efr32mg1p/include/vendor/efr32mg1p_crypto.h
index 79fc62c3ef..52df735dc2 100644
--- a/cpu/efm32/families/efr32mg1p/include/vendor/efr32mg1p_crypto.h
+++ b/cpu/efm32/families/efr32mg1p/include/vendor/efr32mg1p_crypto.h
@@ -1,10 +1,9 @@
/***************************************************************************//**
* @file
* @brief EFR32MG1P_CRYPTO register and bit field definitions
- * @version 5.8.3
*******************************************************************************
* # License
- * Copyright 2019 Silicon Laboratories Inc. www.silabs.com
+ * Copyright 2020 Silicon Laboratories Inc. www.silabs.com
*******************************************************************************
*
* SPDX-License-Identifier: Zlib
diff --git a/cpu/efm32/families/efr32mg1p/include/vendor/efr32mg1p_devinfo.h b/cpu/efm32/families/efr32mg1p/include/vendor/efr32mg1p_devinfo.h
index 21ca64d139..8c7cfbe490 100644
--- a/cpu/efm32/families/efr32mg1p/include/vendor/efr32mg1p_devinfo.h
+++ b/cpu/efm32/families/efr32mg1p/include/vendor/efr32mg1p_devinfo.h
@@ -1,10 +1,9 @@
/***************************************************************************//**
* @file
* @brief EFR32MG1P_DEVINFO register and bit field definitions
- * @version 5.8.3
*******************************************************************************
* # License
- * Copyright 2019 Silicon Laboratories Inc. www.silabs.com
+ * Copyright 2020 Silicon Laboratories Inc. www.silabs.com
*******************************************************************************
*
* SPDX-License-Identifier: Zlib
@@ -297,6 +296,8 @@ typedef struct {
#define _DEVINFO_PART_DEVICE_FAMILY_EFR32BG13B 0x0000002CUL /**< Mode EFR32BG13B for DEVINFO_PART */
#define _DEVINFO_PART_DEVICE_FAMILY_EFR32BG13V 0x0000002DUL /**< Mode EFR32BG13V for DEVINFO_PART */
#define _DEVINFO_PART_DEVICE_FAMILY_EFR32ZG13P 0x0000002EUL /**< Mode EFR32ZG13P for DEVINFO_PART */
+#define _DEVINFO_PART_DEVICE_FAMILY_EFR32ZG13L 0x0000002FUL /**< Mode EFR32ZG13L for DEVINFO_PART */
+#define _DEVINFO_PART_DEVICE_FAMILY_EFR32ZG13S 0x00000030UL /**< Mode EFR32ZG13S for DEVINFO_PART */
#define _DEVINFO_PART_DEVICE_FAMILY_EFR32FG13P 0x00000031UL /**< Mode EFR32FG13P for DEVINFO_PART */
#define _DEVINFO_PART_DEVICE_FAMILY_EFR32FG13B 0x00000032UL /**< Mode EFR32FG13B for DEVINFO_PART */
#define _DEVINFO_PART_DEVICE_FAMILY_EFR32FG13V 0x00000033UL /**< Mode EFR32FG13V for DEVINFO_PART */
@@ -314,16 +315,16 @@ typedef struct {
#define _DEVINFO_PART_DEVICE_FAMILY_G 0x00000047UL /**< Mode G for DEVINFO_PART */
#define _DEVINFO_PART_DEVICE_FAMILY_EFM32GG 0x00000048UL /**< Mode EFM32GG for DEVINFO_PART */
#define _DEVINFO_PART_DEVICE_FAMILY_GG 0x00000048UL /**< Mode GG for DEVINFO_PART */
-#define _DEVINFO_PART_DEVICE_FAMILY_TG 0x00000049UL /**< Mode TG for DEVINFO_PART */
#define _DEVINFO_PART_DEVICE_FAMILY_EFM32TG 0x00000049UL /**< Mode EFM32TG for DEVINFO_PART */
+#define _DEVINFO_PART_DEVICE_FAMILY_TG 0x00000049UL /**< Mode TG for DEVINFO_PART */
#define _DEVINFO_PART_DEVICE_FAMILY_EFM32LG 0x0000004AUL /**< Mode EFM32LG for DEVINFO_PART */
#define _DEVINFO_PART_DEVICE_FAMILY_LG 0x0000004AUL /**< Mode LG for DEVINFO_PART */
-#define _DEVINFO_PART_DEVICE_FAMILY_EFM32WG 0x0000004BUL /**< Mode EFM32WG for DEVINFO_PART */
#define _DEVINFO_PART_DEVICE_FAMILY_WG 0x0000004BUL /**< Mode WG for DEVINFO_PART */
+#define _DEVINFO_PART_DEVICE_FAMILY_EFM32WG 0x0000004BUL /**< Mode EFM32WG for DEVINFO_PART */
#define _DEVINFO_PART_DEVICE_FAMILY_ZG 0x0000004CUL /**< Mode ZG for DEVINFO_PART */
#define _DEVINFO_PART_DEVICE_FAMILY_EFM32ZG 0x0000004CUL /**< Mode EFM32ZG for DEVINFO_PART */
-#define _DEVINFO_PART_DEVICE_FAMILY_HG 0x0000004DUL /**< Mode HG for DEVINFO_PART */
#define _DEVINFO_PART_DEVICE_FAMILY_EFM32HG 0x0000004DUL /**< Mode EFM32HG for DEVINFO_PART */
+#define _DEVINFO_PART_DEVICE_FAMILY_HG 0x0000004DUL /**< Mode HG for DEVINFO_PART */
#define _DEVINFO_PART_DEVICE_FAMILY_EFM32PG1B 0x00000051UL /**< Mode EFM32PG1B for DEVINFO_PART */
#define _DEVINFO_PART_DEVICE_FAMILY_EFM32JG1B 0x00000053UL /**< Mode EFM32JG1B for DEVINFO_PART */
#define _DEVINFO_PART_DEVICE_FAMILY_EFM32PG12B 0x00000055UL /**< Mode EFM32PG12B for DEVINFO_PART */
@@ -359,6 +360,8 @@ typedef struct {
#define DEVINFO_PART_DEVICE_FAMILY_EFR32BG13B (_DEVINFO_PART_DEVICE_FAMILY_EFR32BG13B << 16) /**< Shifted mode EFR32BG13B for DEVINFO_PART */
#define DEVINFO_PART_DEVICE_FAMILY_EFR32BG13V (_DEVINFO_PART_DEVICE_FAMILY_EFR32BG13V << 16) /**< Shifted mode EFR32BG13V for DEVINFO_PART */
#define DEVINFO_PART_DEVICE_FAMILY_EFR32ZG13P (_DEVINFO_PART_DEVICE_FAMILY_EFR32ZG13P << 16) /**< Shifted mode EFR32ZG13P for DEVINFO_PART */
+#define DEVINFO_PART_DEVICE_FAMILY_EFR32ZG13L (_DEVINFO_PART_DEVICE_FAMILY_EFR32ZG13L << 16) /**< Shifted mode EFR32ZG13L for DEVINFO_PART */
+#define DEVINFO_PART_DEVICE_FAMILY_EFR32ZG13S (_DEVINFO_PART_DEVICE_FAMILY_EFR32ZG13S << 16) /**< Shifted mode EFR32ZG13S for DEVINFO_PART */
#define DEVINFO_PART_DEVICE_FAMILY_EFR32FG13P (_DEVINFO_PART_DEVICE_FAMILY_EFR32FG13P << 16) /**< Shifted mode EFR32FG13P for DEVINFO_PART */
#define DEVINFO_PART_DEVICE_FAMILY_EFR32FG13B (_DEVINFO_PART_DEVICE_FAMILY_EFR32FG13B << 16) /**< Shifted mode EFR32FG13B for DEVINFO_PART */
#define DEVINFO_PART_DEVICE_FAMILY_EFR32FG13V (_DEVINFO_PART_DEVICE_FAMILY_EFR32FG13V << 16) /**< Shifted mode EFR32FG13V for DEVINFO_PART */
@@ -376,16 +379,16 @@ typedef struct {
#define DEVINFO_PART_DEVICE_FAMILY_G (_DEVINFO_PART_DEVICE_FAMILY_G << 16) /**< Shifted mode G for DEVINFO_PART */
#define DEVINFO_PART_DEVICE_FAMILY_EFM32GG (_DEVINFO_PART_DEVICE_FAMILY_EFM32GG << 16) /**< Shifted mode EFM32GG for DEVINFO_PART */
#define DEVINFO_PART_DEVICE_FAMILY_GG (_DEVINFO_PART_DEVICE_FAMILY_GG << 16) /**< Shifted mode GG for DEVINFO_PART */
-#define DEVINFO_PART_DEVICE_FAMILY_TG (_DEVINFO_PART_DEVICE_FAMILY_TG << 16) /**< Shifted mode TG for DEVINFO_PART */
#define DEVINFO_PART_DEVICE_FAMILY_EFM32TG (_DEVINFO_PART_DEVICE_FAMILY_EFM32TG << 16) /**< Shifted mode EFM32TG for DEVINFO_PART */
+#define DEVINFO_PART_DEVICE_FAMILY_TG (_DEVINFO_PART_DEVICE_FAMILY_TG << 16) /**< Shifted mode TG for DEVINFO_PART */
#define DEVINFO_PART_DEVICE_FAMILY_EFM32LG (_DEVINFO_PART_DEVICE_FAMILY_EFM32LG << 16) /**< Shifted mode EFM32LG for DEVINFO_PART */
#define DEVINFO_PART_DEVICE_FAMILY_LG (_DEVINFO_PART_DEVICE_FAMILY_LG << 16) /**< Shifted mode LG for DEVINFO_PART */
-#define DEVINFO_PART_DEVICE_FAMILY_EFM32WG (_DEVINFO_PART_DEVICE_FAMILY_EFM32WG << 16) /**< Shifted mode EFM32WG for DEVINFO_PART */
#define DEVINFO_PART_DEVICE_FAMILY_WG (_DEVINFO_PART_DEVICE_FAMILY_WG << 16) /**< Shifted mode WG for DEVINFO_PART */
+#define DEVINFO_PART_DEVICE_FAMILY_EFM32WG (_DEVINFO_PART_DEVICE_FAMILY_EFM32WG << 16) /**< Shifted mode EFM32WG for DEVINFO_PART */
#define DEVINFO_PART_DEVICE_FAMILY_ZG (_DEVINFO_PART_DEVICE_FAMILY_ZG << 16) /**< Shifted mode ZG for DEVINFO_PART */
#define DEVINFO_PART_DEVICE_FAMILY_EFM32ZG (_DEVINFO_PART_DEVICE_FAMILY_EFM32ZG << 16) /**< Shifted mode EFM32ZG for DEVINFO_PART */
-#define DEVINFO_PART_DEVICE_FAMILY_HG (_DEVINFO_PART_DEVICE_FAMILY_HG << 16) /**< Shifted mode HG for DEVINFO_PART */
#define DEVINFO_PART_DEVICE_FAMILY_EFM32HG (_DEVINFO_PART_DEVICE_FAMILY_EFM32HG << 16) /**< Shifted mode EFM32HG for DEVINFO_PART */
+#define DEVINFO_PART_DEVICE_FAMILY_HG (_DEVINFO_PART_DEVICE_FAMILY_HG << 16) /**< Shifted mode HG for DEVINFO_PART */
#define DEVINFO_PART_DEVICE_FAMILY_EFM32PG1B (_DEVINFO_PART_DEVICE_FAMILY_EFM32PG1B << 16) /**< Shifted mode EFM32PG1B for DEVINFO_PART */
#define DEVINFO_PART_DEVICE_FAMILY_EFM32JG1B (_DEVINFO_PART_DEVICE_FAMILY_EFM32JG1B << 16) /**< Shifted mode EFM32JG1B for DEVINFO_PART */
#define DEVINFO_PART_DEVICE_FAMILY_EFM32PG12B (_DEVINFO_PART_DEVICE_FAMILY_EFM32PG12B << 16) /**< Shifted mode EFM32PG12B for DEVINFO_PART */
diff --git a/cpu/efm32/families/efr32mg1p/include/vendor/efr32mg1p_dma_descriptor.h b/cpu/efm32/families/efr32mg1p/include/vendor/efr32mg1p_dma_descriptor.h
index 14419ac2d8..057cbe399f 100644
--- a/cpu/efm32/families/efr32mg1p/include/vendor/efr32mg1p_dma_descriptor.h
+++ b/cpu/efm32/families/efr32mg1p/include/vendor/efr32mg1p_dma_descriptor.h
@@ -1,10 +1,9 @@
/***************************************************************************//**
* @file
* @brief EFR32MG1P_DMA_DESCRIPTOR register and bit field definitions
- * @version 5.8.3
*******************************************************************************
* # License
- * Copyright 2019 Silicon Laboratories Inc. www.silabs.com
+ * Copyright 2020 Silicon Laboratories Inc. www.silabs.com
*******************************************************************************
*
* SPDX-License-Identifier: Zlib
diff --git a/cpu/efm32/families/efr32mg1p/include/vendor/efr32mg1p_dmareq.h b/cpu/efm32/families/efr32mg1p/include/vendor/efr32mg1p_dmareq.h
index 7779fa3131..a5018681df 100644
--- a/cpu/efm32/families/efr32mg1p/include/vendor/efr32mg1p_dmareq.h
+++ b/cpu/efm32/families/efr32mg1p/include/vendor/efr32mg1p_dmareq.h
@@ -1,10 +1,9 @@
/***************************************************************************//**
* @file
* @brief EFR32MG1P_DMAREQ register and bit field definitions
- * @version 5.8.3
*******************************************************************************
* # License
- * Copyright 2019 Silicon Laboratories Inc. www.silabs.com
+ * Copyright 2020 Silicon Laboratories Inc. www.silabs.com
*******************************************************************************
*
* SPDX-License-Identifier: Zlib
diff --git a/cpu/efm32/families/efr32mg1p/include/vendor/efr32mg1p_emu.h b/cpu/efm32/families/efr32mg1p/include/vendor/efr32mg1p_emu.h
index 9e346164f5..d6587d2c57 100644
--- a/cpu/efm32/families/efr32mg1p/include/vendor/efr32mg1p_emu.h
+++ b/cpu/efm32/families/efr32mg1p/include/vendor/efr32mg1p_emu.h
@@ -1,10 +1,9 @@
/***************************************************************************//**
* @file
* @brief EFR32MG1P_EMU register and bit field definitions
- * @version 5.8.3
*******************************************************************************
* # License
- * Copyright 2019 Silicon Laboratories Inc. www.silabs.com
+ * Copyright 2020 Silicon Laboratories Inc. www.silabs.com
*******************************************************************************
*
* SPDX-License-Identifier: Zlib
@@ -167,13 +166,13 @@ typedef struct {
#define _EMU_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for EMU_LOCKKEY */
#define _EMU_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for EMU_LOCKKEY */
#define _EMU_LOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_LOCK */
-#define _EMU_LOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for EMU_LOCK */
#define _EMU_LOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for EMU_LOCK */
+#define _EMU_LOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for EMU_LOCK */
#define _EMU_LOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for EMU_LOCK */
#define _EMU_LOCK_LOCKKEY_UNLOCK 0x0000ADE8UL /**< Mode UNLOCK for EMU_LOCK */
#define EMU_LOCK_LOCKKEY_DEFAULT (_EMU_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_LOCK */
-#define EMU_LOCK_LOCKKEY_LOCK (_EMU_LOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for EMU_LOCK */
#define EMU_LOCK_LOCKKEY_UNLOCKED (_EMU_LOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for EMU_LOCK */
+#define EMU_LOCK_LOCKKEY_LOCK (_EMU_LOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for EMU_LOCK */
#define EMU_LOCK_LOCKKEY_LOCKED (_EMU_LOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for EMU_LOCK */
#define EMU_LOCK_LOCKKEY_UNLOCK (_EMU_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for EMU_LOCK */
@@ -673,13 +672,13 @@ typedef struct {
#define _EMU_PWRLOCK_LOCKKEY_SHIFT 0 /**< Shift value for EMU_LOCKKEY */
#define _EMU_PWRLOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for EMU_LOCKKEY */
#define _EMU_PWRLOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_PWRLOCK */
-#define _EMU_PWRLOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for EMU_PWRLOCK */
#define _EMU_PWRLOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for EMU_PWRLOCK */
+#define _EMU_PWRLOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for EMU_PWRLOCK */
#define _EMU_PWRLOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for EMU_PWRLOCK */
#define _EMU_PWRLOCK_LOCKKEY_UNLOCK 0x0000ADE8UL /**< Mode UNLOCK for EMU_PWRLOCK */
#define EMU_PWRLOCK_LOCKKEY_DEFAULT (_EMU_PWRLOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_PWRLOCK */
-#define EMU_PWRLOCK_LOCKKEY_LOCK (_EMU_PWRLOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for EMU_PWRLOCK */
#define EMU_PWRLOCK_LOCKKEY_UNLOCKED (_EMU_PWRLOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for EMU_PWRLOCK */
+#define EMU_PWRLOCK_LOCKKEY_LOCK (_EMU_PWRLOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for EMU_PWRLOCK */
#define EMU_PWRLOCK_LOCKKEY_LOCKED (_EMU_PWRLOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for EMU_PWRLOCK */
#define EMU_PWRLOCK_LOCKKEY_UNLOCK (_EMU_PWRLOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for EMU_PWRLOCK */
@@ -1094,13 +1093,13 @@ typedef struct {
#define _EMU_TESTLOCK_LOCKKEY_SHIFT 0 /**< Shift value for EMU_LOCKKEY */
#define _EMU_TESTLOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for EMU_LOCKKEY */
#define _EMU_TESTLOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_TESTLOCK */
-#define _EMU_TESTLOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for EMU_TESTLOCK */
#define _EMU_TESTLOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for EMU_TESTLOCK */
+#define _EMU_TESTLOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for EMU_TESTLOCK */
#define _EMU_TESTLOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for EMU_TESTLOCK */
#define _EMU_TESTLOCK_LOCKKEY_UNLOCK 0x0000ADE8UL /**< Mode UNLOCK for EMU_TESTLOCK */
#define EMU_TESTLOCK_LOCKKEY_DEFAULT (_EMU_TESTLOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_TESTLOCK */
-#define EMU_TESTLOCK_LOCKKEY_LOCK (_EMU_TESTLOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for EMU_TESTLOCK */
#define EMU_TESTLOCK_LOCKKEY_UNLOCKED (_EMU_TESTLOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for EMU_TESTLOCK */
+#define EMU_TESTLOCK_LOCKKEY_LOCK (_EMU_TESTLOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for EMU_TESTLOCK */
#define EMU_TESTLOCK_LOCKKEY_LOCKED (_EMU_TESTLOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for EMU_TESTLOCK */
#define EMU_TESTLOCK_LOCKKEY_UNLOCK (_EMU_TESTLOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for EMU_TESTLOCK */
diff --git a/cpu/efm32/families/efr32mg1p/include/vendor/efr32mg1p_fpueh.h b/cpu/efm32/families/efr32mg1p/include/vendor/efr32mg1p_fpueh.h
index 762e559561..29a7be1584 100644
--- a/cpu/efm32/families/efr32mg1p/include/vendor/efr32mg1p_fpueh.h
+++ b/cpu/efm32/families/efr32mg1p/include/vendor/efr32mg1p_fpueh.h
@@ -1,10 +1,9 @@
/***************************************************************************//**
* @file
* @brief EFR32MG1P_FPUEH register and bit field definitions
- * @version 5.8.3
*******************************************************************************
* # License
- * Copyright 2019 Silicon Laboratories Inc. www.silabs.com
+ * Copyright 2020 Silicon Laboratories Inc. www.silabs.com
*******************************************************************************
*
* SPDX-License-Identifier: Zlib
diff --git a/cpu/efm32/families/efr32mg1p/include/vendor/efr32mg1p_gpcrc.h b/cpu/efm32/families/efr32mg1p/include/vendor/efr32mg1p_gpcrc.h
index 2c2a2be776..81b0309785 100644
--- a/cpu/efm32/families/efr32mg1p/include/vendor/efr32mg1p_gpcrc.h
+++ b/cpu/efm32/families/efr32mg1p/include/vendor/efr32mg1p_gpcrc.h
@@ -1,10 +1,9 @@
/***************************************************************************//**
* @file
* @brief EFR32MG1P_GPCRC register and bit field definitions
- * @version 5.8.3
*******************************************************************************
* # License
- * Copyright 2019 Silicon Laboratories Inc. www.silabs.com
+ * Copyright 2020 Silicon Laboratories Inc. www.silabs.com
*******************************************************************************
*
* SPDX-License-Identifier: Zlib
diff --git a/cpu/efm32/families/efr32mg1p/include/vendor/efr32mg1p_gpio.h b/cpu/efm32/families/efr32mg1p/include/vendor/efr32mg1p_gpio.h
index be6abd2fcc..f3d667b9af 100644
--- a/cpu/efm32/families/efr32mg1p/include/vendor/efr32mg1p_gpio.h
+++ b/cpu/efm32/families/efr32mg1p/include/vendor/efr32mg1p_gpio.h
@@ -1,10 +1,9 @@
/***************************************************************************//**
* @file
* @brief EFR32MG1P_GPIO register and bit field definitions
- * @version 5.8.3
*******************************************************************************
* # License
- * Copyright 2019 Silicon Laboratories Inc. www.silabs.com
+ * Copyright 2020 Silicon Laboratories Inc. www.silabs.com
*******************************************************************************
*
* SPDX-License-Identifier: Zlib
@@ -1350,13 +1349,13 @@ typedef struct {
#define _GPIO_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for GPIO_LOCKKEY */
#define _GPIO_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for GPIO_LOCKKEY */
#define _GPIO_LOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_LOCK */
-#define _GPIO_LOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for GPIO_LOCK */
#define _GPIO_LOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for GPIO_LOCK */
+#define _GPIO_LOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for GPIO_LOCK */
#define _GPIO_LOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for GPIO_LOCK */
#define _GPIO_LOCK_LOCKKEY_UNLOCK 0x0000A534UL /**< Mode UNLOCK for GPIO_LOCK */
#define GPIO_LOCK_LOCKKEY_DEFAULT (_GPIO_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_LOCK */
-#define GPIO_LOCK_LOCKKEY_LOCK (_GPIO_LOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for GPIO_LOCK */
#define GPIO_LOCK_LOCKKEY_UNLOCKED (_GPIO_LOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for GPIO_LOCK */
+#define GPIO_LOCK_LOCKKEY_LOCK (_GPIO_LOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for GPIO_LOCK */
#define GPIO_LOCK_LOCKKEY_LOCKED (_GPIO_LOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for GPIO_LOCK */
#define GPIO_LOCK_LOCKKEY_UNLOCK (_GPIO_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for GPIO_LOCK */
diff --git a/cpu/efm32/families/efr32mg1p/include/vendor/efr32mg1p_gpio_p.h b/cpu/efm32/families/efr32mg1p/include/vendor/efr32mg1p_gpio_p.h
index 7ec5a3cdf4..c272537d0d 100644
--- a/cpu/efm32/families/efr32mg1p/include/vendor/efr32mg1p_gpio_p.h
+++ b/cpu/efm32/families/efr32mg1p/include/vendor/efr32mg1p_gpio_p.h
@@ -1,10 +1,9 @@
/***************************************************************************//**
* @file
* @brief EFR32MG1P_GPIO_P register and bit field definitions
- * @version 5.8.3
*******************************************************************************
* # License
- * Copyright 2019 Silicon Laboratories Inc. www.silabs.com
+ * Copyright 2020 Silicon Laboratories Inc. www.silabs.com
*******************************************************************************
*
* SPDX-License-Identifier: Zlib
diff --git a/cpu/efm32/families/efr32mg1p/include/vendor/efr32mg1p_i2c.h b/cpu/efm32/families/efr32mg1p/include/vendor/efr32mg1p_i2c.h
index 1efd280d00..8e79bde7dd 100644
--- a/cpu/efm32/families/efr32mg1p/include/vendor/efr32mg1p_i2c.h
+++ b/cpu/efm32/families/efr32mg1p/include/vendor/efr32mg1p_i2c.h
@@ -1,10 +1,9 @@
/***************************************************************************//**
* @file
* @brief EFR32MG1P_I2C register and bit field definitions
- * @version 5.8.3
*******************************************************************************
* # License
- * Copyright 2019 Silicon Laboratories Inc. www.silabs.com
+ * Copyright 2020 Silicon Laboratories Inc. www.silabs.com
*******************************************************************************
*
* SPDX-License-Identifier: Zlib
diff --git a/cpu/efm32/families/efr32mg1p/include/vendor/efr32mg1p_idac.h b/cpu/efm32/families/efr32mg1p/include/vendor/efr32mg1p_idac.h
index d469180d03..8ba4367263 100644
--- a/cpu/efm32/families/efr32mg1p/include/vendor/efr32mg1p_idac.h
+++ b/cpu/efm32/families/efr32mg1p/include/vendor/efr32mg1p_idac.h
@@ -1,10 +1,9 @@
/***************************************************************************//**
* @file
* @brief EFR32MG1P_IDAC register and bit field definitions
- * @version 5.8.3
*******************************************************************************
* # License
- * Copyright 2019 Silicon Laboratories Inc. www.silabs.com
+ * Copyright 2020 Silicon Laboratories Inc. www.silabs.com
*******************************************************************************
*
* SPDX-License-Identifier: Zlib
diff --git a/cpu/efm32/families/efr32mg1p/include/vendor/efr32mg1p_ldma.h b/cpu/efm32/families/efr32mg1p/include/vendor/efr32mg1p_ldma.h
index 079317b830..ea1f80f02a 100644
--- a/cpu/efm32/families/efr32mg1p/include/vendor/efr32mg1p_ldma.h
+++ b/cpu/efm32/families/efr32mg1p/include/vendor/efr32mg1p_ldma.h
@@ -1,10 +1,9 @@
/***************************************************************************//**
* @file
* @brief EFR32MG1P_LDMA register and bit field definitions
- * @version 5.8.3
*******************************************************************************
* # License
- * Copyright 2019 Silicon Laboratories Inc. www.silabs.com
+ * Copyright 2020 Silicon Laboratories Inc. www.silabs.com
*******************************************************************************
*
* SPDX-License-Identifier: Zlib
diff --git a/cpu/efm32/families/efr32mg1p/include/vendor/efr32mg1p_ldma_ch.h b/cpu/efm32/families/efr32mg1p/include/vendor/efr32mg1p_ldma_ch.h
index 95d05b2f37..291ec6589d 100644
--- a/cpu/efm32/families/efr32mg1p/include/vendor/efr32mg1p_ldma_ch.h
+++ b/cpu/efm32/families/efr32mg1p/include/vendor/efr32mg1p_ldma_ch.h
@@ -1,10 +1,9 @@
/***************************************************************************//**
* @file
* @brief EFR32MG1P_LDMA_CH register and bit field definitions
- * @version 5.8.3
*******************************************************************************
* # License
- * Copyright 2019 Silicon Laboratories Inc. www.silabs.com
+ * Copyright 2020 Silicon Laboratories Inc. www.silabs.com
*******************************************************************************
*
* SPDX-License-Identifier: Zlib
diff --git a/cpu/efm32/families/efr32mg1p/include/vendor/efr32mg1p_letimer.h b/cpu/efm32/families/efr32mg1p/include/vendor/efr32mg1p_letimer.h
index 0fa3857728..37b67eaefb 100644
--- a/cpu/efm32/families/efr32mg1p/include/vendor/efr32mg1p_letimer.h
+++ b/cpu/efm32/families/efr32mg1p/include/vendor/efr32mg1p_letimer.h
@@ -1,10 +1,9 @@
/***************************************************************************//**
* @file
* @brief EFR32MG1P_LETIMER register and bit field definitions
- * @version 5.8.3
*******************************************************************************
* # License
- * Copyright 2019 Silicon Laboratories Inc. www.silabs.com
+ * Copyright 2020 Silicon Laboratories Inc. www.silabs.com
*******************************************************************************
*
* SPDX-License-Identifier: Zlib
diff --git a/cpu/efm32/families/efr32mg1p/include/vendor/efr32mg1p_leuart.h b/cpu/efm32/families/efr32mg1p/include/vendor/efr32mg1p_leuart.h
index 5f194ffa01..6f864245cc 100644
--- a/cpu/efm32/families/efr32mg1p/include/vendor/efr32mg1p_leuart.h
+++ b/cpu/efm32/families/efr32mg1p/include/vendor/efr32mg1p_leuart.h
@@ -1,10 +1,9 @@
/***************************************************************************//**
* @file
* @brief EFR32MG1P_LEUART register and bit field definitions
- * @version 5.8.3
*******************************************************************************
* # License
- * Copyright 2019 Silicon Laboratories Inc. www.silabs.com
+ * Copyright 2020 Silicon Laboratories Inc. www.silabs.com
*******************************************************************************
*
* SPDX-License-Identifier: Zlib
diff --git a/cpu/efm32/families/efr32mg1p/include/vendor/efr32mg1p_msc.h b/cpu/efm32/families/efr32mg1p/include/vendor/efr32mg1p_msc.h
index d22d478a56..5aa4db3a17 100644
--- a/cpu/efm32/families/efr32mg1p/include/vendor/efr32mg1p_msc.h
+++ b/cpu/efm32/families/efr32mg1p/include/vendor/efr32mg1p_msc.h
@@ -1,10 +1,9 @@
/***************************************************************************//**
* @file
* @brief EFR32MG1P_MSC register and bit field definitions
- * @version 5.8.3
*******************************************************************************
* # License
- * Copyright 2019 Silicon Laboratories Inc. www.silabs.com
+ * Copyright 2020 Silicon Laboratories Inc. www.silabs.com
*******************************************************************************
*
* SPDX-License-Identifier: Zlib
@@ -408,13 +407,13 @@ typedef struct {
#define _MSC_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for MSC_LOCKKEY */
#define _MSC_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for MSC_LOCKKEY */
#define _MSC_LOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_LOCK */
-#define _MSC_LOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for MSC_LOCK */
#define _MSC_LOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for MSC_LOCK */
+#define _MSC_LOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for MSC_LOCK */
#define _MSC_LOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for MSC_LOCK */
#define _MSC_LOCK_LOCKKEY_UNLOCK 0x00001B71UL /**< Mode UNLOCK for MSC_LOCK */
#define MSC_LOCK_LOCKKEY_DEFAULT (_MSC_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_LOCK */
-#define MSC_LOCK_LOCKKEY_LOCK (_MSC_LOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for MSC_LOCK */
#define MSC_LOCK_LOCKKEY_UNLOCKED (_MSC_LOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for MSC_LOCK */
+#define MSC_LOCK_LOCKKEY_LOCK (_MSC_LOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for MSC_LOCK */
#define MSC_LOCK_LOCKKEY_LOCKED (_MSC_LOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for MSC_LOCK */
#define MSC_LOCK_LOCKKEY_UNLOCK (_MSC_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for MSC_LOCK */
@@ -458,13 +457,13 @@ typedef struct {
#define _MSC_MASSLOCK_MASK 0x0000FFFFUL /**< Mask for MSC_MASSLOCK */
#define _MSC_MASSLOCK_LOCKKEY_SHIFT 0 /**< Shift value for MSC_LOCKKEY */
#define _MSC_MASSLOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for MSC_LOCKKEY */
-#define _MSC_MASSLOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for MSC_MASSLOCK */
#define _MSC_MASSLOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for MSC_MASSLOCK */
+#define _MSC_MASSLOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for MSC_MASSLOCK */
#define _MSC_MASSLOCK_LOCKKEY_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_MASSLOCK */
#define _MSC_MASSLOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for MSC_MASSLOCK */
#define _MSC_MASSLOCK_LOCKKEY_UNLOCK 0x0000631AUL /**< Mode UNLOCK for MSC_MASSLOCK */
-#define MSC_MASSLOCK_LOCKKEY_LOCK (_MSC_MASSLOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for MSC_MASSLOCK */
#define MSC_MASSLOCK_LOCKKEY_UNLOCKED (_MSC_MASSLOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for MSC_MASSLOCK */
+#define MSC_MASSLOCK_LOCKKEY_LOCK (_MSC_MASSLOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for MSC_MASSLOCK */
#define MSC_MASSLOCK_LOCKKEY_DEFAULT (_MSC_MASSLOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_MASSLOCK */
#define MSC_MASSLOCK_LOCKKEY_LOCKED (_MSC_MASSLOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for MSC_MASSLOCK */
#define MSC_MASSLOCK_LOCKKEY_UNLOCK (_MSC_MASSLOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for MSC_MASSLOCK */
diff --git a/cpu/efm32/families/efr32mg1p/include/vendor/efr32mg1p_pcnt.h b/cpu/efm32/families/efr32mg1p/include/vendor/efr32mg1p_pcnt.h
index 7748520357..0a101dc984 100644
--- a/cpu/efm32/families/efr32mg1p/include/vendor/efr32mg1p_pcnt.h
+++ b/cpu/efm32/families/efr32mg1p/include/vendor/efr32mg1p_pcnt.h
@@ -1,10 +1,9 @@
/***************************************************************************//**
* @file
* @brief EFR32MG1P_PCNT register and bit field definitions
- * @version 5.8.3
*******************************************************************************
* # License
- * Copyright 2019 Silicon Laboratories Inc. www.silabs.com
+ * Copyright 2020 Silicon Laboratories Inc. www.silabs.com
*******************************************************************************
*
* SPDX-License-Identifier: Zlib
diff --git a/cpu/efm32/families/efr32mg1p/include/vendor/efr32mg1p_prs.h b/cpu/efm32/families/efr32mg1p/include/vendor/efr32mg1p_prs.h
index 173ec9d4b9..56b38e0a55 100644
--- a/cpu/efm32/families/efr32mg1p/include/vendor/efr32mg1p_prs.h
+++ b/cpu/efm32/families/efr32mg1p/include/vendor/efr32mg1p_prs.h
@@ -1,10 +1,9 @@
/***************************************************************************//**
* @file
* @brief EFR32MG1P_PRS register and bit field definitions
- * @version 5.8.3
*******************************************************************************
* # License
- * Copyright 2019 Silicon Laboratories Inc. www.silabs.com
+ * Copyright 2020 Silicon Laboratories Inc. www.silabs.com
*******************************************************************************
*
* SPDX-License-Identifier: Zlib
diff --git a/cpu/efm32/families/efr32mg1p/include/vendor/efr32mg1p_prs_ch.h b/cpu/efm32/families/efr32mg1p/include/vendor/efr32mg1p_prs_ch.h
index 801f4a22a5..bd1975a9ee 100644
--- a/cpu/efm32/families/efr32mg1p/include/vendor/efr32mg1p_prs_ch.h
+++ b/cpu/efm32/families/efr32mg1p/include/vendor/efr32mg1p_prs_ch.h
@@ -1,10 +1,9 @@
/***************************************************************************//**
* @file
* @brief EFR32MG1P_PRS_CH register and bit field definitions
- * @version 5.8.3
*******************************************************************************
* # License
- * Copyright 2019 Silicon Laboratories Inc. www.silabs.com
+ * Copyright 2020 Silicon Laboratories Inc. www.silabs.com
*******************************************************************************
*
* SPDX-License-Identifier: Zlib
diff --git a/cpu/efm32/families/efr32mg1p/include/vendor/efr32mg1p_prs_signals.h b/cpu/efm32/families/efr32mg1p/include/vendor/efr32mg1p_prs_signals.h
index ed463658d9..28ef989242 100644
--- a/cpu/efm32/families/efr32mg1p/include/vendor/efr32mg1p_prs_signals.h
+++ b/cpu/efm32/families/efr32mg1p/include/vendor/efr32mg1p_prs_signals.h
@@ -1,10 +1,9 @@
/***************************************************************************//**
* @file
* @brief EFR32MG1P_PRS_SIGNALS register and bit field definitions
- * @version 5.8.3
*******************************************************************************
* # License
- * Copyright 2019 Silicon Laboratories Inc. www.silabs.com
+ * Copyright 2020 Silicon Laboratories Inc. www.silabs.com
*******************************************************************************
*
* SPDX-License-Identifier: Zlib
diff --git a/cpu/efm32/families/efr32mg1p/include/vendor/efr32mg1p_rmu.h b/cpu/efm32/families/efr32mg1p/include/vendor/efr32mg1p_rmu.h
index bbb8609870..bd6e21697b 100644
--- a/cpu/efm32/families/efr32mg1p/include/vendor/efr32mg1p_rmu.h
+++ b/cpu/efm32/families/efr32mg1p/include/vendor/efr32mg1p_rmu.h
@@ -1,10 +1,9 @@
/***************************************************************************//**
* @file
* @brief EFR32MG1P_RMU register and bit field definitions
- * @version 5.8.3
*******************************************************************************
* # License
- * Copyright 2019 Silicon Laboratories Inc. www.silabs.com
+ * Copyright 2020 Silicon Laboratories Inc. www.silabs.com
*******************************************************************************
*
* SPDX-License-Identifier: Zlib
@@ -189,13 +188,13 @@ typedef struct {
#define _RMU_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for RMU_LOCKKEY */
#define _RMU_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for RMU_LOCKKEY */
#define _RMU_LOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for RMU_LOCK */
-#define _RMU_LOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for RMU_LOCK */
#define _RMU_LOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for RMU_LOCK */
+#define _RMU_LOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for RMU_LOCK */
#define _RMU_LOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for RMU_LOCK */
#define _RMU_LOCK_LOCKKEY_UNLOCK 0x0000E084UL /**< Mode UNLOCK for RMU_LOCK */
#define RMU_LOCK_LOCKKEY_DEFAULT (_RMU_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for RMU_LOCK */
-#define RMU_LOCK_LOCKKEY_LOCK (_RMU_LOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for RMU_LOCK */
#define RMU_LOCK_LOCKKEY_UNLOCKED (_RMU_LOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for RMU_LOCK */
+#define RMU_LOCK_LOCKKEY_LOCK (_RMU_LOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for RMU_LOCK */
#define RMU_LOCK_LOCKKEY_LOCKED (_RMU_LOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for RMU_LOCK */
#define RMU_LOCK_LOCKKEY_UNLOCK (_RMU_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for RMU_LOCK */
diff --git a/cpu/efm32/families/efr32mg1p/include/vendor/efr32mg1p_romtable.h b/cpu/efm32/families/efr32mg1p/include/vendor/efr32mg1p_romtable.h
index c38585cb4e..5202487289 100644
--- a/cpu/efm32/families/efr32mg1p/include/vendor/efr32mg1p_romtable.h
+++ b/cpu/efm32/families/efr32mg1p/include/vendor/efr32mg1p_romtable.h
@@ -1,10 +1,9 @@
/***************************************************************************//**
* @file
* @brief EFR32MG1P_ROMTABLE register and bit field definitions
- * @version 5.8.3
*******************************************************************************
* # License
- * Copyright 2019 Silicon Laboratories Inc. www.silabs.com
+ * Copyright 2020 Silicon Laboratories Inc. www.silabs.com
*******************************************************************************
*
* SPDX-License-Identifier: Zlib
diff --git a/cpu/efm32/families/efr32mg1p/include/vendor/efr32mg1p_rtcc.h b/cpu/efm32/families/efr32mg1p/include/vendor/efr32mg1p_rtcc.h
index 0c821775ab..68187548a9 100644
--- a/cpu/efm32/families/efr32mg1p/include/vendor/efr32mg1p_rtcc.h
+++ b/cpu/efm32/families/efr32mg1p/include/vendor/efr32mg1p_rtcc.h
@@ -1,10 +1,9 @@
/***************************************************************************//**
* @file
* @brief EFR32MG1P_RTCC register and bit field definitions
- * @version 5.8.3
*******************************************************************************
* # License
- * Copyright 2019 Silicon Laboratories Inc. www.silabs.com
+ * Copyright 2020 Silicon Laboratories Inc. www.silabs.com
*******************************************************************************
*
* SPDX-License-Identifier: Zlib
@@ -531,13 +530,13 @@ typedef struct {
#define _RTCC_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for RTCC_LOCKKEY */
#define _RTCC_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for RTCC_LOCKKEY */
#define _RTCC_LOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_LOCK */
-#define _RTCC_LOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for RTCC_LOCK */
#define _RTCC_LOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for RTCC_LOCK */
+#define _RTCC_LOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for RTCC_LOCK */
#define _RTCC_LOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for RTCC_LOCK */
#define _RTCC_LOCK_LOCKKEY_UNLOCK 0x0000AEE8UL /**< Mode UNLOCK for RTCC_LOCK */
#define RTCC_LOCK_LOCKKEY_DEFAULT (_RTCC_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for RTCC_LOCK */
-#define RTCC_LOCK_LOCKKEY_LOCK (_RTCC_LOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for RTCC_LOCK */
#define RTCC_LOCK_LOCKKEY_UNLOCKED (_RTCC_LOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for RTCC_LOCK */
+#define RTCC_LOCK_LOCKKEY_LOCK (_RTCC_LOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for RTCC_LOCK */
#define RTCC_LOCK_LOCKKEY_LOCKED (_RTCC_LOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for RTCC_LOCK */
#define RTCC_LOCK_LOCKKEY_UNLOCK (_RTCC_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for RTCC_LOCK */
diff --git a/cpu/efm32/families/efr32mg1p/include/vendor/efr32mg1p_rtcc_cc.h b/cpu/efm32/families/efr32mg1p/include/vendor/efr32mg1p_rtcc_cc.h
index fdcb0fd530..e18afd7951 100644
--- a/cpu/efm32/families/efr32mg1p/include/vendor/efr32mg1p_rtcc_cc.h
+++ b/cpu/efm32/families/efr32mg1p/include/vendor/efr32mg1p_rtcc_cc.h
@@ -1,10 +1,9 @@
/***************************************************************************//**
* @file
* @brief EFR32MG1P_RTCC_CC register and bit field definitions
- * @version 5.8.3
*******************************************************************************
* # License
- * Copyright 2019 Silicon Laboratories Inc. www.silabs.com
+ * Copyright 2020 Silicon Laboratories Inc. www.silabs.com
*******************************************************************************
*
* SPDX-License-Identifier: Zlib
diff --git a/cpu/efm32/families/efr32mg1p/include/vendor/efr32mg1p_rtcc_ret.h b/cpu/efm32/families/efr32mg1p/include/vendor/efr32mg1p_rtcc_ret.h
index d8bda66c1f..7e439ca75a 100644
--- a/cpu/efm32/families/efr32mg1p/include/vendor/efr32mg1p_rtcc_ret.h
+++ b/cpu/efm32/families/efr32mg1p/include/vendor/efr32mg1p_rtcc_ret.h
@@ -1,10 +1,9 @@
/***************************************************************************//**
* @file
* @brief EFR32MG1P_RTCC_RET register and bit field definitions
- * @version 5.8.3
*******************************************************************************
* # License
- * Copyright 2019 Silicon Laboratories Inc. www.silabs.com
+ * Copyright 2020 Silicon Laboratories Inc. www.silabs.com
*******************************************************************************
*
* SPDX-License-Identifier: Zlib
diff --git a/cpu/efm32/families/efr32mg1p/include/vendor/efr32mg1p_timer.h b/cpu/efm32/families/efr32mg1p/include/vendor/efr32mg1p_timer.h
index c5981da94a..fc2a072a19 100644
--- a/cpu/efm32/families/efr32mg1p/include/vendor/efr32mg1p_timer.h
+++ b/cpu/efm32/families/efr32mg1p/include/vendor/efr32mg1p_timer.h
@@ -1,10 +1,9 @@
/***************************************************************************//**
* @file
* @brief EFR32MG1P_TIMER register and bit field definitions
- * @version 5.8.3
*******************************************************************************
* # License
- * Copyright 2019 Silicon Laboratories Inc. www.silabs.com
+ * Copyright 2020 Silicon Laboratories Inc. www.silabs.com
*******************************************************************************
*
* SPDX-License-Identifier: Zlib
@@ -586,13 +585,13 @@ typedef struct {
#define _TIMER_LOCK_TIMERLOCKKEY_SHIFT 0 /**< Shift value for TIMER_TIMERLOCKKEY */
#define _TIMER_LOCK_TIMERLOCKKEY_MASK 0xFFFFUL /**< Bit mask for TIMER_TIMERLOCKKEY */
#define _TIMER_LOCK_TIMERLOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_LOCK */
-#define _TIMER_LOCK_TIMERLOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for TIMER_LOCK */
#define _TIMER_LOCK_TIMERLOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for TIMER_LOCK */
+#define _TIMER_LOCK_TIMERLOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for TIMER_LOCK */
#define _TIMER_LOCK_TIMERLOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for TIMER_LOCK */
#define _TIMER_LOCK_TIMERLOCKKEY_UNLOCK 0x0000CE80UL /**< Mode UNLOCK for TIMER_LOCK */
#define TIMER_LOCK_TIMERLOCKKEY_DEFAULT (_TIMER_LOCK_TIMERLOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_LOCK */
-#define TIMER_LOCK_TIMERLOCKKEY_LOCK (_TIMER_LOCK_TIMERLOCKKEY_LOCK << 0) /**< Shifted mode LOCK for TIMER_LOCK */
#define TIMER_LOCK_TIMERLOCKKEY_UNLOCKED (_TIMER_LOCK_TIMERLOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for TIMER_LOCK */
+#define TIMER_LOCK_TIMERLOCKKEY_LOCK (_TIMER_LOCK_TIMERLOCKKEY_LOCK << 0) /**< Shifted mode LOCK for TIMER_LOCK */
#define TIMER_LOCK_TIMERLOCKKEY_LOCKED (_TIMER_LOCK_TIMERLOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for TIMER_LOCK */
#define TIMER_LOCK_TIMERLOCKKEY_UNLOCK (_TIMER_LOCK_TIMERLOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for TIMER_LOCK */
@@ -1573,13 +1572,13 @@ typedef struct {
#define _TIMER_DTLOCK_LOCKKEY_SHIFT 0 /**< Shift value for TIMER_LOCKKEY */
#define _TIMER_DTLOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for TIMER_LOCKKEY */
#define _TIMER_DTLOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTLOCK */
-#define _TIMER_DTLOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for TIMER_DTLOCK */
#define _TIMER_DTLOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for TIMER_DTLOCK */
+#define _TIMER_DTLOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for TIMER_DTLOCK */
#define _TIMER_DTLOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for TIMER_DTLOCK */
#define _TIMER_DTLOCK_LOCKKEY_UNLOCK 0x0000CE80UL /**< Mode UNLOCK for TIMER_DTLOCK */
#define TIMER_DTLOCK_LOCKKEY_DEFAULT (_TIMER_DTLOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_DTLOCK */
-#define TIMER_DTLOCK_LOCKKEY_LOCK (_TIMER_DTLOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for TIMER_DTLOCK */
#define TIMER_DTLOCK_LOCKKEY_UNLOCKED (_TIMER_DTLOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for TIMER_DTLOCK */
+#define TIMER_DTLOCK_LOCKKEY_LOCK (_TIMER_DTLOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for TIMER_DTLOCK */
#define TIMER_DTLOCK_LOCKKEY_LOCKED (_TIMER_DTLOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for TIMER_DTLOCK */
#define TIMER_DTLOCK_LOCKKEY_UNLOCK (_TIMER_DTLOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for TIMER_DTLOCK */
diff --git a/cpu/efm32/families/efr32mg1p/include/vendor/efr32mg1p_timer_cc.h b/cpu/efm32/families/efr32mg1p/include/vendor/efr32mg1p_timer_cc.h
index 947c2deeba..2f0936a207 100644
--- a/cpu/efm32/families/efr32mg1p/include/vendor/efr32mg1p_timer_cc.h
+++ b/cpu/efm32/families/efr32mg1p/include/vendor/efr32mg1p_timer_cc.h
@@ -1,10 +1,9 @@
/***************************************************************************//**
* @file
* @brief EFR32MG1P_TIMER_CC register and bit field definitions
- * @version 5.8.3
*******************************************************************************
* # License
- * Copyright 2019 Silicon Laboratories Inc. www.silabs.com
+ * Copyright 2020 Silicon Laboratories Inc. www.silabs.com
*******************************************************************************
*
* SPDX-License-Identifier: Zlib
diff --git a/cpu/efm32/families/efr32mg1p/include/vendor/efr32mg1p_usart.h b/cpu/efm32/families/efr32mg1p/include/vendor/efr32mg1p_usart.h
index 17a5cdfe07..7923c01498 100644
--- a/cpu/efm32/families/efr32mg1p/include/vendor/efr32mg1p_usart.h
+++ b/cpu/efm32/families/efr32mg1p/include/vendor/efr32mg1p_usart.h
@@ -1,10 +1,9 @@
/***************************************************************************//**
* @file
* @brief EFR32MG1P_USART register and bit field definitions
- * @version 5.8.3
*******************************************************************************
* # License
- * Copyright 2019 Silicon Laboratories Inc. www.silabs.com
+ * Copyright 2020 Silicon Laboratories Inc. www.silabs.com
*******************************************************************************
*
* SPDX-License-Identifier: Zlib
diff --git a/cpu/efm32/families/efr32mg1p/include/vendor/efr32mg1p_wdog.h b/cpu/efm32/families/efr32mg1p/include/vendor/efr32mg1p_wdog.h
index 975c28b8e5..5fa4f7b830 100644
--- a/cpu/efm32/families/efr32mg1p/include/vendor/efr32mg1p_wdog.h
+++ b/cpu/efm32/families/efr32mg1p/include/vendor/efr32mg1p_wdog.h
@@ -1,10 +1,9 @@
/***************************************************************************//**
* @file
* @brief EFR32MG1P_WDOG register and bit field definitions
- * @version 5.8.3
*******************************************************************************
* # License
- * Copyright 2019 Silicon Laboratories Inc. www.silabs.com
+ * Copyright 2020 Silicon Laboratories Inc. www.silabs.com
*******************************************************************************
*
* SPDX-License-Identifier: Zlib
diff --git a/cpu/efm32/families/efr32mg1p/include/vendor/efr32mg1p_wdog_pch.h b/cpu/efm32/families/efr32mg1p/include/vendor/efr32mg1p_wdog_pch.h
index c5f4d242a7..785c3d11ae 100644
--- a/cpu/efm32/families/efr32mg1p/include/vendor/efr32mg1p_wdog_pch.h
+++ b/cpu/efm32/families/efr32mg1p/include/vendor/efr32mg1p_wdog_pch.h
@@ -1,10 +1,9 @@
/***************************************************************************//**
* @file
* @brief EFR32MG1P_WDOG_PCH register and bit field definitions
- * @version 5.8.3
*******************************************************************************
* # License
- * Copyright 2019 Silicon Laboratories Inc. www.silabs.com
+ * Copyright 2020 Silicon Laboratories Inc. www.silabs.com
*******************************************************************************
*
* SPDX-License-Identifier: Zlib
diff --git a/cpu/efm32/families/efr32mg1p/include/vendor/em_device.h b/cpu/efm32/families/efr32mg1p/include/vendor/em_device.h
index 0058e02bf0..17c7795bf3 100644
--- a/cpu/efm32/families/efr32mg1p/include/vendor/em_device.h
+++ b/cpu/efm32/families/efr32mg1p/include/vendor/em_device.h
@@ -11,10 +11,9 @@
* Add "#include "em_device.h" to your source files
* @endverbatim
*
- * @version 5.8.3
*******************************************************************************
* # License
- * Copyright 2019 Silicon Laboratories Inc. www.silabs.com
+ * Copyright 2020 Silicon Laboratories Inc. www.silabs.com
*******************************************************************************
*
* SPDX-License-Identifier: Zlib
diff --git a/cpu/efm32/families/efr32mg1p/include/vendor/system_efr32mg1p.h b/cpu/efm32/families/efr32mg1p/include/vendor/system_efr32mg1p.h
index 3997bd2e64..66b4fc13b0 100644
--- a/cpu/efm32/families/efr32mg1p/include/vendor/system_efr32mg1p.h
+++ b/cpu/efm32/families/efr32mg1p/include/vendor/system_efr32mg1p.h
@@ -1,10 +1,9 @@
/***************************************************************************//**
* @file
* @brief CMSIS Cortex-M3/M4 System Layer for EFR32 devices.
- * @version 5.8.3
*******************************************************************************
* # License
- * Copyright 2019 Silicon Laboratories Inc. www.silabs.com
+ * Copyright 2020 Silicon Laboratories Inc. www.silabs.com
*******************************************************************************
*
* SPDX-License-Identifier: Zlib
@@ -47,12 +46,29 @@ extern "C" {
* @{
******************************************************************************/
+/*******************************************************************************
+ ****************************** TYPEDEFS ***********************************
+ ******************************************************************************/
+
+/* Interrupt vectortable entry */
+typedef union {
+ void (*pFunc)(void);
+ void *topOfStack;
+} tVectorEntry;
+
/*******************************************************************************
************************** GLOBAL VARIABLES *******************************
******************************************************************************/
-extern uint32_t SystemCoreClock; /**< System Clock Frequency (Core Clock) */
-extern uint32_t SystemHfrcoFreq; /**< System HFRCO frequency */
+extern uint32_t SystemCoreClock; /**< System Clock Frequency (Core Clock) */
+extern uint32_t SystemHfrcoFreq; /**< System HFRCO frequency */
+
+#if defined(__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+#if defined(__ICCARM__) /* IAR requires the __vector_table symbol */
+#define __Vectors __vector_table
+#endif
+extern const tVectorEntry __Vectors[];
+#endif
/*******************************************************************************
***************************** PROTOTYPES **********************************
diff --git a/cpu/efm32/families/efr32mg1p/system.c b/cpu/efm32/families/efr32mg1p/system.c
index 7a71aa3ac3..c7dae5f56f 100644
--- a/cpu/efm32/families/efr32mg1p/system.c
+++ b/cpu/efm32/families/efr32mg1p/system.c
@@ -1,10 +1,9 @@
/***************************************************************************//**
* @file
* @brief CMSIS Cortex-M3/M4 System Layer for EFR32 devices.
- * @version 5.8.3
*******************************************************************************
* # License
- * Copyright 2019 Silicon Laboratories Inc. www.silabs.com
+ * Copyright 2020 Silicon Laboratories Inc. www.silabs.com
*******************************************************************************
*
* SPDX-License-Identifier: Zlib
@@ -117,13 +116,6 @@ uint32_t SystemHfrcoFreq = EFR32_HFRCO_STARTUP_FREQ;
************************** GLOBAL FUNCTIONS *******************************
******************************************************************************/
-#if defined(__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
-#if defined(__ICCARM__) /* IAR requires the __vector_table symbol */
-#define __Vectors __vector_table
-#endif
-extern uint32_t __Vectors;
-#endif
-
/***************************************************************************//**
* @brief
* Get the current core clock frequency.