diff --git a/cpu/cc2538/Kconfig b/cpu/cc2538/Kconfig
index 5b1491e3ff..221c944319 100644
--- a/cpu/cc2538/Kconfig
+++ b/cpu/cc2538/Kconfig
@@ -11,7 +11,7 @@ config CPU_FAM_CC2538
     select HAS_CPU_CC2538
     select HAS_PERIPH_CPUID
     select HAS_PERIPH_FLASHPAGE
-    select HAS_PERIPH_FLASHPAGE_RAW
+    select HAS_PERIPH_FLASHPAGE_PAGEWISE
     select HAS_PERIPH_GPIO
     select HAS_PERIPH_GPIO_IRQ
     select HAS_PERIPH_HWRNG
diff --git a/cpu/cc2538/Makefile.features b/cpu/cc2538/Makefile.features
index 2b6665241f..75dc056392 100644
--- a/cpu/cc2538/Makefile.features
+++ b/cpu/cc2538/Makefile.features
@@ -3,7 +3,7 @@ CPU_FAM = cc2538
 
 FEATURES_PROVIDED += periph_cpuid
 FEATURES_PROVIDED += periph_flashpage
-FEATURES_PROVIDED += periph_flashpage_raw
+FEATURES_PROVIDED += periph_flashpage_pagewise
 FEATURES_PROVIDED += periph_gpio periph_gpio_irq
 FEATURES_PROVIDED += periph_hwrng
 FEATURES_PROVIDED += periph_uart_modecfg
diff --git a/cpu/cc2538/include/cpu_conf.h b/cpu/cc2538/include/cpu_conf.h
index aa37cd6108..ff1c2792b9 100644
--- a/cpu/cc2538/include/cpu_conf.h
+++ b/cpu/cc2538/include/cpu_conf.h
@@ -65,9 +65,9 @@ extern "C" {
 /* The minimum block size which can be written is 4B. However, the erase
  * block is always FLASHPAGE_SIZE.
  */
-#define FLASHPAGE_RAW_BLOCKSIZE    (4U)
+#define FLASHPAGE_WRITE_BLOCK_SIZE      (4U)
 /* Writing should be always 4 bytes aligned */
-#define FLASHPAGE_RAW_ALIGNMENT    (4U)
+#define FLASHPAGE_WRITE_BLOCK_ALIGNMENT (4U)
 /** @} */
 
 #ifdef __cplusplus
diff --git a/cpu/cc2538/periph/flashpage.c b/cpu/cc2538/periph/flashpage.c
index 2278e9a5b0..1070c3ba51 100644
--- a/cpu/cc2538/periph/flashpage.c
+++ b/cpu/cc2538/periph/flashpage.c
@@ -61,16 +61,25 @@ static inline void _erase(uint32_t *page_addr)
     irq_restore(state);
 }
 
-__attribute__ ((section (".ramfunc")))
-void flashpage_write_raw(void *target_addr, const void *data, size_t len)
+void flashpage_erase(unsigned page)
 {
-    /* assert multiples of FLASHPAGE_RAW_BLOCKSIZE are written and no less of
+    assert((unsigned) page < FLASHPAGE_NUMOF);
+
+    uint32_t *page_addr = (uint32_t *)flashpage_addr(page);
+
+    _erase(page_addr);
+}
+
+__attribute__ ((section (".ramfunc")))
+void flashpage_write(void *target_addr, const void *data, size_t len)
+{
+    /* assert multiples of FLASHPAGE_WRITE_BLOCK_SIZE are written and no less of
        that length. */
-    assert(!(len % FLASHPAGE_RAW_BLOCKSIZE));
+    assert(!(len % FLASHPAGE_WRITE_BLOCK_SIZE));
 
     /* ensure writes are aligned */
-    assert(!(((unsigned)target_addr % FLASHPAGE_RAW_ALIGNMENT) ||
-            ((unsigned)data % FLASHPAGE_RAW_ALIGNMENT)));
+    assert(!(((unsigned)target_addr % FLASHPAGE_WRITE_BLOCK_ALIGNMENT) ||
+            ((unsigned)data % FLASHPAGE_WRITE_BLOCK_ALIGNMENT)));
 
     /* ensure the length doesn't exceed the actual flash size */
     assert(((unsigned)target_addr + len) <=
@@ -90,7 +99,7 @@ void flashpage_write_raw(void *target_addr, const void *data, size_t len)
     /* starts the write-sequence state machine */
     DEBUG("[flashpage_raw] write: now writing the data\n");
     FLASH_CTRL_FCTL |= FLASH_CTRL_FCTL_WRITE;
-    for (unsigned i = 0; i < (len / FLASHPAGE_RAW_BLOCKSIZE); i++) {
+    for (unsigned i = 0; i < (len / FLASHPAGE_WRITE_BLOCK_SIZE); i++) {
         FLASH_CTRL_FWDATA = (uint32_t) *(data_addr++);
         /* wait for flash operation to complete */
         while (FLASH_CTRL_FCTL & FLASH_CTRL_FCTL_FULL) {}
@@ -98,18 +107,3 @@ void flashpage_write_raw(void *target_addr, const void *data, size_t len)
     /* re-enable interrupts */
     irq_restore(state);
 }
-
-void flashpage_write(int page, const void *data)
-{
-    assert((unsigned) page < FLASHPAGE_NUMOF);
-
-    uint32_t *page_addr = (uint32_t *)flashpage_addr(page);
-
-    /* erase page */
-    _erase(page_addr);
-
-    /* write page */
-    if (data != NULL) {
-        flashpage_write_raw(page_addr, data, FLASHPAGE_SIZE);
-    }
-}