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cpu/esp32: cleanup of SPI interfaces

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Although ESP32 has four SPI controllers, only two of them can be effectively used (HSP and VSPI). The third one (FSPI) is used for external memory such as flash and PSRAM and can not be used for peripherals. FSPI is therefore removed from the API. In addition, the SPI0_DEV and SPI1_DEV configuration parameters are renamed SPI0_CTRL and SPI1_CTRL to better describe what they define and to avoid confusion with SPI_DEV (0) and SPI_DEV (1).
This commit is contained in:
Gunar Schorcht 2019-01-09 13:03:22 +01:00
parent f7e524d18e
commit 437f8b87b9
2 changed files with 20 additions and 72 deletions
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42
cpu/esp32/include/periph_cpu.h
View File

@ -339,46 +339,32 @@ extern const unsigned pwm_dev_num;
*
* ESP32 has four SPI controllers:
*
* - controller SPI0 is reserved for accessing flash memory
* - controller SPI1 realizes interface FSPI and shares its signals with SPI0
* - controller SPI0 is reserved for caching the flash memory
* - controller SPI1 is reserved for external memories like flash and PSRAM
* - controller SPI2 realizes interface HSPI that can be used for peripherals
* - controller SPI3 realizes interface VSPI that can be used for peripherals
*
* At most three interfaces can be used:
* Thus, a maximum of two SPI controllers can be used as peripheral interfaces:
*
* - VSPI with configurable pin definitions
* - HSPI with configurable pin definitions
* - FSPI with fixed pin definitions except the CS signal
* - VSPI
* - HSPI
*
* All SPI interfaces could be used in quad SPI mode, but RIOT's low level
* SPI interfaces could be used in quad SPI mode, but RIOT's low level
* device driver doesn't support it.
*
* @note
* - Since the FSPI interface shares its bus signals with the controller
* that implements the flash memory interface, we use the name FSPI for this
* interface. In the technical reference, this interface is misleadingly
* simply referred to as SPI.
* - Since the FSPI interface shares its bus signals with flash
* memory interface and optionally other external memories, you can only use
* this SPI interface to attach external memory with same SPI mode and same
* bus speed but with a different CS.
* - Using FSPI for anything else can disturb flash memory access which
* causes a number of problems. If not really necessary, you should not use
* this interface.
*
* The board-specific configuration of the SPI interface SPI_DEV(n) requires
* the defintion of
*
* SPIn_DEV, the interface which can be VSPI, HSPI, or FSPI,
* SPIn_SCK, the GPIO used as clock signal (fixed for FSPI),
* SPIn_MISO, the GPIO used as MISO signal (fixed for FSPI),
* SPIn_MOSI, the GPIO used as MOSI signal (fixed for FSPI), and
* SPIn_CS0, the GPIO used as CS signal when cs parameter in spi_aquire is GPIO_UNDEF,
* - SPIn_CTRL, the SPI controller which is used for the interface (VSPI or HSPI),
* - SPIn_SCK, the GPIO used as clock signal
* - SPIn_MISO, the GPIO used as MISO signal
* - SPIn_MOSI, the GPIO used as MOSI signal, and
* - SPIn_CS0, the GPIO used as CS signal when the cs parameter in spi_aquire
* is GPIO_UNDEF,
*
* where n can be 0, 1 or 2. If they are not defined, the SPI interface
* SPI_DEV(n) is not used.
* where n can be 0 or 1.
*
* @note The configuration of the SPI interfaces SPI_DEV(n) must be in
* @note The configuration of the SPI interfaces SPI_DEV(n) should be in
* continuous ascending order of n.
*
* SPI_NUMOF is determined automatically from the board-specific peripheral

50
cpu/esp32/periph/spi.c
View File

@ -42,6 +42,7 @@
#define SPI_BLOCK_SIZE 64 /* number of bytes per SPI transfer */
#define CSPI (0) /* controller SPI0 realizes interface CSPI */
#define FSPI (1) /* controller SPI1 realizes interface FSPI */
#define HSPI (2) /* controller SPI2 realizes interface HSPI */
#define VSPI (3) /* controller SPI3 realizes interface VSPI */
@ -70,57 +71,25 @@ struct _spi_bus_t {
};
static struct _spi_bus_t _spi[] = {
#ifdef SPI0_DEV
#ifdef SPI0_CTRL
{
.controller = SPI0_DEV,
.controller = SPI0_CTRL,
.pin_cs = SPI0_CS0,
#if SPI0_DEV != FSPI
.pin_sck = SPI0_SCK,
.pin_mosi = SPI0_MOSI,
.pin_miso = SPI0_MISO,
#else
.pin_sck = FSPI_SCK,
.pin_mosi = FSPI_MOSI,
.pin_miso = FSPI_MISO,
#endif
.initialized = false,
.pins_initialized = false,
.lock = MUTEX_INIT
},
#endif
#ifdef SPI1_DEV
#ifdef SPI1_CTRL
{
.controller = SPI1_DEV,
.controller = SPI1_CTRL,
.pin_cs = SPI1_CS0,
#if SPI1_DEV != FSPI
.pin_sck = SPI1_SCK,
.pin_mosi = SPI1_MOSI,
.pin_miso = SPI1_MISO,
#else
.pin_sck = FSPI_SCK,
.pin_mosi = FSPI_MOSI,
.pin_miso = FSPI_MISO,
#endif
.initialized = false,
.pins_initialized = false,
.lock = MUTEX_INIT
},
#endif
#ifdef SPI2_DEV
{
.controller = SPI2_DEV,
.pin_cs = SPI2_CS0,
#if SPI2_DEV != FSPI
.pin_sck = SPI2_SCK,
.pin_mosi = SPI2_MOSI,
.pin_miso = SPI2_MISO,
#else
.pin_sck = FSPI_SCK,
.pin_mosi = FSPI_MOSI,
.pin_miso = FSPI_MISO,
#endif
.initialized = false,
.pins_initialized = false,
.lock = MUTEX_INIT
@ -161,13 +130,6 @@ void IRAM_ATTR spi_init (spi_t bus)
CHECK_PARAM(bus < spi_bus_num);
switch (_spi[bus].controller) {
case FSPI: _spi[bus].regs = &SPI1;
_spi[bus].mod = PERIPH_SPI_MODULE;
_spi[bus].int_src = ETS_SPI1_INTR_SOURCE;
_spi[bus].signal_sck = SPICLK_OUT_IDX;
_spi[bus].signal_mosi = SPID_OUT_IDX;
_spi[bus].signal_miso = SPIQ_IN_IDX;
break;
case HSPI: _spi[bus].regs = &SPI2;
_spi[bus].mod = PERIPH_HSPI_MODULE;
_spi[bus].int_src = ETS_SPI2_INTR_SOURCE;
@ -412,7 +374,7 @@ void IRAM_ATTR spi_release(spi_t bus)
mutex_unlock(&_spi[bus].lock);
}
static const char* _spi_names[] = { "SSPI", "FSPI", "HSPI", "VSPI" };
static const char* _spi_names[] = { "CSPI", "FSPI", "HSPI", "VSPI" };
void spi_print_config(void)
{