diff --git a/cpu/esp32/doc.md b/cpu/esp32/doc.md index 7e045167fa..4430cf6a95 100644 --- a/cpu/esp32/doc.md +++ b/cpu/esp32/doc.md @@ -181,7 +181,7 @@ either based on - Tensilica Xtensa 32-bit LX7 microprocessor (ESP32-S2, ESP32-S3), or - 32-bit RISC-V CPU (ESP32-C3, ESP32-C3 ESP32-H2). -At the moment, ESP32, ESP32-S2, ESP32-S3, ESP32-C3 and ESP32-H2 +At the moment, ESP32, ESP32-S2, ESP32-S3, ESP32-C3, ESP32-C6 and ESP32-H2 variants (families) are supported by RIOT-OS. @note Even if the used ESP32x SoC is a dual-core version, RIOT-OS uses only @@ -268,6 +268,43 @@ The key features of ESP32-C3 are:
+### Features of The ESP32-C6 SoC variant (family) + +The key features of ESP32-C6 are: + +
+ +| MCU | ESP32-C6 | Supported by RIOT | +| ------------------|-------------------------------------------------------------------|------------------ | +| Vendor | Espressif | | +| Cores | 1 x 32-bit RISC-V core | yes | +| FPU | - | - | +| RAM | 512 KiB SRAM
16 KiB LP SRAM | yes
yes | +| ROM | 320 KiB | yes | +| Flash | 16 MiB | yes | +| Frequency | 160 MHz, 120 MHz, **80 MHz**, 40 MHz, 20 MHz | yes | +| Power Consumption | 27 mA @ 160 MHz
19 mA @ 80 MHz
180 uA in light sleep mode
7 uA in deep sleep mode | yes
yes
yes
yes | +| Timer | 2 x 54 bit | yes | +| ADC | 1 x SAR-ADC with up to 7 x 12 bit channels total | yes | +| DAC | - | - | +| GPIO | 31 | yes | +| I2C | 2 | yes | +| SPI | 3 (1 usable as general purpose SPI) | yes | +| UART | 3 (2 in high-power domain and 1 in low-power domain) | yes | +| WiFi | IEEE 802.11 b/g/n/ax built in | yes | +| Bluetooth | Bluetooth 5 (LE) | yes | +| IEEE 802.15.4 | 250 Kbps data rate in 2.4 GHz band with OQPSK PHY | yes | +| Ethernet | - | - | +| CAN | version 2.0 | yes | +| IR | up to 4 channels TX/RX | - | +| Motor PWM | 1 device x 6 channels | no | +| LED PWM | 6 channels with 20 bit resolution in 1 channel group with 4 timers| yes | +| Crypto | Hardware acceleration of AES, SHA-2, RSA, ECC, RNG | no | +| Vcc | 3.0 - 3.6 V | | +| Documents | [Datasheet](https://www.espressif.com/sites/default/files/documentation/esp32-c6_datasheet_en.pdf)
[Technical Reference](https://www.espressif.com/sites/default/files/documentation/esp32-c6_technical_reference_manual_en.pdf) | | + +

+ ### Features of The ESP32-H2 SoC variant (family) The key features of ESP32-H2 are: @@ -389,6 +426,8 @@ Most common modules used by ESP32x SoC boards are: - [ESP32-WROVER](https://www.espressif.com/sites/default/files/documentation/esp32-wrover_datasheet_en.pdf) - [ESP32-C3-MINI-1](https://www.espressif.com/sites/default/files/documentation/esp32-c3-mini-1_datasheet_en.pdf) - [ESP32-C3-WROOM-02](https://www.espressif.com/sites/default/files/documentation/esp32-c3-wroom-02_datasheet_en.pdf) +- [ESP32-C6-MINI-1](https://www.espressif.com/sites/default/files/documentation/esp32-c6-mini-1_datasheet_en.pdf) +- [ESP32-C6-WROOM-1](https://www.espressif.com/sites/default/files/documentation/esp32-c6-wroom-1_datasheet_en.pdf) - [ESP32-H2-MINI-1](https://www.espressif.com/sites/default/files/documentation/esp32-h2-mini-1_mini-1u_datasheet_en.pdf) - [ESP32-S2-MINI-1](https://www.espressif.com/sites/default/files/documentation/esp32-s2-mini-1_esp32-s2-mini-1u_datasheet_en.pdf) - [ESP32-S2-SOLO](https://www.espressif.com/sites/default/files/documentation/esp32-s2-solo_esp32-s2-solo-u_datasheet_en.pdf) @@ -502,7 +541,7 @@ install Espressif's precompiled versions of the following tools: - ESP32 vendor toolchain - GDB for ESP32x SoCs based on Xtensa or RISC-V -- OpenOCD for ESP32 (for ESP32, ESP32-S2, ESP32-S3, ESP32-C3 and ESP32-H2) +- OpenOCD for ESP32 (for ESP32, ESP32-S2, ESP32-S3, ESP32-C3, ESP32-C6 and ESP32-H2) - QEMU for ESP32x SoCs (for ESP32, ESP32-S3 and ESP32-C3) `$RIOTBASE` defines the root directory of the RIOT repository. The shell @@ -514,7 +553,7 @@ $ dist/tools/esptools/install.sh Usage: install.sh install.sh gdb install.sh qemu - = all | gdb | openocd | qemu | + = all | esptool | gdb | openocd | qemu | esp8266 | esp32 | esp32c3 | esp32h2 | esp32s2 | esp32s3 = xtensa | riscv ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ @@ -546,7 +585,7 @@ Usage: export.sh export.sh gdb export.sh qemu = all | gdb | openocd | qemu | - esp8266 | esp32 | esp32c3 | esp32h2 | esp32s2 | esp32s3 + esp8266 | esp32 | esp32c3 | esp32c6 | esp32h2 | esp32s2 | esp32s3 = xtensa | riscv ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ @@ -756,6 +795,7 @@ For details, see: - \ref esp32_gpio_pins_esp32 "ESP32" - \ref esp32_gpio_pins_esp32c3 "ESP32-C3" +- \ref esp32_gpio_pins_esp32c6 "ESP32-C6" - \ref esp32_gpio_pins_esp32h2 "ESP32-H2" - \ref esp32_gpio_pins_esp32s2 "ESP32-S2" - \ref esp32_gpio_pins_esp32s3 "ESP32-S3" @@ -771,6 +811,7 @@ details, see: - \ref esp32_adc_channels_esp32 "ESP32" - \ref esp32_adc_channels_esp32c3 "ESP32-C3" +- \ref esp32_adc_channels_esp32c6 "ESP32-C6" - \ref esp32_adc_channels_esp32h2 "ESP32-H2" - \ref esp32_adc_channels_esp32s2 "ESP32-S2" - \ref esp32_adc_channels_esp32s3 "ESP32-S3" @@ -893,6 +934,7 @@ on used ESP32x SoC family, for details see: - \ref esp32_i2c_interfaces_esp32 "ESP32" - \ref esp32_i2c_interfaces_esp32c3 "ESP32-C3" +- \ref esp32_i2c_interfaces_esp32c6 "ESP32-C6" - \ref esp32_i2c_interfaces_esp32h2 "ESP32-H2" - \ref esp32_i2c_interfaces_esp32s2 "ESP32-S2" - \ref esp32_i2c_interfaces_esp32s3 "ESP32-S3" @@ -946,6 +988,7 @@ channel depends on respective ESP32x SoC family. For details, see: - \ref esp32_pwm_channels_esp32 "ESP32" - \ref esp32_pwm_channels_esp32c3 "ESP32-C3" +- \ref esp32_pwm_channels_esp32c6 "ESP32-C6" - \ref esp32_pwm_channels_esp32h2 "ESP32-H2" - \ref esp32_pwm_channels_esp32s2 "ESP32-S2" - \ref esp32_pwm_channels_esp32s3 "ESP32-S3" @@ -1125,6 +1168,7 @@ on used ESP32x SoC family, for details see: - \ref esp32_spi_interfaces_esp32 "ESP32" - \ref esp32_spi_interfaces_esp32c3 "ESP32-C3" +- \ref esp32_spi_interfaces_esp32c6 "ESP32-C6" - \ref esp32_spi_interfaces_esp32h2 "ESP32-H2" - \ref esp32_spi_interfaces_esp32s2 "ESP32-S2" - \ref esp32_spi_interfaces_esp32s3 "ESP32-S3" @@ -1170,6 +1214,7 @@ ESP32x SoC family, for details see: - \ref esp32_timers_esp32 "ESP32" - \ref esp32_timers_esp32c3 "ESP32-C3" +- \ref esp32_timers_esp32c6 "ESP32-C6" - \ref esp32_timers_esp32h2 "ESP32-H2" - \ref esp32_timers_esp32s2 "ESP32-S2" - \ref esp32_timers_esp32s3 "ESP32-S3" @@ -1233,6 +1278,7 @@ on used ESP32x SoC family, for details see: - \ref esp32_uart_interfaces_esp32 "ESP32" - \ref esp32_uart_interfaces_esp32c3 "ESP32-C3" +- \ref esp32_uart_interfaces_esp32c6 "ESP32-C6" - \ref esp32_uart_interfaces_esp32h2 "ESP32-H2" - \ref esp32_uart_interfaces_esp32s2 "ESP32-S2" - \ref esp32_uart_interfaces_esp32s3 "ESP32-S3" @@ -1828,7 +1874,7 @@ The following ESP32x SoC variants (families) integrate a Bluetooth Link Controller and a Bluetooth baseband system: - ESP32 supports Bluetooth v4.2 BR/EDR and Bluetooth LE -- ESP32-C3, ESP32-H2, ESP32-S3 support Bluetooth 5 and Bluetooth mesh +- ESP32-C3, ESP32-C6, ESP32-H2, ESP32-S3 support Bluetooth 5 and Bluetooth mesh The Bluetooth interface can be used with the Bluetooth host implementation of the NimBLE package. Use one of the `nimble_*` modules for different @@ -1839,7 +1885,7 @@ implementation. Please refer to the NimBle package documentation for details. ## IEEE 802.15.4 Network Interface {#esp32_esp_ieee802154_interface} -ESP-H2 includes an IEEE 802.15.4 subsystem +ESP32-C6 and ESP-H2 include an IEEE 802.15.4 subsystem that integrates PHY and MAC layer. The \ref drivers_ieee802154_hal "IEEE 802.15.4 Hardware Abstraction Layer" @@ -2049,6 +2095,7 @@ For details, see: - \ref esp32_jtag_interface_esp32 "ESP32" - \ref esp32_jtag_interface_esp32c3 "ESP32-C3" +- \ref esp32_jtag_interface_esp32c6 "ESP32-C6" - \ref esp32_jtag_interface_esp32h2 "ESP32-H2" - \ref esp32_jtag_interface_esp32s2 "ESP32-S2" - \ref esp32_jtag_interface_esp32s3 "ESP32-S3" @@ -2071,6 +2118,7 @@ that can be used without additional chips. For details, see: - \ref esp32_jtag_interface_esp32 "ESP32" - \ref esp32_jtag_interface_esp32c3 "ESP32-C3" +- \ref esp32_jtag_interface_esp32c6 "ESP32-C6" - \ref esp32_jtag_interface_esp32h2 "ESP32-H2" - \ref esp32_jtag_interface_esp32s2 "ESP32-S2" - \ref esp32_jtag_interface_esp32s3 "ESP32-S3" @@ -2115,6 +2163,7 @@ ESP32x SoC variant (family) can be found in ESP-IDF Programming Guide: - [ESP32](https://docs.espressif.com/projects/esp-idf/en/latest/esp32/api-guides/jtag-debugging/index.html) - [ESP32-C3](https://docs.espressif.com/projects/esp-idf/en/latest/esp32c3/api-guides/jtag-debugging/index.html) +- [ESP32-C6](https://docs.espressif.com/projects/esp-idf/en/latest/esp32c6/api-guides/jtag-debugging/index.html) - [ESP32-H2](https://docs.espressif.com/projects/esp-idf/en/latest/esp32h2/api-guides/jtag-debugging/index.html) - [ESP32-S3](https://docs.espressif.com/projects/esp-idf/en/latest/esp32s3/api-guides/jtag-debugging/index.html) - [ESP32-S2](https://docs.espressif.com/projects/esp-idf/en/latest/esp32s2/api-guides/jtag-debugging/index.html) diff --git a/cpu/esp32/doc_esp32c6.doc.md b/cpu/esp32/doc_esp32c6.doc.md new file mode 100644 index 0000000000..97f899c507 --- /dev/null +++ b/cpu/esp32/doc_esp32c6.doc.md @@ -0,0 +1,226 @@ + + +@defgroup cpu_esp32_esp32c6 ESP32-C6 family +@ingroup cpu_esp32 +@brief Specific properties of ESP32-C6 variant (family) +@author Gunar Schorcht + +\section esp32_riot_esp32c6 Specific properties of ESP32-C6 variant (family) + +## GPIO pins {#esp32_gpio_pins_esp32c6} + +ESP32-C6 has 19 broken-out GPIO pins, where a subset can be used as ADC channel +and as low-power digital inputs/outputs in deep-sleep mode, the so-called +LP GPIOs. Some of them are used by special SoC components. The following +table gives a short overview. + +
+ +Pin | Type | ADC / LP | PU / PD | Special function | Remarks +-------|:-------|:--------:|:-------:|------------------|-------- +GPIO0 | In/Out | ADC / LP | yes | XTAL_32K_P | - +GPIO1 | In/Out | ADC / LP | yes | XTAL_32K_N | - +GPIO2 | In/Out | ADC / LP | yes | | FSPIQ +GPIO3 | In/Out | ADC / LP | yes | | - +GPIO4 | In/Out | ADC / LP | yes | MTMS | FSPIWP +GPIO5 | In/Out | ADC / LP | yes | MTDI | FSPIHD +GPIO6 | In/Out | ADC / LP | yes | MTCK | FSPICLK +GPIO7 | In/Out | LP | yes | MTDO | FSPID +GPIO8 | In/Out | | yes | | Bootstrapping +GPIO9 | In/Out | | yes | | Bootstrapping, pulled up +GPIO10 | In/Out | | yes | | N/A on chips with in-package flash +GPIO11 | In/Out | | yes | | N/A on chips with in-package flash +GPIO12 | In/Out | | yes | USB D- | USB Serial / JTAG interface +GPIO13 | In/Out | | yes | USB D+ | USB Serial / JTAG interface +GPIO14 | In/Out | | yes | | N/A on chips w/o in-package flash +GPIO15 | In/Out | | yes | | Bootstrapping +GPIO16 | In/Out | | yes | UART0 TX | FSPICS0 +GPIO17 | In/Out | | yes | UART0 RX | FSPICS1 +GPIO18 | In/Out | | yes | UART0 RX | FSPICS2 +GPIO19 | In/Out | | yes | | FSPICS3 +GPIO20 | In/Out | | yes | | FSPICS4 +GPIO21 | In/Out | | yes | | FSPICS5 +GPIO22 | In/Out | | yes | | - +GPIO23 | In/Out | | yes | | - +GPIO24 | In/Out | | yes | SPICS0 | N/A on chips with in-package flash +GPIO25 | In/Out | | yes | SPIQ | N/A on chips with in-package flash +GPIO26 | In/Out | | yes | SPIWP | N/A on chips with in-package flash +GPIO27 | In/Out | | yes | VDD_SPI | N/A on chips with in-package flash +GPIO28 | In/Out | | yes | SPIHD | N/A on chips with in-package flash +GPIO29 | In/Out | | yes | SPICLK | N/A on chips with in-package flash +GPIO30 | In/Out | | yes | SPID | N/A on chips with in-package flash + +

+ +ADC: these pins can be used as ADC inputs
+LP: these pins are LP GPIOs and can be used in deep-sleep mode
+PU/PD: these pins have software configurable pull-up/pull-down functionality.
+ +GPIO8 and GPIO9 are bootstrapping pins which are used to boot +ESP32-C6 in different modes: + +
+ +GPIO9 | GPIO8 | Mode +:----:|:-----:|:------------------------------------------------------------ +1 | X | SPI Boot mode to boot the firmware from flash (default mode) +0 | 1 | SPI Download Boot mode + +Other combinations are invalid. + +

+ +## ADC Channels {#esp32_adc_channels_esp32c6} + +ESP32-C6 integrates one 12-bit ADC with 7 channels in +total: GPIO0, GPIO1, GPIO2, GPIO3, GPIO4, GPIO5 and GPIO6 + +The maximum number of ADC channels #ADC_NUMOF_MAX is 7. + +## I2C Interfaces {#esp32_i2c_interfaces_esp32c6} + +ESP32-C6 has two built-in I2C interfaces. + +The following table shows the default configuration of I2C interfaces +used for ESP32-C6 boards. It can be overridden by +[application-specific configurations](#esp32_application_specific_configurations). + +
+ +Device | Signal | Pin | Symbol | Remarks +:----------|:-------|:-------|:--------------|:---------------- +I2C_DEV(0) | | | `I2C0_SPEED` | default is `I2C_SPEED_FAST` +I2C_DEV(0) | SCL | GPIO5 | `I2C0_SCL` | - +I2C_DEV(0) | SDA | GPIO4 | `I2C0_SDA` | - + +

+ +## PWM Channels {#esp32_pwm_channels_esp32c6} + +The ESP32-C6 LEDC module has 1 channel group with 6 channels. Each of +these channels can be clocked by one of the 4 timers. This means that +it is possible to define up to 4 PWM devices with different frequencies +and resolutions and a total of 6 PWM channels. + +## SPI Interfaces {#esp32_spi_interfaces_esp32c6} + +ESP32-C6 has three SPI controllers where SPI0 and SPI1 share the same bus. +They are used as interface for external memory and can only operate in memory +mode: + +- Controller SPI0 is reserved for caching external memory like Flash +- Controller SPI1 is reserved for external memory like PSRAM +- Controller SPI2 can be used as general purpose SPI (also called FSPI) + +Thus, only SPI2 (FSPI) can be used as general purpose SPI in RIOT as +SPI_DEV(0). + +The following table shows the pin configuration used for most boards, even +though it **can vary** from board to board. + +
+ +Device | Signal | Pin | Symbol | Remarks +:-------------|:------:|:-------|:-----------:|:--------------------------- +SPI_DEV(0) | SCK | GPIO6 |`SPI0_SCK` | `SPI2_HOST` (`FSPI`) +SPI_DEV(0) | MOSI | GPIO7 |`SPI0_MOSI` | `SPI2_HOST` (`FSPI`) +SPI_DEV(0) | MISO | GPIO2 |`SPI0_MISO` | `SPI2_HOST` (`FSPI`) +SPI_DEV(0) | CS0 | GPIO18 |`SPI0_CS0` | `SPI2_HOST` (`FSPI`) + +

+ +## Timers {#esp32_timers_esp32c6} + +ESP32-C6 has two timer groups with one timer each, resulting in a total of +two timers. Thus one timer with one channel can be used in RIOT +as timer device TIMER_DEV(0), because the other timer is used as system timer. + +ESP32-C6 do not have CCOMPARE registers. The counter implementation can not +be used. + +## UART Interfaces {#esp32_uart_interfaces_esp32c6} + +ESP32-C6 integrates three UART interfaces, two in the high-power domain and +one in the low-power domain. The low-power UART interface is not yet supported. +The following default pin configuration of UART interfaces as used by a most +boards can be overridden by the application, see section +[Application-Specific Configurations](#esp32_application_specific_configurations). + +
+ +Device |Signal|Pin |Symbol |Remarks +:-----------|:-----|:-------|:-----------|:---------------- +UART_DEV(0) | TxD | GPIO16 |`UART0_TXD` | cannot be changed +UART_DEV(0) | RxD | GPIO17 |`UART0_RXD` | cannot be changed +UART_DEV(1) | TxD | |`UART1_TXD` | optional, can be configured +UART_DEV(1) | RxD | |`UART1_RXD` | optional, can be configured + +

+ +## JTAG Interface {#esp32_jtag_interface_esp32c6} + +There are two options on how to use the JTAG interface on ESP32-C6: + +1. Using the built-in USB-to-JTAG bridge connected to an USB cable as follows: +
+ USB Signal | ESP32-C6 Pin + :--------------|:----------- + D- (white) | GPIO12 + D+ (green) | GPIO13 + V_Bus (red) | 5V + Ground (black) | GND +

+ +2. Using an external JTAG adapter connected to the JTAG interface exposed + to GPIOs as follows: +
+ JTAG Signal | ESP32-C6 Pin + :-----------|:----------- + TRST_N | CHIP_PU + TDO | GPIO7 (MTDO) + TDI | GPIO5 (MTDI) + TCK | GPIO6 (MTCK) + TMS | GPIO4 (MTMS) + GND | GND +

+ +Using the built-in USB-to-JTAG bridge is the default option, i.e. the JTAG +interface of the ESP32-C6 is connected to the built-in USB-to-JTAG bridge. +To use an external JTAG adapter, the JTAG interface of the ESP32-C6 has to +be connected to the GPIOs as shown above. For this purpose eFuses have to be +burned with the following command: + +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +espefuse.py burn_efuse JTAG_SEL_ENABLE --port /dev/ttyUSB0 +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +@warning Burning eFuses is an irreversible operation. + +Once the eFuses are burned with this command and option `JTAG_SEL_ENABLE`, +GPIO15 is used as a bootstrapping pin to choose between the two options. +If GPIO15 is HIGH when ESP32-C6 is reset, the JTAG interface is connected +to the built-in USB to JTAG bridge and the USB cable can be used for on-chip +debugging. Otherwise, the JTAG interface is exposed to GPIO4 ... GPIO7 +and an external JTAG adapter has to be used. + +Alternatively, the integrated USB-to-JTAG bridge can be permanently disabled +with the following command: + +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +espefuse.py burn_efuse DIS_USB_JTAG --port /dev/ttyUSB0 +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +@warning Burning eFuses is an irreversible operation. + +Once the eFuses are burned with this command and option `DIS_USB_JTAG`, +the JTAG interface is always exposed to GPIO4 ... GPIO7 and an external +JTAG adapter has to be used. + +For more information about JTAG configuration for ESP32-C6, refer to the +section [Configure Other JTAG Interface] +(https://docs.espressif.com/projects/esp-idf/en/latest/esp32c6/api-guides/jtag-debugging/configure-other-jtag.html) +in the ESP-IDF documentation.