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cpu/stm32: merge f0f1f3 clock configuration headers

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This commit is contained in:
Alexandre Abadie 2020-12-16 14:32:30 +01:00
parent 815fc9107f
commit 45c2b19f25
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GPG Key ID: 1C919A403CAE1405
2 changed files with 44 additions and 15 deletions
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7
cpu/stm32/include/clk/clk_conf.h
View File

@ -22,10 +22,9 @@
#include "kernel_defines.h"
#include "macros/units.h"
#if defined(CPU_FAM_STM32F0)
#include "f0/cfg_clock_default.h"
#elif defined(CPU_FAM_STM32F1) || defined(CPU_FAM_STM32F3)
#include "f1f3/cfg_clock_default.h"
#if defined(CPU_FAM_STM32F0) || defined(CPU_FAM_STM32F1) || \
defined(CPU_FAM_STM32F3)
#include "f0f1f3/cfg_clock_default.h"
#elif defined(CPU_FAM_STM32F2) || defined(CPU_FAM_STM32F4) || \
defined(CPU_FAM_STM32F7)
#include "f2f4f7/cfg_clock_default.h"

52
cpu/stm32/include/clk/f1f3/cfg_clock_default.h → cpu/stm32/include/clk/f0f1f3/cfg_clock_default.h
View File

@ -13,7 +13,7 @@
* @{
*
* @file
* @brief Default clock configuration for STM32F1/F3
* @brief Default clock configuration for STM32F0/F1/F3
*
* @author Víctor Ariño <victor.arino@triagnosys.com>
* @author Sören Tempel <tempel@uni-bremen.de>
@ -23,8 +23,8 @@
*
*/
#ifndef CLK_F1F3_CFG_CLOCK_DEFAULT_H
#define CLK_F1F3_CFG_CLOCK_DEFAULT_H
#ifndef CLK_F0F1F3_CFG_CLOCK_DEFAULT_H
#define CLK_F0F1F3_CFG_CLOCK_DEFAULT_H
#ifdef __cplusplus
extern "C" {
@ -83,8 +83,12 @@ extern "C" {
#define CLOCK_HSI MHZ(8)
/* The following parameters configure a 72MHz system clock with HSE (8MHz or
16MHz) and HSI (8MHz) as input clock
/* The following parameters configure:
- on F0: a 48MHz system clock with HSI (or default HSE) as input clock
On stm32f031x6 and stm32f042x6 lines, there's no HSE and PREDIV is
hard-wired to 2, so to reach 48MHz set PLL_PREDIV to 2 and PLL_MUL to 12 so
system clock = (HSI8 / 2) * 12 = 48MHz
- on F1/F3: a 72MHz system clock with HSE (8MHz or 16MHz) and HSI (8MHz) as input clock
On stm32f303x6, stm32f303x8, stm32f303xB, stm32f303xC, stm32f328x8 and
stm32f358xC lines, PREDIV is hard-wired to 2 (see RM0316 p.126 to p.128).
To reach the maximum possible system clock (64MHz) set PLL_PREDIV to 2 and
@ -94,19 +98,28 @@ extern "C" {
#if (IS_ACTIVE(CONFIG_BOARD_HAS_HSE) && (CLOCK_HSE == MHZ(16))) || \
defined(CPU_LINE_STM32F303x6) || defined(CPU_LINE_STM32F303x8) || \
defined(CPU_LINE_STM32F303xB) || defined(CPU_LINE_STM32F303xC) || \
defined(CPU_LINE_STM32F328x8) || defined(CPU_LINE_STM32F358xC)
defined(CPU_LINE_STM32F328x8) || defined(CPU_LINE_STM32F358xC) || \
defined(CPU_LINE_STM32F031x6) || defined(CPU_LINE_STM32F042x6)
#define CONFIG_CLOCK_PLL_PREDIV (2)
#else
#define CONFIG_CLOCK_PLL_PREDIV (1)
#endif
#endif
#ifndef CONFIG_CLOCK_PLL_MUL
#ifdef CPU_FAM_STM32F0
#if defined(CPU_LINE_STM32F031x6) || defined(CPU_LINE_STM32F042x6)
#define CONFIG_CLOCK_PLL_MUL (12)
#else
#define CONFIG_CLOCK_PLL_MUL (6)
#endif
#else /* CPU_FAM_F1 || CPU_FAM_F3 */
#if defined(CPU_LINE_STM32F303x8)
#define CONFIG_CLOCK_PLL_MUL (16)
#else
#define CONFIG_CLOCK_PLL_MUL (9)
#endif
#endif
#endif /* CPU_FAM_STM32F0 */
#endif /* CONFIG_CLOCK_PLL_MUL */
#if IS_ACTIVE(CONFIG_USE_CLOCK_HSI)
#define CLOCK_CORECLOCK (CLOCK_HSI)
@ -130,29 +143,46 @@ extern "C" {
* PLL_IN: input clock is HSE if available or HSI otherwise
* PLL_PREDIV : pre-divider, allowed range: [1:16]
* PLL_MUL: multiplier, allowed range: [2:16]
* CORECLOCK -> 72MHz MAX!
* CORECLOCK -> 48MHz Max on F0, 72MHz MAX on F1/F3!
*/
#define CLOCK_CORECLOCK ((CLOCK_PLL_SRC / CONFIG_CLOCK_PLL_PREDIV) * CONFIG_CLOCK_PLL_MUL)
#ifdef CPU_FAM_STM32F0
#if CLOCK_CORECLOCK > MHZ(48)
#error "SYSCLK cannot exceed 48MHz"
#endif
#else
#if CLOCK_CORECLOCK > MHZ(72)
#error "SYSCLK cannot exceed 72MHz"
#endif
#endif
#endif /* CONFIG_USE_CLOCK_PLL */
#define CLOCK_AHB CLOCK_CORECLOCK /* HCLK, max: 72MHz */
#define CLOCK_AHB CLOCK_CORECLOCK /* HCLK, max: 48MHz (F0), 72MHz (F1/F3)*/
#ifndef CONFIG_CLOCK_APB1_DIV
#ifdef CPU_FAM_STM32F0
#define CONFIG_CLOCK_APB1_DIV (1)
#else
#define CONFIG_CLOCK_APB1_DIV (2)
#endif
#define CLOCK_APB1 (CLOCK_AHB / CONFIG_CLOCK_APB1_DIV) /* PCLK1, max: 36MHz */
#endif
#define CLOCK_APB1 (CLOCK_AHB / CONFIG_CLOCK_APB1_DIV) /* PCLK1, max: 48MHz (F0), 36MHz (F1/F3)*/
#ifdef CPU_FAM_STM32F0
/* APB2 and APB1 are the same bus but configuration registers still follows the
* split between APB1 and APB2. Since it's the same bus, APB2 clock is equal to APB1 clock.
*/
#define CLOCK_APB2 (CLOCK_APB1)
#else
#ifndef CONFIG_CLOCK_APB2_DIV
#define CONFIG_CLOCK_APB2_DIV (1)
#endif
#define CLOCK_APB2 (CLOCK_AHB / CONFIG_CLOCK_APB2_DIV) /* PCLK2, max: 72MHz */
#endif
/** @} */
#ifdef __cplusplus
}
#endif
#endif /* CLK_F1F3_CFG_CLOCK_DEFAULT_H */
#endif /* CLK_F0F1F3_CFG_CLOCK_DEFAULT_H */
/** @} */