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This commit is contained in:
Rakendra Thapa 2015-07-14 21:41:25 +05:30
parent 9c4a5f5d86
commit 4757e30e10
10 changed files with 448 additions and 448 deletions
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14
boards/ek-lm4f120xl/board.c
View File

@ -23,8 +23,8 @@ static void leds_init(void);
void board_init(void)
{
/* initialize the boards LEDs, this is done for debugging purpose */
leds_init();
/* initialize the boards LEDs, this is done for debugging purpose */
leds_init();
/* initialize the CPU */
cpu_init();
@ -35,11 +35,11 @@ void board_init(void)
*/
static void leds_init(void)
{
// enable clock for PORTF
ROM_SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOF);
// enable clock for PORTF
ROM_SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOF);
//configure the pins as general output
//configure the pins as general output
ROM_GPIOPinTypeGPIOOutput(GPIO_PORTF_BASE, GPIO_PIN_1 | GPIO_PIN_2 | GPIO_PIN_3);
// Turn Red led on
ROM_GPIOPinWrite(GPIO_PORTF_BASE, GPIO_PIN_1 | GPIO_PIN_2 | GPIO_PIN_3, 2);
// Turn Red led on
ROM_GPIOPinWrite(GPIO_PORTF_BASE, GPIO_PIN_1 | GPIO_PIN_2 | GPIO_PIN_3, 2);
}

12
boards/ek-lm4f120xl/include/board.h
View File

@ -48,8 +48,8 @@ extern "C" {
* @{
*/
#define LED_GREEN_PIN 0x08
#define LED_BLUE_PIN 0x04
#define LED_RED_PIN 0x02
#define LED_BLUE_PIN 0x04
#define LED_RED_PIN 0x02
#define LED_GREEN_ON GPIO_PORTF_DATA_R |= LED_GREEN_PIN
#define LED_GREEN_OFF GPIO_PORTF_DATA_R &= ~(LED_GREEN_PIN)
@ -63,10 +63,10 @@ extern "C" {
#define LED_RED_OFF GPIO_PORTF_DATA_R &= ~(LED_RED_PIN)
#define LED_RED_TOGGLE /* not available */
/* @} */
#define TRACE printf("TRACE %s:%d: %s\n", __FILE__, __LINE__, __FUNCTION__)
#define VAL_I(x) printf(#x ": %d\n",x);
#define VAL_X(x) printf(#x ":0x%X\n", (unsigned int)x);
#define VAL_S(x) printf(#x ":%s\n", x);
#define TRACE printf("TRACE %s:%d: %s\n", __FILE__, __LINE__, __FUNCTION__)
#define VAL_I(x) printf(#x ": %d\n",x);
#define VAL_X(x) printf(#x ":0x%X\n", (unsigned int)x);
#define VAL_S(x) printf(#x ":%s\n", x);
/**
* @brief Initialize board specific hardware, including clock, LEDs and std-IO

54
cpu/lm4f120/cpu.c
View File

@ -31,42 +31,42 @@
*/
void cpu_init(void)
{
// initializes the Cortex-M core
cortexm_init();
// initializes the Cortex-M core
cortexm_init();
/* initialize the clock system */
cpu_clock_init(CLK40);
/* initialize the clock system */
cpu_clock_init(CLK40);
}
void setup_fpu(void)
{
ROM_FPUEnable();
ROM_FPULazyStackingEnable();
ROM_FPUEnable();
ROM_FPULazyStackingEnable();
}
void cpu_clock_init(int clk)
{
setup_fpu();
switch(clk){
case CLK80:
ROM_SysCtlClockSet(SYSCTL_SYSDIV_2_5 | SYSCTL_USE_PLL | SYSCTL_XTAL_16MHZ | SYSCTL_OSC_MAIN);
break;
case CLK50:
ROM_SysCtlClockSet(SYSCTL_SYSDIV_4 | SYSCTL_USE_PLL | SYSCTL_XTAL_16MHZ | SYSCTL_OSC_MAIN);
break;
case CLK40:
ROM_SysCtlClockSet(SYSCTL_SYSDIV_5 | SYSCTL_USE_PLL | SYSCTL_XTAL_16MHZ | SYSCTL_OSC_MAIN);
break;
case CLK16:
ROM_SysCtlClockSet(SYSCTL_SYSDIV_1 | SYSCTL_USE_PLL | SYSCTL_XTAL_16MHZ | SYSCTL_OSC_MAIN);
break;
case CLK1:
ROM_SysCtlClockSet(SYSCTL_SYSDIV_1 | SYSCTL_USE_PLL | SYSCTL_XTAL_1MHZ | SYSCTL_OSC_MAIN);
break;
default:
ROM_SysCtlClockSet(SYSCTL_SYSDIV_1 | SYSCTL_USE_PLL | SYSCTL_XTAL_16MHZ | SYSCTL_OSC_MAIN);
break;
}
setup_fpu();
switch(clk){
case CLK80:
ROM_SysCtlClockSet(SYSCTL_SYSDIV_2_5 | SYSCTL_USE_PLL | SYSCTL_XTAL_16MHZ | SYSCTL_OSC_MAIN);
break;
case CLK50:
ROM_SysCtlClockSet(SYSCTL_SYSDIV_4 | SYSCTL_USE_PLL | SYSCTL_XTAL_16MHZ | SYSCTL_OSC_MAIN);
break;
case CLK40:
ROM_SysCtlClockSet(SYSCTL_SYSDIV_5 | SYSCTL_USE_PLL | SYSCTL_XTAL_16MHZ | SYSCTL_OSC_MAIN);
break;
case CLK16:
ROM_SysCtlClockSet(SYSCTL_SYSDIV_1 | SYSCTL_USE_PLL | SYSCTL_XTAL_16MHZ | SYSCTL_OSC_MAIN);
break;
case CLK1:
ROM_SysCtlClockSet(SYSCTL_SYSDIV_1 | SYSCTL_USE_PLL | SYSCTL_XTAL_1MHZ | SYSCTL_OSC_MAIN);
break;
default:
ROM_SysCtlClockSet(SYSCTL_SYSDIV_1 | SYSCTL_USE_PLL | SYSCTL_XTAL_16MHZ | SYSCTL_OSC_MAIN);
break;
}
}

14
cpu/lm4f120/include/cpu_conf.h
View File

@ -61,7 +61,7 @@ extern "C" {
* @brief Length for reading CPU_ID
*/
#define CPUID_ID_LEN (12)
#define CPUID_ADDR NVIC_CPUID
#define CPUID_ADDR NVIC_CPUID
/**
* @name CC110X buffer size definitions for the stm32f4
@ -75,12 +75,12 @@ extern "C" {
/**
* @name Define the nominal CPU core clock in this board
*/
#define F_CPU 1000000
#define CLK80 1
#define CLK50 2
#define CLK40 3
#define CLK16 4
#define CLK1 5
#define F_CPU 1000000
#define CLK80 1
#define CLK50 2
#define CLK40 3
#define CLK16 4
#define CLK1 5
extern void setup_fpu(void);

6
cpu/lm4f120/include/hwtimer_cpu.h
View File

@ -29,9 +29,9 @@ extern "C" {
*/
#define HWTIMER_MAXTIMERS 1 /**< the CPU implementation supports 4 HW timers */
#define HWTIMER_SPEED 1000000 /**< the HW timer runs with 1MHz */
#define HWTIMER_MAXTICKS 0xffffffff /**< 32-bit timer */
#define HWTIMER_MSEC (HWTIMER_SPEED/1000)
#define HWTIMER_SEC (HWTIMER_SPEED/1000000)
#define HWTIMER_MAXTICKS 0xffffffff /**< 32-bit timer */
#define HWTIMER_MSEC (HWTIMER_SPEED/1000)
#define HWTIMER_SEC (HWTIMER_SPEED/1000000)
/** @} */
#ifdef __cplusplus

96
cpu/lm4f120/include/lm4f120h5qr.h
View File

@ -62,54 +62,54 @@ typedef enum
PendSV_IRQn = -2, /*!< 14 Cortex-M4 Pend SV Interrupt */
SysTick_IRQn = -1, /*!< 15 Cortex-M4 System Tick Interrupt */
/****** LM4F specific Interrupt Numbers **********************************************************************/
GPIOPortA_IRQn = 0,
GPIOPortB_IRQn = 1,
GPIOPortC_IRQn = 2,
GPIOPortD_IRQn = 3,
GPIOPortE_IRQn = 4,
UART0_IRQn = 5,
UART1_IRQn = 6,
SSI0_IRQn = 7,
I2C0_IRQn = 8,
PWMFault_IRQn = 9,
PWM0_IRQn = 10,
PWM1_IRQn = 11,
PWM2_IRQn = 12,
Quadrature0_IRQn = 13,
ADC0_IRQn = 14,
ADC1_IRQn = 15,
ADC2_IRQn = 16,
ADC3_IRQn = 17,
WDT_IRQn = 18,
Timer0A_IRQn = 19,
Timer0B_IRQn = 20,
Timer1A_IRQn = 21,
Timer1B_IRQn = 22,
Timer2A_IRQn = 23,
Timer2B_IRQn = 24,
Comp0_IRQn = 25,
Comp1_IRQn = 26,
Comp2_IRQn = 27,
SysCtl_IRQn = 28,
FlashCtl_IRQn = 29,
GPIOPortF_IRQn = 30,
GPIOPortG_IRQn = 31,
GPIOPortH_IRQn = 32,
UART2_IRQn = 33,
SSI1_IRQn = 34,
Timer3A_IRQn = 35,
Timer3B_IRQn = 36,
I2C1_IRQn = 37,
Quadrature1_IRQn = 38,
CAN0_IRQn = 39,
CAN1_IRQn = 40,
CAN2_IRQn = 41,
Ethernet_IRQn = 42,
Hibernate_IRQn = 43,
USB0_IRQn = 44,
PWM3_IRQn = 45,
uDMA_IRQn = 46,
uDMA_Error_IRQn = 47,
GPIOPortA_IRQn = 0,
GPIOPortB_IRQn = 1,
GPIOPortC_IRQn = 2,
GPIOPortD_IRQn = 3,
GPIOPortE_IRQn = 4,
UART0_IRQn = 5,
UART1_IRQn = 6,
SSI0_IRQn = 7,
I2C0_IRQn = 8,
PWMFault_IRQn = 9,
PWM0_IRQn = 10,
PWM1_IRQn = 11,
PWM2_IRQn = 12,
Quadrature0_IRQn = 13,
ADC0_IRQn = 14,
ADC1_IRQn = 15,
ADC2_IRQn = 16,
ADC3_IRQn = 17,
WDT_IRQn = 18,
Timer0A_IRQn = 19,
Timer0B_IRQn = 20,
Timer1A_IRQn = 21,
Timer1B_IRQn = 22,
Timer2A_IRQn = 23,
Timer2B_IRQn = 24,
Comp0_IRQn = 25,
Comp1_IRQn = 26,
Comp2_IRQn = 27,
SysCtl_IRQn = 28,
FlashCtl_IRQn = 29,
GPIOPortF_IRQn = 30,
GPIOPortG_IRQn = 31,
GPIOPortH_IRQn = 32,
UART2_IRQn = 33,
SSI1_IRQn = 34,
Timer3A_IRQn = 35,
Timer3B_IRQn = 36,
I2C1_IRQn = 37,
Quadrature1_IRQn = 38,
CAN0_IRQn = 39,
CAN1_IRQn = 40,
CAN2_IRQn = 41,
Ethernet_IRQn = 42,
Hibernate_IRQn = 43,
USB0_IRQn = 44,
PWM3_IRQn = 45,
uDMA_IRQn = 46,
uDMA_Error_IRQn = 47,
} IRQn_Type;

146
cpu/lm4f120/periph/adc.c
View File

@ -34,34 +34,34 @@ adc_config_t adc_config[ADC_NUMOF];
int adc_init(adc_t dev, adc_precision_t precision)
{
adc_poweron(dev);
// ADC0 is used with AIN0 on port E3.
// ADC1 is used with AIN1 on port E2.
// GPIO port E needs to be enabled so that these pinds can be used
ROM_SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOE);
// ADC0 is used with AIN0 on port E3.
// ADC1 is used with AIN1 on port E2.
// GPIO port E needs to be enabled so that these pinds can be used
ROM_SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOE);
// Set the ADC to 125KSPS.
// This requires less power and produce longer samping time,
// creating accurate conversions
ROM_SysCtlADCSpeedSet(SYSCTL_ADCSPEED_125KSPS);
// Set the ADC to 125KSPS.
// This requires less power and produce longer samping time,
// creating accurate conversions
ROM_SysCtlADCSpeedSet(SYSCTL_ADCSPEED_125KSPS);
switch (precision) {
switch (precision) {
case ADC_RES_6BIT:
case ADC_RES_8BIT:
case ADC_RES_10BIT:
#if ADC_0_EN
ROM_ADCResolutionSet(ADC0_BASE, ADC_RES_10BIT_S);
ROM_ADCResolutionSet(ADC0_BASE, ADC_RES_10BIT_S);
#endif
#if ADC_1_EN
ROM_ADCResolutionSet(ADC1_BASE, ADC_RES_10BIT_S);
ROM_ADCResolutionSet(ADC1_BASE, ADC_RES_10BIT_S);
#endif
adc_config[dev].max_value = 0x3ff;
break;
case ADC_RES_12BIT:
#if ADC_0_EN
ROM_ADCResolutionSet(ADC0_BASE, ADC_RES_12BIT_S);
ROM_ADCResolutionSet(ADC0_BASE, ADC_RES_12BIT_S);
#endif
#if ADC_1_EN
ROM_ADCResolutionSet(ADC1_BASE, ADC_RES_12BIT_S);
ROM_ADCResolutionSet(ADC1_BASE, ADC_RES_12BIT_S);
#endif
adc_config[dev].max_value = 0xfff;
break;
@ -72,57 +72,57 @@ int adc_init(adc_t dev, adc_precision_t precision)
switch (dev) {
#if ADC_0_EN
case ADC_0:
// Select the Analog ADC Function for these pins.
// Select the Analog ADC Function for these pins.
ROM_GPIOPinTypeADC(GPIO_PORTE_BASE, GPIO_PIN_3);
// Before configuring the sequencer, we need to disable ita to prevent errorneous execution
ROM_ADCSequenceDisable(ADC0_BASE, 3);
// Before configuring the sequencer, we need to disable ita to prevent errorneous execution
ROM_ADCSequenceDisable(ADC0_BASE, 3);
// Enable Sample Sequence 3 with a Software Start (Processor signal trigger).
// The software writes an 8 (SS3) to ADC_PSSI_R to initiate a conversion on sequencer 3.
// Sequence 3 will do a single sample when the processor sends a signal to start the conversion.
ROM_ADCSequenceConfigure(ADC0_BASE, 3, ADC_TRIGGER_PROCESSOR, 0);
// Enable Sample Sequence 3 with a Software Start (Processor signal trigger).
// The software writes an 8 (SS3) to ADC_PSSI_R to initiate a conversion on sequencer 3.
// Sequence 3 will do a single sample when the processor sends a signal to start the conversion.
ROM_ADCSequenceConfigure(ADC0_BASE, 3, ADC_TRIGGER_PROCESSOR, 0);
// Configure step 0 on sequence 3.
// Sample channel 0 (ADC_CTL_CH0) in single-ended mode and configure the interrupt flag.
// (ADC_CTL_IE) to be set to enable Interrupt.
ROM_ADCSequenceStepConfigure(ADC0_BASE, 3, 0,
ADC_CTL_CH0 | ADC_CTL_IE | ADC_CTL_END);
// Configure step 0 on sequence 3.
// Sample channel 0 (ADC_CTL_CH0) in single-ended mode and configure the interrupt flag.
// (ADC_CTL_IE) to be set to enable Interrupt.
ROM_ADCSequenceStepConfigure(ADC0_BASE, 3, 0,
ADC_CTL_CH0 | ADC_CTL_IE | ADC_CTL_END);
// Clear the interrupt status flag. This is done to make sure
// the interrupt flag is cleared before we sample.
ROM_ADCIntClear(ADC0_BASE, 3);
// Clear the interrupt status flag. This is done to make sure
// the interrupt flag is cleared before we sample.
ROM_ADCIntClear(ADC0_BASE, 3);
// Since sample sequence 3 is now configured, it must be enabled.
ROM_ADCSequenceEnable(ADC0_BASE, 3);
// Since sample sequence 3 is now configured, it must be enabled.
ROM_ADCSequenceEnable(ADC0_BASE, 3);
break;
#endif
#if ADC_1_EN
case ADC_1:
// Select the Analog ADC Function for these pins.
// Select the Analog ADC Function for these pins.
ROM_GPIOPinTypeADC(GPIO_PORTE_BASE, GPIO_PIN_2);
// Before configuring the sequencer, we need to disable ita to prevent errorneous execution
ROM_ADCSequenceDisable(ADC1_BASE, 3);
// Before configuring the sequencer, we need to disable ita to prevent errorneous execution
ROM_ADCSequenceDisable(ADC1_BASE, 3);
// Enable Sample Sequence 3 with a Software Start (Processor signal trigger).
// The software writes an 8 (SS3) to ADC_PSSI_R to initiate a conversion on sequencer 3.
// Sequence 3 will do a single sample when the processor sends a signal to start the conversion.
ROM_ADCSequenceConfigure(ADC1_BASE, 3, ADC_TRIGGER_PROCESSOR, 0);
// Enable Sample Sequence 3 with a Software Start (Processor signal trigger).
// The software writes an 8 (SS3) to ADC_PSSI_R to initiate a conversion on sequencer 3.
// Sequence 3 will do a single sample when the processor sends a signal to start the conversion.
ROM_ADCSequenceConfigure(ADC1_BASE, 3, ADC_TRIGGER_PROCESSOR, 0);
// Configure step 0 on sequence 3.
// Sample channel 0 (ADC_CTL_CH1) in single-ended mode and configure the interrupt flag.
// (ADC_CTL_IE) to be set to enable Interrupt.
ROM_ADCSequenceStepConfigure(ADC1_BASE, 3, 0,
ADC_CTL_CH1 | ADC_CTL_IE | ADC_CTL_END);
// Configure step 0 on sequence 3.
// Sample channel 0 (ADC_CTL_CH1) in single-ended mode and configure the interrupt flag.
// (ADC_CTL_IE) to be set to enable Interrupt.
ROM_ADCSequenceStepConfigure(ADC1_BASE, 3, 0,
ADC_CTL_CH1 | ADC_CTL_IE | ADC_CTL_END);
// Clear the interrupt status flag. This is done to make sure
// the interrupt flag is cleared before we sample.
ROM_ADCIntClear(ADC1_BASE, 3);
// Clear the interrupt status flag. This is done to make sure
// the interrupt flag is cleared before we sample.
ROM_ADCIntClear(ADC1_BASE, 3);
// Since sample sequence 3 is now configured, it must be enabled.
ROM_ADCSequenceEnable(ADC1_BASE, 3);
// Since sample sequence 3 is now configured, it must be enabled.
ROM_ADCSequenceEnable(ADC1_BASE, 3);
break;
#endif
@ -134,41 +134,41 @@ int adc_init(adc_t dev, adc_precision_t precision)
int adc_sample(adc_t dev, int channel)
{
unsigned long ulADC_val=0;
unsigned long ulADC_val=0;
switch (dev) {
#if ADC_0_EN
case ADC_0:
// Trigger the ADC conversion
ROM_ADCProcessorTrigger(ADC0_BASE, 3);
// Trigger the ADC conversion
ROM_ADCProcessorTrigger(ADC0_BASE, 3);
// Wait for conversion to be completed.
while(!ROM_ADCIntStatus(ADC0_BASE, 3, false));
// Wait for conversion to be completed.
while(!ROM_ADCIntStatus(ADC0_BASE, 3, false));
// Read ADC value.
ROM_ADCSequenceDataGet(ADC0_BASE, 3, &ulADC_val);
// Read ADC value.
ROM_ADCSequenceDataGet(ADC0_BASE, 3, &ulADC_val);
// Clear the ADC interrupt flag
ROM_ADCIntClear(ADC0_BASE, 3);
break;
// Clear the ADC interrupt flag
ROM_ADCIntClear(ADC0_BASE, 3);
break;
#endif
#if ADC_1_EN
case ADC_1:
// Trigger the ADC conversion
ROM_ADCProcessorTrigger(ADC1_BASE, 3);
// Trigger the ADC conversion
ROM_ADCProcessorTrigger(ADC1_BASE, 3);
// Wait for conversion to be completed.
while(!ROM_ADCIntStatus(ADC1_BASE, 3, false));
// Wait for conversion to be completed.
while(!ROM_ADCIntStatus(ADC1_BASE, 3, false));
// Read ADC value.
ROM_ADCSequenceDataGet(ADC1_BASE, 3, &ulADC_val);
// Read ADC value.
ROM_ADCSequenceDataGet(ADC1_BASE, 3, &ulADC_val);
// Clear the ADC interrupt flag
ROM_ADCIntClear(ADC1_BASE, 3);
break;
// Clear the ADC interrupt flag
ROM_ADCIntClear(ADC1_BASE, 3);
break;
#endif
default:
return -1;
default:
return -1;
}
/* return result */
@ -180,13 +180,13 @@ void adc_poweron(adc_t dev)
switch (dev) {
#if ADC_0_EN
case ADC_0:
// The ADC0 Peripheral must be enabled for use
ROM_SysCtlPeripheralEnable(SYSCTL_PERIPH_ADC0);
// The ADC0 Peripheral must be enabled for use
ROM_SysCtlPeripheralEnable(SYSCTL_PERIPH_ADC0);
break;
#endif
#if ADC_1_EN
case ADC_1:
ROM_SysCtlPeripheralEnable(SYSCTL_PERIPH_ADC1);
ROM_SysCtlPeripheralEnable(SYSCTL_PERIPH_ADC1);
break;
#endif
}
@ -197,12 +197,12 @@ void adc_poweroff(adc_t dev)
switch (dev) {
#if ADC_0_EN
case ADC_0:
ROM_SysCtlPeripheralDisable(SYSCTL_PERIPH_ADC0);
ROM_SysCtlPeripheralDisable(SYSCTL_PERIPH_ADC0);
break;
#endif
#if ADC_1_EN
case ADC_1:
ROM_SysCtlPeripheralDisable(SYSCTL_PERIPH_ADC0);
ROM_SysCtlPeripheralDisable(SYSCTL_PERIPH_ADC0);
break;
#endif
}

82
cpu/lm4f120/periph/timer.c
View File

@ -43,19 +43,19 @@ static timer_conf_t config[TIMER_NUMOF];
int timer_init(tim_t dev, unsigned int us_per_tick, void (*callback)(int))
{
if (dev == TIMER_0) {
config[dev].cb = callback; // User Function
ROM_SysCtlPeripheralEnable(SYSCTL_PERIPH_WTIMER0); // Activate Timer0
WTIMER0_CTL_R &= ~0x00000001; // Disable timer0A during setup
WTIMER0_CFG_R = TIMER_CFG_16_BIT;
WTIMER0_TAMR_R = TIMER_TAMR_TAMR_PERIOD; // Configure for periodic mode
WTIMER0_TAPR_R = TIMER_0_PRESCALER; // 1us timer0A
WTIMER0_ICR_R = 0x00000001; // clear timer0A timeout flag
WTIMER0_IMR_R |= 0x00000001; // arm timeout interrupt
ROM_IntPrioritySet(INT_WTIMER0A, 32);
timer_irq_enable(dev);
timer_start(dev);
DEBUG("startTimeout Value=0x%lx\n", ROM_TimerValueGet(WTIMER0_BASE, TIMER_A));
return 1;
config[dev].cb = callback; // User Function
ROM_SysCtlPeripheralEnable(SYSCTL_PERIPH_WTIMER0); // Activate Timer0
WTIMER0_CTL_R &= ~0x00000001; // Disable timer0A during setup
WTIMER0_CFG_R = TIMER_CFG_16_BIT;
WTIMER0_TAMR_R = TIMER_TAMR_TAMR_PERIOD; // Configure for periodic mode
WTIMER0_TAPR_R = TIMER_0_PRESCALER; // 1us timer0A
WTIMER0_ICR_R = 0x00000001; // clear timer0A timeout flag
WTIMER0_IMR_R |= 0x00000001; // arm timeout interrupt
ROM_IntPrioritySet(INT_WTIMER0A, 32);
timer_irq_enable(dev);
timer_start(dev);
DEBUG("startTimeout Value=0x%lx\n", ROM_TimerValueGet(WTIMER0_BASE, TIMER_A));
return 1;
}
return -1;
}
@ -64,8 +64,8 @@ int timer_set(tim_t dev, int channel, unsigned int timeout)
{
if (dev == TIMER_0) {
unsigned int now = timer_read(dev);
DEBUG("timer_set now=0x%x\n",now);
DEBUG("timer_set timeout=0x%x\n", timeout);
DEBUG("timer_set now=0x%x\n",now);
DEBUG("timer_set timeout=0x%x\n", timeout);
return timer_set_absolute(dev, channel, now+timeout);
}
return -1;
@ -74,8 +74,8 @@ int timer_set(tim_t dev, int channel, unsigned int timeout)
int timer_set_absolute(tim_t dev, int channel, unsigned int value)
{
if (dev == TIMER_0) {
WTIMER0_TAILR_R = 0x00000000 | value; // period; Reload value
DEBUG("Setting timer absolute value=0x%x\n", value);
WTIMER0_TAILR_R = 0x00000000 | value; // period; Reload value
DEBUG("Setting timer absolute value=0x%x\n", value);
return 1;
}
return -1;
@ -84,7 +84,7 @@ int timer_set_absolute(tim_t dev, int channel, unsigned int value)
int timer_clear(tim_t dev, int channel)
{
if (dev == TIMER_0){
WTIMER0_ICR_R = TIMER_ICR_TATOCINT; // clear timer0A timeout flag
WTIMER0_ICR_R = TIMER_ICR_TATOCINT; // clear timer0A timeout flag
return 1;
}
return -1;
@ -93,11 +93,11 @@ int timer_clear(tim_t dev, int channel)
unsigned int timer_read(tim_t dev)
{
if (dev == TIMER_0) {
unsigned int currTimer0Val=0;
unsigned int loadTimer0Val=0;
currTimer0Val = (unsigned int)ROM_TimerValueGet(WTIMER0_BASE, TIMER_A);
loadTimer0Val = (unsigned int)ROM_TimerLoadGet(WTIMER0_BASE, TIMER_A);
DEBUG("WTIMER0_TAILR_R=0x%lx\t currTimer0Val=0x%x\t loadTimer0Val=0x%x\n", WTIMER0_TAILR_R, currTimer0Val, loadTimer0Val);
unsigned int currTimer0Val=0;
unsigned int loadTimer0Val=0;
currTimer0Val = (unsigned int)ROM_TimerValueGet(WTIMER0_BASE, TIMER_A);
loadTimer0Val = (unsigned int)ROM_TimerLoadGet(WTIMER0_BASE, TIMER_A);
DEBUG("WTIMER0_TAILR_R=0x%lx\t currTimer0Val=0x%x\t loadTimer0Val=0x%x\n", WTIMER0_TAILR_R, currTimer0Val, loadTimer0Val);
return (loadTimer0Val - currTimer0Val);
}
return 0;
@ -106,58 +106,58 @@ unsigned int timer_read(tim_t dev)
void timer_start(tim_t dev)
{
if (dev == TIMER_0) {
ROM_TimerEnable(WTIMER0_BASE, TIMER_A);
ROM_TimerEnable(WTIMER0_BASE, TIMER_A);
}
}
void timer_stop(tim_t dev)
{
if (dev == TIMER_0) {
ROM_TimerDisable(WTIMER0_BASE, TIMER_A);
ROM_TimerDisable(WTIMER0_BASE, TIMER_A);
}
}
void timer_irq_enable(tim_t dev)
{
if (dev == TIMER_0) {
ROM_IntEnable(INT_WTIMER0A);
ROM_TimerIntEnable(WTIMER0_BASE, TIMER_TIMA_TIMEOUT);
ROM_IntEnable(INT_WTIMER0A);
ROM_TimerIntEnable(WTIMER0_BASE, TIMER_TIMA_TIMEOUT);
}
}
void timer_irq_disable(tim_t dev)
{
if (dev == TIMER_0) {
ROM_IntDisable(INT_WTIMER0A);
ROM_IntDisable(INT_WTIMER0A);
}
}
void timer_reset(tim_t dev)
{
if (dev == TIMER_0) {
// Performs a software reset of a peripheral
ROM_SysCtlPeripheralReset(SYSCTL_PERIPH_WTIMER0);
// Performs a software reset of a peripheral
ROM_SysCtlPeripheralReset(SYSCTL_PERIPH_WTIMER0);
}
}
#if TIMER_0_EN
void isr_timer0(void)
{
TIMER0_ICR_R = TIMER_ICR_TATOCINT; // acknowledge timer0A timeout
config[TIMER_0].cb(0);
TIMER0_ICR_R = TIMER_ICR_TATOCINT; // acknowledge timer0A timeout
config[TIMER_0].cb(0);
if (sched_context_switch_request){
thread_yield();
}
if (sched_context_switch_request){
thread_yield();
}
}
void isr_wtimer0(void)
{
WTIMER0_ICR_R = TIMER_ICR_TATOCINT; // acknowledge timer0A timeout
config[TIMER_0].cb(0);
if (sched_context_switch_request){
thread_yield();
}
WTIMER0_ICR_R = TIMER_ICR_TATOCINT; // acknowledge timer0A timeout
config[TIMER_0].cb(0);
if (sched_context_switch_request){
thread_yield();
}
}
#endif

174
cpu/lm4f120/periph/uart.c
View File

@ -55,9 +55,9 @@ static uart_conf_t config[UART_NUMOF];
*/
static const unsigned long g_ulUARTPeriph[3] =
{
SYSCTL_PERIPH_UART0,
SYSCTL_PERIPH_UART1,
SYSCTL_PERIPH_UART2
SYSCTL_PERIPH_UART0,
SYSCTL_PERIPH_UART1,
SYSCTL_PERIPH_UART2
};
/**
@ -65,9 +65,9 @@ static const unsigned long g_ulUARTPeriph[3] =
*/
static const unsigned long g_ulUARTBase[3] =
{
UART0_BASE,
UART1_BASE,
UART2_BASE
UART0_BASE,
UART1_BASE,
UART2_BASE
};
// The list of possible interrupts for the console UART.
@ -76,8 +76,8 @@ static const unsigned long g_ulUARTBase[3] =
static const unsigned long g_ulUARTInt[3] =
{
INT_UART0,
INT_UART1,
INT_UART2
INT_UART1,
INT_UART2
};
/**********************************************************************************/
@ -85,109 +85,109 @@ static const unsigned long g_ulUARTInt[3] =
*/
int uart_init(uart_t uart, uint32_t baudrate, uart_rx_cb_t rx_cb, uart_tx_cb_t tx_cb, void *arg)
{
// Check the arguments
ASSERT(uart == 0);
// Check to make sure the UART peripheral is present
if(!ROM_SysCtlPeripheralPresent(SYSCTL_PERIPH_UART0)){
return -1;
}
// Check the arguments
ASSERT(uart == 0);
// Check to make sure the UART peripheral is present
if(!ROM_SysCtlPeripheralPresent(SYSCTL_PERIPH_UART0)){
return -1;
}
int res = uart_init_blocking(uart, baudrate);
if(res < 0){
return res;
}
int res = uart_init_blocking(uart, baudrate);
if(res < 0){
return res;
}
/* save callbacks */
config[uart].rx_cb = rx_cb;
config[uart].tx_cb = tx_cb;
config[uart].arg = arg;
// ulBase = g_ulUARTBase[uart];
// ulBase = g_ulUARTBase[uart];
// Configure the relevant UART pins for operations as a UART rather than GPIOs.
/* enable recieve interrupt */
switch (uart){
// Configure the relevant UART pins for operations as a UART rather than GPIOs.
/* enable recieve interrupt */
switch (uart){
#if UART_0_EN
case UART_0:
NVIC_SetPriority(UART_0_IRQ_CHAN, UART_IRQ_PRIO);
case UART_0:
NVIC_SetPriority(UART_0_IRQ_CHAN, UART_IRQ_PRIO);
ROM_UARTTxIntModeSet(UART0_BASE, UART_TXINT_MODE_EOT);
ROM_UARTFIFOLevelSet(UART0_BASE, UART_FIFO_TX4_8, UART_FIFO_RX4_8); // Set FIFO to 8 Characters
ROM_UARTFIFOEnable(UART0_BASE); // Enable FIFOs
// Enable the UART interrupt
ROM_UARTTxIntModeSet(UART0_BASE, UART_TXINT_MODE_EOT);
ROM_UARTFIFOLevelSet(UART0_BASE, UART_FIFO_TX4_8, UART_FIFO_RX4_8); // Set FIFO to 8 Characters
ROM_UARTFIFOEnable(UART0_BASE); // Enable FIFOs
// Enable the UART interrupt
NVIC_EnableIRQ(UART_0_IRQ_CHAN);
// Enable RX interrupt
UART0_IM_R = UART_IM_RXIM | UART_IM_RTIM;
break;
// Enable RX interrupt
UART0_IM_R = UART_IM_RXIM | UART_IM_RTIM;
break;
#endif
#if UART_1_EN
case UART_1:
case UART_1:
NVIC_SetPriority(UART_1_IRQ_CHAN, UART_IRQ_PRIO);
// Enable the UART interrupt
// Enable the UART interrupt
NVIC_EnableIRQ(UART_1_IRQ_CHAN);
break;
break;
#endif
}
return 0;
}
return 0;
}
int uart_init_blocking(uart_t uart, uint32_t baudrate)
{
switch(uart){
switch(uart){
#if UART_0_EN
case UART_0:
ROM_SysCtlPeripheralEnable(SYSCTL_PERIPH_UART0);
ROM_SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOA);
ROM_GPIOPinConfigure(GPIO_PA0_U0RX);
ROM_GPIOPinConfigure(GPIO_PA1_U0TX);
ROM_GPIOPinTypeUART(GPIO_PORTA_BASE, GPIO_PIN_0 | GPIO_PIN_1);
case UART_0:
ROM_SysCtlPeripheralEnable(SYSCTL_PERIPH_UART0);
ROM_SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOA);
ROM_GPIOPinConfigure(GPIO_PA0_U0RX);
ROM_GPIOPinConfigure(GPIO_PA1_U0TX);
ROM_GPIOPinTypeUART(GPIO_PORTA_BASE, GPIO_PIN_0 | GPIO_PIN_1);
ROM_UARTDisable(UART0_BASE);
ROM_UARTConfigSetExpClk(UART0_BASE,ROM_SysCtlClockGet(), baudrate,
(UART_CONFIG_PAR_NONE | UART_CONFIG_STOP_ONE |
UART_CONFIG_WLEN_8));
ROM_UARTDisable(UART0_BASE);
ROM_UARTConfigSetExpClk(UART0_BASE,ROM_SysCtlClockGet(), baudrate,
(UART_CONFIG_PAR_NONE | UART_CONFIG_STOP_ONE |
UART_CONFIG_WLEN_8));
ROM_UARTEnable(UART0_BASE);
break;
ROM_UARTEnable(UART0_BASE);
break;
#endif
}
return 0;
}
return 0;
}
void uart_tx_begin(uart_t uart)
{
uart_write(uart, '\0');
UART0_IM_R |= UART_IM_TXIM;
uart_write(uart, '\0');
UART0_IM_R |= UART_IM_TXIM;
}
int uart_write(uart_t uart, char data)
{
int ret=ROM_UARTCharPutNonBlocking(UART0_BASE, data);
int ret=ROM_UARTCharPutNonBlocking(UART0_BASE, data);
return ret;
}
int uart_read_blocking(uart_t uart, char *data)
{
*data = (char)ROM_UARTCharGet(UART0_BASE);
return 1;
*data = (char)ROM_UARTCharGet(UART0_BASE);
return 1;
}
int uart_write_blocking(uart_t uart, char data)
{
ROM_UARTCharPut(UART0_BASE, data);
ROM_UARTCharPut(UART0_BASE, data);
return 1;
}
void uart_poweron(uart_t uart)
{
ROM_UARTEnable(UART0_BASE);
ROM_UARTEnable(UART0_BASE);
}
void uart_poweroff(uart_t uart)
{
ROM_UARTDisable(UART0_BASE);
ROM_UARTDisable(UART0_BASE);
}
//*****************************************************************************
@ -198,36 +198,36 @@ void uart_poweroff(uart_t uart)
void isr_usart0(void)
{
unsigned long ulStatus;
char cChar;
long lChar;
unsigned long ulStatus;
char cChar;
long lChar;
// Get the interrupt status
ulStatus = ROM_UARTIntStatus(UART0_BASE, true);
// Clear the asserted interrupts
ROM_UARTIntClear(UART0_BASE, ulStatus);
// Get the interrupt status
ulStatus = ROM_UARTIntStatus(UART0_BASE, true);
// Clear the asserted interrupts
ROM_UARTIntClear(UART0_BASE, ulStatus);
// Are we interrupted due to TX done
if(ulStatus & UART_INT_TX)
{
if (config[UART_0].tx_cb(config[UART_0].arg) == 0){
UART0_IM_R &= ~UART_IM_TXIM;
}
}
// Are we interrupted due to TX done
if(ulStatus & UART_INT_TX)
{
if (config[UART_0].tx_cb(config[UART_0].arg) == 0){
UART0_IM_R &= ~UART_IM_TXIM;
}
}
// Are we interrupted due to a recieved character
if(ulStatus & (UART_INT_RX | UART_INT_RT))
{
// Get all the available characters from the UART
while(ROM_UARTCharsAvail(UART0_BASE))
{
// Read a character
lChar = ROM_UARTCharGetNonBlocking(UART0_BASE);
cChar = (unsigned char)(lChar & 0xFF);
config[UART_0].rx_cb(config[UART_0].arg, cChar);
}
}
if (sched_context_switch_request) {
// Are we interrupted due to a recieved character
if(ulStatus & (UART_INT_RX | UART_INT_RT))
{
// Get all the available characters from the UART
while(ROM_UARTCharsAvail(UART0_BASE))
{
// Read a character
lChar = ROM_UARTCharGetNonBlocking(UART0_BASE);
cChar = (unsigned char)(lChar & 0xFF);
config[UART_0].rx_cb(config[UART_0].arg, cChar);
}
}
if (sched_context_switch_request) {
thread_yield();
}
}

298
cpu/lm4f120/vectors.c
View File

@ -35,11 +35,11 @@ WEAK_DEFAULT void isr_svc(void);
WEAK_DEFAULT void isr_pendsv(void);
WEAK_DEFAULT void isr_systick(void);
/* LM4F120 specific interrupt vectors */
WEAK_DEFAULT void isr_usart0(void); // UART 0
WEAK_DEFAULT void isr_usart1(void); // UART 1
WEAK_DEFAULT void isr_timer0(void); // 16 bit timer 0 A
WEAK_DEFAULT void isr_timer1(void); // 16 bit timer 1 A
WEAK_DEFAULT void isr_wtimer0(void); // 32 bit timer 0 A
WEAK_DEFAULT void isr_usart0(void); // UART 0
WEAK_DEFAULT void isr_usart1(void); // UART 1
WEAK_DEFAULT void isr_timer0(void); // 16 bit timer 0 A
WEAK_DEFAULT void isr_timer1(void); // 16 bit timer 1 A
WEAK_DEFAULT void isr_wtimer0(void); // 32 bit timer 0 A
WEAK_DEFAULT void isr_wwdg(void);
WEAK_DEFAULT void isr_pvd(void);
WEAK_DEFAULT void isr_tamp_stamp(void);
@ -127,10 +127,10 @@ ISR_VECTORS const void *interrupt_vector[] = {
(void*) mem_manage_default, /* memory manage exception */
(void*) bus_fault_default, /* bus fault exception */
(void*) usage_fault_default, /* usage fault exception */
(void*) (0UL), /* Reserved */
(void*) (0UL), /* Reserved */
(void*) (0UL), /* Reserved */
(void*) (0UL), /* Reserved */
(void*) (0UL), /* Reserved */
(void*) (0UL), /* Reserved */
(void*) (0UL), /* Reserved */
(void*) (0UL), /* Reserved */
(void*) isr_svc, /* system call interrupt, in RIOT used for
* switching into thread context on boot */
(void*) debug_mon_default, /* debug monitor exception */
@ -138,144 +138,144 @@ ISR_VECTORS const void *interrupt_vector[] = {
(void*) isr_pendsv, /* pendSV interrupt, in RIOT the actual
* context switching is happening here */
(void*) isr_systick, /* SysTick interrupt, not used in RIOT */
// Peripherial interrupts start here.
(void *) dummy_handler, // GPIO Port A 16
(void *) dummy_handler, // GPIO Port B 17
(void *) dummy_handler, // GPIO Port C 18
(void *) dummy_handler, // GPIO Port D 19
(void *) dummy_handler, // GPIO Port E 20
(void *) isr_usart0, // UART 0 21
(void *) isr_usart1, // UART 1 22
(void *) dummy_handler, // SSI 0 23
(void *) dummy_handler, // I2C 0 24
(void *) (0UL), // Reserved 25
(void *) (0UL), // Reserved 26
(void *) (0UL), // Reserved 27
(void *) (0UL), // Reserved 28
(void *) (0UL), // Reserved 29
(void *) dummy_handler, // ADC 0 Seq 0 30
(void *) dummy_handler, // ADC 0 Seq 1 31
(void *) dummy_handler, // ADC 0 Seq 2 32
(void *) dummy_handler, // ADC 0 Seq 3 33
(void *) dummy_handler, // WDT 0 and 1 34
(void *) isr_timer0, // 16/32 bit timer 0 A 35
(void *) dummy_handler, // 16/32 bit timer 0 B 36
(void *) isr_timer1, // 16/32 bit timer 1 A 37
(void *) dummy_handler, // 16/32 bit timer 1 B 38
(void *) dummy_handler, // 16/32 bit timer 2 A 39
(void *) dummy_handler, // 16/32 bit timer 2 B 40
(void *) dummy_handler, // Analog comparator 0 41
(void *) dummy_handler, // Analog comparator 1 42
(void *) (0UL), // Reserved 43
(void *) dummy_handler, // System control 44
(void *) dummy_handler, // Flash + EEPROM control 45
(void *) dummy_handler, // GPIO Port F 46
(void *) (0UL), // Reserved 47
(void *) (0UL), // Reserved 48
(void *) dummy_handler, // UART 2 49
(void *) dummy_handler, // SSI 1 50
(void *) dummy_handler, // 16/32 bit timer 3 A 51
(void *) dummy_handler, // 16/32 bit timer 3 B 52
(void *) dummy_handler, // I2C 1 53
(void *) (0UL), // Reserved 54
(void *) dummy_handler, // CAN 0 55
(void *) (0UL), // Reserved 56
(void *) (0UL), // Reserved 57
(void *) (0UL), // Reserved 58
(void *) dummy_handler, // Hibernation module 59
(void *) dummy_handler, // USB 60
(void *) (0UL), // Reserved 61
(void *) dummy_handler, // UDMA SW 62
(void *) dummy_handler, // UDMA Error 63
(void *) dummy_handler, // ADC 1 Seq 0) 64
(void *) dummy_handler, // ADC 1 Seq 1 65
(void *) dummy_handler, // ADC 1 Seq 2 66
(void *) dummy_handler, // ADC 1 Seq 3 67
(void *) (0UL), // Reserved 68
(void *) (0UL), // Reserved 69
(void *) (0UL), // Reserved 70
(void *) (0UL), // Reserved 71
(void *) (0UL), // Reserved 72
(void *) dummy_handler, // SSI 2 73
(void *) dummy_handler, // SSI 2 74
(void *) dummy_handler, // UART 3 75
(void *) dummy_handler, // UART 4 76
(void *) dummy_handler, // UART 5 77
(void *) dummy_handler, // UART 6 78
(void *) dummy_handler, // UART 7 79
(void *) (0UL), // Reserved 80
(void *) (0UL), // Reserved 81
(void *) (0UL), // Reserved 82
(void *) (0UL), // Reserved 83
(void *) dummy_handler, // I2C 2 84
(void *) dummy_handler, // I2C 4 85
(void *) dummy_handler, // 16/32 bit timer 4 A 86
(void *) dummy_handler, // 16/32 bit timer 4 B 87
(void *) (0UL), // Reserved 88
(void *) (0UL), // Reserved 89
(void *) (0UL), // Reserved 90
(void *) (0UL), // Reserved 91
(void *) (0UL), // Reserved 92
(void *) (0UL), // Reserved 93
(void *) (0UL), // Reserved 94
(void *) (0UL), // Reserved 95
(void *) (0UL), // Reserved 96
(void *) (0UL), // Reserved 97
(void *) (0UL), // Reserved 98
(void *) (0UL), // Reserved 99
(void *) (0UL), // Reserved 100
(void *) (0UL), // Reserved 101
(void *) (0UL), // Reserved 102
(void *) (0UL), // Reserved 103
(void *) (0UL), // Reserved 104
(void *) (0UL), // Reserved 105
(void *) (0UL), // Reserved 106
(void *) (0UL), // Reserved 107
(void *) dummy_handler, // 16/32 bit timer 5 A 108
(void *) dummy_handler, // 16/32 bit timer 5 B 109
(void *) isr_wtimer0, // 32/64 bit timer 0 A 110
(void *) dummy_handler, // 32/64 bit timer 0 B 111
(void *) dummy_handler, // 32/64 bit timer 1 A 112
(void *) dummy_handler, // 32/64 bit timer 1 B 113
(void *) dummy_handler, // 32/64 bit timer 2 A 114
(void *) dummy_handler, // 32/64 bit timer 2 B 115
(void *) dummy_handler, // 32/64 bit timer 3 A 116
(void *) dummy_handler, // 32/64 bit timer 3 B 117
(void *) dummy_handler, // 32/64 bit timer 4 A 118
(void *) dummy_handler, // 32/64 bit timer 4 B 119
(void *) dummy_handler, // 32/64 bit timer 5 A 120
(void *) dummy_handler, // 32/64 bit timer 5 B 121
(void *) dummy_handler, // System Exception 122
(void *) (0UL), // Reserved 123
(void *) (0UL), // Reserved 124
(void *) (0UL), // Reserved 125
(void *) (0UL), // Reserved 126
(void *) (0UL), // Reserved 127
(void *) (0UL), // Reserved 128
(void *) (0UL), // Reserved 129
(void *) (0UL), // Reserved 130
(void *) (0UL), // Reserved 131
(void *) (0UL), // Reserved 132
(void *) (0UL), // Reserved 133
(void *) (0UL), // Reserved 134
(void *) (0UL), // Reserved 135
(void *) (0UL), // Reserved 136
(void *) (0UL), // Reserved 137
(void *) (0UL), // Reserved 138
(void *) (0UL), // Reserved 139
(void *) (0UL), // Reserved 140
(void *) (0UL), // Reserved 141
(void *) (0UL), // Reserved 142
(void *) (0UL), // Reserved 143
(void *) (0UL), // Reserved 144
(void *) (0UL), // Reserved 145
(void *) (0UL), // Reserved 146
(void *) (0UL), // Reserved 147
(void *) (0UL), // Reserved 148
(void *) (0UL), // Reserved 149
(void *) (0UL), // Reserved 150
(void *) (0UL), // Reserved 151
(void *) (0UL), // Reserved 152
(void *) (0UL), // Reserved 153
(void *) (0UL) // Reserved 154
// Peripherial interrupts start here.
(void *) dummy_handler, // GPIO Port A 16
(void *) dummy_handler, // GPIO Port B 17
(void *) dummy_handler, // GPIO Port C 18
(void *) dummy_handler, // GPIO Port D 19
(void *) dummy_handler, // GPIO Port E 20
(void *) isr_usart0, // UART 0 21
(void *) isr_usart1, // UART 1 22
(void *) dummy_handler, // SSI 0 23
(void *) dummy_handler, // I2C 0 24
(void *) (0UL), // Reserved 25
(void *) (0UL), // Reserved 26
(void *) (0UL), // Reserved 27
(void *) (0UL), // Reserved 28
(void *) (0UL), // Reserved 29
(void *) dummy_handler, // ADC 0 Seq 0 30
(void *) dummy_handler, // ADC 0 Seq 1 31
(void *) dummy_handler, // ADC 0 Seq 2 32
(void *) dummy_handler, // ADC 0 Seq 3 33
(void *) dummy_handler, // WDT 0 and 1 34
(void *) isr_timer0, // 16/32 bit timer 0 A 35
(void *) dummy_handler, // 16/32 bit timer 0 B 36
(void *) isr_timer1, // 16/32 bit timer 1 A 37
(void *) dummy_handler, // 16/32 bit timer 1 B 38
(void *) dummy_handler, // 16/32 bit timer 2 A 39
(void *) dummy_handler, // 16/32 bit timer 2 B 40
(void *) dummy_handler, // Analog comparator 0 41
(void *) dummy_handler, // Analog comparator 1 42
(void *) (0UL), // Reserved 43
(void *) dummy_handler, // System control 44
(void *) dummy_handler, // Flash + EEPROM control 45
(void *) dummy_handler, // GPIO Port F 46
(void *) (0UL), // Reserved 47
(void *) (0UL), // Reserved 48
(void *) dummy_handler, // UART 2 49
(void *) dummy_handler, // SSI 1 50
(void *) dummy_handler, // 16/32 bit timer 3 A 51
(void *) dummy_handler, // 16/32 bit timer 3 B 52
(void *) dummy_handler, // I2C 1 53
(void *) (0UL), // Reserved 54
(void *) dummy_handler, // CAN 0 55
(void *) (0UL), // Reserved 56
(void *) (0UL), // Reserved 57
(void *) (0UL), // Reserved 58
(void *) dummy_handler, // Hibernation module 59
(void *) dummy_handler, // USB 60
(void *) (0UL), // Reserved 61
(void *) dummy_handler, // UDMA SW 62
(void *) dummy_handler, // UDMA Error 63
(void *) dummy_handler, // ADC 1 Seq 0) 64
(void *) dummy_handler, // ADC 1 Seq 1 65
(void *) dummy_handler, // ADC 1 Seq 2 66
(void *) dummy_handler, // ADC 1 Seq 3 67
(void *) (0UL), // Reserved 68
(void *) (0UL), // Reserved 69
(void *) (0UL), // Reserved 70
(void *) (0UL), // Reserved 71
(void *) (0UL), // Reserved 72
(void *) dummy_handler, // SSI 2 73
(void *) dummy_handler, // SSI 2 74
(void *) dummy_handler, // UART 3 75
(void *) dummy_handler, // UART 4 76
(void *) dummy_handler, // UART 5 77
(void *) dummy_handler, // UART 6 78
(void *) dummy_handler, // UART 7 79
(void *) (0UL), // Reserved 80
(void *) (0UL), // Reserved 81
(void *) (0UL), // Reserved 82
(void *) (0UL), // Reserved 83
(void *) dummy_handler, // I2C 2 84
(void *) dummy_handler, // I2C 4 85
(void *) dummy_handler, // 16/32 bit timer 4 A 86
(void *) dummy_handler, // 16/32 bit timer 4 B 87
(void *) (0UL), // Reserved 88
(void *) (0UL), // Reserved 89
(void *) (0UL), // Reserved 90
(void *) (0UL), // Reserved 91
(void *) (0UL), // Reserved 92
(void *) (0UL), // Reserved 93
(void *) (0UL), // Reserved 94
(void *) (0UL), // Reserved 95
(void *) (0UL), // Reserved 96
(void *) (0UL), // Reserved 97
(void *) (0UL), // Reserved 98
(void *) (0UL), // Reserved 99
(void *) (0UL), // Reserved 100
(void *) (0UL), // Reserved 101
(void *) (0UL), // Reserved 102
(void *) (0UL), // Reserved 103
(void *) (0UL), // Reserved 104
(void *) (0UL), // Reserved 105
(void *) (0UL), // Reserved 106
(void *) (0UL), // Reserved 107
(void *) dummy_handler, // 16/32 bit timer 5 A 108
(void *) dummy_handler, // 16/32 bit timer 5 B 109
(void *) isr_wtimer0, // 32/64 bit timer 0 A 110
(void *) dummy_handler, // 32/64 bit timer 0 B 111
(void *) dummy_handler, // 32/64 bit timer 1 A 112
(void *) dummy_handler, // 32/64 bit timer 1 B 113
(void *) dummy_handler, // 32/64 bit timer 2 A 114
(void *) dummy_handler, // 32/64 bit timer 2 B 115
(void *) dummy_handler, // 32/64 bit timer 3 A 116
(void *) dummy_handler, // 32/64 bit timer 3 B 117
(void *) dummy_handler, // 32/64 bit timer 4 A 118
(void *) dummy_handler, // 32/64 bit timer 4 B 119
(void *) dummy_handler, // 32/64 bit timer 5 A 120
(void *) dummy_handler, // 32/64 bit timer 5 B 121
(void *) dummy_handler, // System Exception 122
(void *) (0UL), // Reserved 123
(void *) (0UL), // Reserved 124
(void *) (0UL), // Reserved 125
(void *) (0UL), // Reserved 126
(void *) (0UL), // Reserved 127
(void *) (0UL), // Reserved 128
(void *) (0UL), // Reserved 129
(void *) (0UL), // Reserved 130
(void *) (0UL), // Reserved 131
(void *) (0UL), // Reserved 132
(void *) (0UL), // Reserved 133
(void *) (0UL), // Reserved 134
(void *) (0UL), // Reserved 135
(void *) (0UL), // Reserved 136
(void *) (0UL), // Reserved 137
(void *) (0UL), // Reserved 138
(void *) (0UL), // Reserved 139
(void *) (0UL), // Reserved 140
(void *) (0UL), // Reserved 141
(void *) (0UL), // Reserved 142
(void *) (0UL), // Reserved 143
(void *) (0UL), // Reserved 144
(void *) (0UL), // Reserved 145
(void *) (0UL), // Reserved 146
(void *) (0UL), // Reserved 147
(void *) (0UL), // Reserved 148
(void *) (0UL), // Reserved 149
(void *) (0UL), // Reserved 150
(void *) (0UL), // Reserved 151
(void *) (0UL), // Reserved 152
(void *) (0UL), // Reserved 153
(void *) (0UL) // Reserved 154
};