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boards/seeedstudio-xiao-esp32s3: initial support
This commit is contained in:
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14
boards/seeedstudio-xiao-esp32s3/Kconfig
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14
boards/seeedstudio-xiao-esp32s3/Kconfig
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@ -0,0 +1,14 @@
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# SPDX-FileCopyrightText: 2024 Technische Universität Dresden
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# SPDX-FileCopyrightText: 2024 Isikcan 'Jon' Yilmaz
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# SPDX-License-Identifier: LGPL-2.1-only
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config BOARD
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default "seeedstudio-xiao-esp32s3" if BOARD_SEEEDSTUDIO_XIAO_ESP32S3
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config BOARD_SEEEDSTUDIO_XIAO_ESP32S3
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bool
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default y
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select BOARD_COMMON_ESP32S3
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select CPU_MODEL_ESP32S3_WROOM_1X_N8R8
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source "$(RIOTBOARD)/common/esp32s3/Kconfig"
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5
boards/seeedstudio-xiao-esp32s3/Makefile
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5
boards/seeedstudio-xiao-esp32s3/Makefile
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MODULE = board
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DIRS = $(RIOTBOARD)/common/esp32s3
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include $(RIOTBASE)/Makefile.base
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6
boards/seeedstudio-xiao-esp32s3/Makefile.dep
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6
boards/seeedstudio-xiao-esp32s3/Makefile.dep
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@ -0,0 +1,6 @@
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ifneq (,$(filter saul_default,$(USEMODULE)))
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USEMODULE += saul_gpio
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endif
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include $(RIOTBOARD)/common/esp32s3/stdio_esp32s3_default.dep.mk
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include $(RIOTBOARD)/common/esp32s3/Makefile.dep
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18
boards/seeedstudio-xiao-esp32s3/Makefile.features
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18
boards/seeedstudio-xiao-esp32s3/Makefile.features
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@ -0,0 +1,18 @@
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# the board uses a ESP32-S3R8 with an 8MB QSPI Flash and an 8MB QSPI PSRAM
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CPU_MODEL = esp32s3_wroom_1x_n8r8
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# common board and CPU features
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include $(RIOTBOARD)/common/esp32s3/Makefile.features
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# peripherals provided by the board
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FEATURES_PROVIDED += periph_adc
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FEATURES_PROVIDED += periph_i2c
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FEATURES_PROVIDED += periph_pwm
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FEATURES_PROVIDED += periph_spi
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FEATURES_PROVIDED += periph_usbdev
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# other features provided by the board
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FEATURES_PROVIDED += esp_jtag
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FEATURES_PROVIDED += highlevel_stdio
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FEATURES_PROVIDED += tinyusb_device
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FEATURES_PROVIDED += xiao_shield
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5
boards/seeedstudio-xiao-esp32s3/Makefile.include
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5
boards/seeedstudio-xiao-esp32s3/Makefile.include
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@ -0,0 +1,5 @@
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PORT_LINUX ?= /dev/ttyACM0
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OPENOCD_CONFIG ?= board/esp32s3-builtin.cfg
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include $(RIOTBOARD)/common/esp32s3/Makefile.include
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132
boards/seeedstudio-xiao-esp32s3/doc.md
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132
boards/seeedstudio-xiao-esp32s3/doc.md
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@ -0,0 +1,132 @@
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<!--
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SPDX-FileCopyrightText: 2024 Isikcan 'Jon' Yilmaz
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SPDX-License-Identifier: LGPL-2.1-only
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-->
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@defgroup boards_seeedstudio-xiao-esp32s3 Seeed Studio XIAO ESP32S3 Board
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@ingroup boards_esp32s3
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@brief Support for the Seeed Studio Xiao ESP32S3
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@author Isikcan 'Jon' Yilmaz <can158@gmail.com>
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\section esp32s3_seeedstudio Seeed Studio Xiao ESP32S3
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## Table of Contents {#esp32s3_seeedstudio_toc}
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-# [Overview](#esp32s3_seeedstudio_overview)
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-# [Hardware](#esp32s3_seeedstudio_hardware)
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-# [MCU](#esp32s3_seeedstudio_mcu)
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-# [Board Configuration](#esp32s3_seeedstudio_board_configuration)
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-# [Board Pinout](#esp32s3_seeedstudio_pinout)
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-# [Flashing the Device](#esp32s3_seeedstudio_flashing)
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-# [Using STDIO](#esp32s3_seeedstudio_stdio)
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## Overview {#esp32s3_seeedstudio_overview}
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The Seeed Studio Xiao ESP32S3 is one of the ESP32-S3 boards from Seeed Studio.
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\image html https://files.seeedstudio.com/wiki/SeeedStudio-XIAO-ESP32S3/img/xiaoesp32s3.jpg "Seeed Studio ESP32S3" width=800px
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Vendor's info page for the board [here](https://wiki.seeedstudio.com/xiao_esp32s3_getting_started/)
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The main features of the board are:
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- ESP32-S3 SoC with 2.4 GHz WiFi 802.11b/g/n and Bluetooth5, BLE
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- 8 MByte Flash
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- 8 MByte QSPI RAM
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- Native USB and USB Serial JTAG
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- 21 x 17.8 mm footprint
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[Back to table of contents](#esp32s3_seeedstudio_toc)
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## Hardware {#esp32s3_seeedstudio_hardware}
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This section describes
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- the [MCU](#esp32s3_seeedstudio_mcu),
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- the default [board configuration](#esp32s3_seeedstudio_board_configuration),
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- the [board pinout](#esp32s3_seeedstudio_pinout).
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[Back to table of contents](#esp32s3_seeedstudio_toc)
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### MCU {#esp32s3_seeedstudio_mcu}
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Most features of the board are provided by the ESP32-S3 SoC. For detailed
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information about the ESP32-S3 SoC variant (family) and ESP32x SoCs,
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see section \ref esp32_mcu_esp32 "ESP32 SoC Series".
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[Back to table of contents](#esp32s3_seeedstudio_toc)
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### Board Configuration {#esp32s3_seeedstudio_board_configuration}
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Seeed Studio Xiao ESP32S3 boards have no special hardware on board,
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besides a yellow LED connected to GPIO21.
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The default board configuration provides:
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- 9 x ADC
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- 1 x SPI
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- 1 x I2C
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- 1 x UART
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- 10 x PWM, 4 channels each
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For detailed information about the peripheral configurations of ESP32-S3
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boards, see section \ref esp32_peripherals "Common Peripherals".
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[Back to table of contents](#esp32s3_seeedstudio_toc)
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### Board Pinout {#esp32s3_seeedstudio_pinout}
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The following figure shows the pinout as configured by board definition
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(excluding the camera module).
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@image html https://files.seeedstudio.com/wiki/SeeedStudio-XIAO-ESP32S3/img/2.jpg "Seeed Studio Xiao ESP32S3 Pinout" width=900px
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The corresponding board schematic can be found
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[here](https://files.seeedstudio.com/wiki/SeeedStudio-XIAO-ESP32S3/res/XIAO_ESP32S3_SCH_v1.2.pdf)
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[Back to table of contents](#esp32s3_seeedstudio_toc)
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## Flashing the Device {#esp32s3_seeedstudio_flashing}
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Since the board does not have a USB-to-Serial chip, the easiest way to flash
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the board is using the USB Serial/JTAG interface. Just connect the board to
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your host computer and use the following command:
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~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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BOARD=seeedstudio-xiao-esp32s3 make flash ...
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~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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@note Usually the make system resets the board before flashing to enable the
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USB Serial/JTAG interface. In some special cases this reset does not work so
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that the programmer cannot connect to the board and the flashing is aborted
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with a timeout:
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```
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Serial port /dev/ttyACM0
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Connecting...
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...
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serial.serialutil.SerialTimeoutException: Write timeout
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```
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This can happen for example if the board is not yet flashed with RIOT or the
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USB interface is used for another purpose. In this case, restart the board
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manually in download mode by pressing and releasing the RESET button while
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holding down the BOOT button. In download mode, the USB Serial/JTAG interface is
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always available.
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For detailed information about ESP32-S3 as well as configuring and compiling
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RIOT for ESP32-S3 boards, see \ref esp32_riot.
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[Back to table of contents](#esp32s3_seeedstudio_toc)
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## Using STDIO {#esp32s3_seeedstudio_stdio}
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Since the board does not have a USB-to-Serial chip, the USB Serial/JTAG
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interface is used by default for the STDIO (module `stdio_usb_serial_jtag`)
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which provides an USB CDC ACM interface.
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If the USB port is used by the USBUS stack or the tinyUSB stack, implicitly
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the module `stdio_cdc_acm` or `stdio_tinyusb_cdc_acm` is used for the STDIO
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via the USB CDC ACM interface.
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Alternatively, the UART interface could be used with an external USB-to-Serial
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adapter. Simply add `stdio_uart` to the list of used modules for this purpose:
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~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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BOARD=seeedstudio-xiao-esp32s3 USEMODULE=stdio_uart make flash ...
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~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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84
boards/seeedstudio-xiao-esp32s3/include/board.h
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84
boards/seeedstudio-xiao-esp32s3/include/board.h
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/*
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* SPDX-FileCopyrightText: 2024 Isikcan 'Jon' Yilmaz
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* SPDX-License-Identifier: LGPL-2.1-only
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*/
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#pragma once
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/**
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* @ingroup boards_seeedstudio-xiao-esp32s3
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* @brief Board definitions for Seeed Studio Xiao ESP32S3 board
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* @{
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*
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* The board definitions in this file are valid for the Seeed Studio Xiao ESP32S3 board.
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*
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* Any modifications required for specific applications
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* can be overridden by \ref esp32_application_specific_configurations
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* "application-specific board configuration".
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*
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* @file
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* @author Isikcan 'Jon' Yilmaz <can158@gmail.com>
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*/
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#include <stdint.h>
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/**
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* @name Button pin definitions
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* @{
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*/
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/**
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* @brief Default button GPIO pin definition
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*
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* Seeed Studio Xiao ESP32S3 boards have a BOOT button connected to GPIO0, which can be
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* used as button during normal operation. Since the GPIO0 pin is pulled up,
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* the button signal is inverted, i.e., pressing the button will give a
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* low signal.
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*/
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#define BTN0_PIN GPIO0
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/**
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* @brief Default button GPIO mode definition
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*
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* Since the GPIO of the button is pulled up with an external resistor, the
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* mode for the GPIO pin has to be GPIO_IN.
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*/
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#define BTN0_MODE GPIO_IN
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/**
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* @brief Default interrupt flank definition for the button GPIO
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*/
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#ifndef BTN0_INT_FLANK
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# define BTN0_INT_FLANK GPIO_FALLING
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#endif
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/**
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* @brief Definition for compatibility with previous versions
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*/
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#define BUTTON0_PIN BTN0_PIN
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/** @} */
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/**
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* @name LED (on-board) configuration
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*
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* The Seeed Studio Xiao ESP32S3 board has one red LED connected to GPIO21.
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* @{
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*/
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/** @} */
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#ifndef LED0_PIN
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# define LED0_PIN GPIO21
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# define LED0_ACTIVE (0)
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#endif
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/* include common board definitions as last step */
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#include "board_common.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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#ifdef __cplusplus
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} /* end extern "C" */
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#endif
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/** @} */
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45
boards/seeedstudio-xiao-esp32s3/include/gpio_params.h
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45
boards/seeedstudio-xiao-esp32s3/include/gpio_params.h
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/*
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* SPDX-FileCopyrightText: 2024 Isikcan 'Jon' Yilmaz
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* SPDX-License-Identifier: LGPL-2.1-only
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*/
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#pragma once
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/**
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* @ingroup boards_seeedstudio-xiao-esp32s3
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* @brief Board specific configuration of direct mapped GPIOs
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* @file
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* @author Isikcan 'Jon' Yilmaz <can158@gmail.com>
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* @{
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*/
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#include "board.h"
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#include "saul/periph.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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/**
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* @brief LED and Button configuration
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*/
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static const saul_gpio_params_t saul_gpio_params[] =
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{
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{
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.name = "BOOT",
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.pin = BTN0_PIN,
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.mode = BTN0_MODE,
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.flags = SAUL_GPIO_INVERTED
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},
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{
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.name = "LED",
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.pin = LED0_PIN,
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.mode = GPIO_OUT,
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.flags = SAUL_GPIO_INIT_CLEAR
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},
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};
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#ifdef __cplusplus
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}
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#endif
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/** @} */
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153
boards/seeedstudio-xiao-esp32s3/include/periph_conf.h
Normal file
153
boards/seeedstudio-xiao-esp32s3/include/periph_conf.h
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/*
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* SPDX-FileCopyrightText: 2024 Isikcan 'Jon' Yilmaz
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* SPDX-License-Identifier: LGPL-2.1-only
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*/
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#pragma once
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/**
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* @ingroup boards_seeedstudio-xiao-esp32s3
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* @brief Peripheral configurations for Seeed Studio Xiao ESP32S3 boards
|
||||
* @{
|
||||
*
|
||||
* Any modifications required for specific applications
|
||||
* can be overridden by \ref esp32_application_specific_configurations
|
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* "application-specific board configuration".
|
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*
|
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* For detailed information about the peripheral configuration for ESP32-S3
|
||||
* boards, see section \ref esp32_peripherals "Common Peripherals".
|
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*
|
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* @file
|
||||
* @author Isikcan 'Jon' Yilmaz <can158@gmail.com>
|
||||
*/
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#include <stdint.h>
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#ifdef __cplusplus
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extern "C" {
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||||
#endif
|
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/**
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* @name ADC Channel Configuration
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* @{
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||||
*/
|
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/**
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* @brief Declaration of GPIOs that can be used as ADC channels
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*
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* All pins of ADC1 are declared as ADC channels. Keep in mind that GPIO10 is
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* not broken out and used as VBAT signal. GPIO3 is a strapping pin if
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* `EFUSE_STRAP_JTAG_SEL` is set, see \ref esp32_gpio_pins_esp32s3_strapping.
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*
|
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* @note As long as the GPIOs listed in ADC_GPIOS are not initialized as ADC
|
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* channels with the `adc_init` function, they can be used for other
|
||||
* purposes.
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||||
*/
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#ifndef ADC_GPIOS
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# define ADC_GPIOS { GPIO1, GPIO2, GPIO3, GPIO4, GPIO5, GPIO6, GPIO7, GPIO8, GPIO9 }
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#endif
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/** @} */
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/**
|
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* @name I2C configuration
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||||
*
|
||||
* For the Seeedstudio Xiao ESP32S3 board, only one I2C interface I2C_DEV(0)
|
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* is defined.
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*
|
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* The GPIOs listed in the configuration are only initialized as I2C signals
|
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* when module `periph_i2c` is used. Otherwise they are not allocated and
|
||||
* can be used for other purposes.
|
||||
*
|
||||
* @{
|
||||
*/
|
||||
#ifndef I2C0_SPEED
|
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# define I2C0_SPEED I2C_SPEED_FAST /**< I2C bus speed of I2C_DEV(0) */
|
||||
#endif
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||||
#ifndef I2C0_SCL
|
||||
# define I2C0_SCL GPIO6 /**< SCL signal of I2C_DEV(0) */
|
||||
#endif
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||||
#ifndef I2C0_SDA
|
||||
# define I2C0_SDA GPIO5 /**< SDA signal of I2C_DEV(0) */
|
||||
#endif
|
||||
/** @} */
|
||||
|
||||
/**
|
||||
* @name PWM channel configuration
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*
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||||
* Two PWM devices are configured. These devices can use all GPIOs that are not
|
||||
* defined as I2C, SPI or UART for this board. Generally, all outputs pins
|
||||
* could be used as PWM channels.
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||||
*
|
||||
* @note As long as the according PWM device is not initialized with
|
||||
* the `pwm_init`, the GPIOs declared for this device can be used
|
||||
* for other purposes.
|
||||
*
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Declaration of the channels for device PWM_DEV(0),
|
||||
* at maximum PWM_CHANNEL_NUM_DEV_MAX.
|
||||
*/
|
||||
#ifndef PWM0_GPIOS
|
||||
# define PWM0_GPIOS { GPIO0, GPIO1, GPIO2 }
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Declaration of the channels for device PWM_DEV(1),
|
||||
* at maximum PWM_CHANNEL_NUM_DEV_MAX.
|
||||
*/
|
||||
#ifndef PWM1_GPIOS
|
||||
# define PWM1_GPIOS { GPIO21 }
|
||||
#endif
|
||||
/** @} */
|
||||
|
||||
/**
|
||||
* @name SPI configuration
|
||||
*
|
||||
* @note The GPIOs listed in the configuration are first initialized as SPI
|
||||
* signals when the corresponding SPI interface is used for the first time
|
||||
* by either calling the `spi_init_cs` function or the `spi_acquire`
|
||||
* function. That is, they are not allocated as SPI signals before and can
|
||||
* be used for other purposes as long as the SPI interface is not used.
|
||||
* @{
|
||||
*/
|
||||
#ifndef SPI0_CTRL
|
||||
# define SPI0_CTRL FSPI /**< FSPI is used as SPI_DEV(0) */
|
||||
#endif
|
||||
#ifndef SPI0_SCK
|
||||
# define SPI0_SCK GPIO7 /**< FSPI SCK (pin FSPICLK) */
|
||||
#endif
|
||||
#ifndef SPI0_MISO
|
||||
# define SPI0_MISO GPIO8 /**< FSPI MISO (pin FSPIQ) */
|
||||
#endif
|
||||
#ifndef SPI0_MOSI
|
||||
# define SPI0_MOSI GPIO9 /**< FSPI MOSI (pin FSPID) */
|
||||
#endif
|
||||
#ifndef SPI0_CS0
|
||||
# define SPI0_CS0 GPIO3 /**< FSPI CS0 (pin FSPICS0) */
|
||||
#endif
|
||||
/** @} */
|
||||
|
||||
/**
|
||||
* @name UART configuration
|
||||
*
|
||||
* ESP32-S3 provides 3 UART interfaces at maximum:
|
||||
*
|
||||
* UART_DEV(0) uses fixed standard configuration.<br>
|
||||
* UART_DEV(1) is not used.<br>
|
||||
* UART_DEV(2) is not used.
|
||||
*
|
||||
* @{
|
||||
*/
|
||||
#define UART0_TXD GPIO43 /**< direct I/O pin for UART_DEV(0) TxD, can't be changed */
|
||||
#define UART0_RXD GPIO44 /**< direct I/O pin for UART_DEV(0) RxD, can't be changed */
|
||||
/** @} */
|
||||
|
||||
#ifdef __cplusplus
|
||||
} /* end extern "C" */
|
||||
#endif
|
||||
|
||||
/* include common peripheral definitions as last step */
|
||||
#include "periph_conf_common.h"
|
||||
|
||||
/** @} */
|
||||
Loading…
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Reference in New Issue
Block a user