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teensy31: Fix off-by-1 error in clock dividers

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The comment says the config should yield 24 MHz flash clock, but the
settings were configured to divide-by-3. (48 MHz / 3)
This commit is contained in:
Joakim Nohlgård 2018-04-11 19:55:51 +02:00
parent 8841486f2e
commit 4ba9d2b280
1 changed files with 1 additions and 1 deletions
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2
boards/teensy31/include/periph_conf.h
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@ -44,7 +44,7 @@ static const clock_config_t clock_config = {
* should have better accuracy than the internal slow clock, and lower power
* consumption than using the 16 MHz crystal and the OSC0 module */
.clkdiv1 = SIM_CLKDIV1_OUTDIV1(0) | SIM_CLKDIV1_OUTDIV2(0) |
SIM_CLKDIV1_OUTDIV3(2) | SIM_CLKDIV1_OUTDIV4(2),
SIM_CLKDIV1_OUTDIV3(1) | SIM_CLKDIV1_OUTDIV4(1),
.default_mode = KINETIS_MCG_MODE_FEE,
.erc_range = KINETIS_MCG_ERC_RANGE_LOW, /* Input clock is 32768 Hz */
.fcrdiv = 0, /* Fast IRC divide by 1 => 4 MHz */