From 50fda7e07fd53fd45dfe71dc09ac1634bb045241 Mon Sep 17 00:00:00 2001 From: DipSwitch Date: Tue, 5 Apr 2016 23:22:50 +0200 Subject: [PATCH] [SQUASH] Fix timer clock calculations --- boards/nucleo-f103/dist/openocd.cfg | 2 +- boards/nucleo-f103/include/periph_conf.h | 10 ++++++---- cpu/stm32f1/cpu.c | 2 +- cpu/stm32f1/periph/timer.c | 2 +- 4 files changed, 9 insertions(+), 7 deletions(-) diff --git a/boards/nucleo-f103/dist/openocd.cfg b/boards/nucleo-f103/dist/openocd.cfg index e6d5040e50..4017f6f358 100755 --- a/boards/nucleo-f103/dist/openocd.cfg +++ b/boards/nucleo-f103/dist/openocd.cfg @@ -1 +1 @@ -source [find board/st_nucleo_f1.cfg] +source [find board/st_nucleo_f103rb.cfg] diff --git a/boards/nucleo-f103/include/periph_conf.h b/boards/nucleo-f103/include/periph_conf.h index 2d810dd840..71334499c4 100644 --- a/boards/nucleo-f103/include/periph_conf.h +++ b/boards/nucleo-f103/include/periph_conf.h @@ -29,12 +29,12 @@ extern "C" { * @name Clock system configuration * @{ */ -#define CLOCK_HSE (8000000U) /* external oscillator */ -#define CLOCK_CORECLOCK (72000000U) /* desired core clock frequency */ +#define CLOCK_HSI (8000000U) /* external oscillator */ +#define CLOCK_CORECLOCK (64000000U) /* desired core clock frequency */ /* the actual PLL values are automatically generated */ -#define CLOCK_PLL_DIV RCC_CFGR_PLLXTPRE_HSE /* not divided */ -#define CLOCK_PLL_MUL RCC_CFGR_PLLMULL9 +#define CLOCK_PLL_DIV (0) +#define CLOCK_PLL_MUL (16) /* AHB, APB1, APB2 dividers */ #define CLOCK_AHB_DIV RCC_CFGR_HPRE_DIV1 @@ -44,6 +44,8 @@ extern "C" { /* resulting bus clocks */ #define CLOCK_APB1 (CLOCK_CORECLOCK / 2) #define CLOCK_APB2 (CLOCK_CORECLOCK) +#define CLOCK_APB1_TIMERS ((CLOCK_APB1_DIV > 0) ? (CLOCK_APB1 << 1) : (CLOCK_APB1)) +#define CLOCK_APB2_TIMERS ((CLOCK_APB2_DIV > 0) ? (CLOCK_APB2 << 1) : (CLOCK_APB2)) /* Flash latency */ #define CLOCK_FLASH_LATENCY FLASH_ACR_LATENCY_2 /* for >= 72 MHz */ diff --git a/cpu/stm32f1/cpu.c b/cpu/stm32f1/cpu.c index ae9d3f9d6e..aac6fd5bf5 100644 --- a/cpu/stm32f1/cpu.c +++ b/cpu/stm32f1/cpu.c @@ -91,7 +91,7 @@ static void clk_init(void) RCC->CFGR |= (uint32_t)CLOCK_APB1_DIV; /* PLL configuration: PLLCLK = CLOCK_SOURCE / PLL_DIV * PLL_MUL */ RCC->CFGR &= ~((uint32_t)(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL)); - RCC->CFGR |= (uint32_t)(CLOCK_PLL_SOURCE | CLOCK_PLL_DIV | CLOCK_PLL_MUL); + RCC->CFGR |= (uint32_t)(CLOCK_PLL_SOURCE | CLOCK_PLL_DIV | ((CLOCK_PLL_MUL - 2) << 18)); /* Enable PLL */ RCC->CR |= RCC_CR_PLLON; /* Wait till PLL is ready */ diff --git a/cpu/stm32f1/periph/timer.c b/cpu/stm32f1/periph/timer.c index e57d9b53cb..2efb34f2e3 100644 --- a/cpu/stm32f1/periph/timer.c +++ b/cpu/stm32f1/periph/timer.c @@ -56,7 +56,7 @@ int timer_init(tim_t tim, unsigned long freq, timer_cb_t cb, void *arg) dev(tim)->CR2 = 0; dev(tim)->ARR = TIMER_MAXVAL; /* set prescaler */ - dev(tim)->PSC = ((CLOCK_CORECLOCK / freq) - 1); + dev(tim)->PSC = ((((timer_config[tim].bus == APB1) ? CLOCK_APB1_TIMERS : CLOCK_APB2_TIMERS) / freq) - 1); /* generate an update event to apply our configuration */ dev(tim)->EGR = TIM_EGR_UG;