From 53235dd2e2b84a45b5ed4aea7635e3420d59aee8 Mon Sep 17 00:00:00 2001 From: Gerson Fernando Budke Date: Sun, 28 Mar 2021 11:40:36 -0300 Subject: [PATCH] cpu/atxmega/atxmega_cpu: Fix clk sel after dfll en The current ATxmega clock_init enable DFLL to improve the accuracy of the 2MHz and 32MHz internal oscillators. In some ATxmega revisions, after started DFLL the clock become unstable. Add another sync point for 32MHz internal oscilator. Note: If clock is not stable, system won't switch from 2MHz to 32MHz as main clock. Signed-off-by: Gerson Fernando Budke --- cpu/atxmega/atxmega_cpu.c | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-) diff --git a/cpu/atxmega/atxmega_cpu.c b/cpu/atxmega/atxmega_cpu.c index 433b0f7f18..e144ef2af1 100644 --- a/cpu/atxmega/atxmega_cpu.c +++ b/cpu/atxmega/atxmega_cpu.c @@ -98,10 +98,15 @@ void __attribute__((weak)) avr8_clk_init(void) != (OSC_RC32KRDY_bm | OSC_RC32MRDY_bm)) {} /* Enable DFLL - defaults to calibrate against internal 32Khz clock */ - DFLLRC32M.CTRL = DFLL_ENABLE_bm; + DFLLRC2M.CTRL = DFLL_ENABLE_bm; /* Enable DFLL - defaults to calibrate against internal 32Khz clock */ - DFLLRC2M.CTRL = DFLL_ENABLE_bm; + DFLLRC32M.CTRL = DFLL_ENABLE_bm; + + /* Some ATxmega need sync clocks after enable DFLL. Otherwise clock may + * stay at 2MHz source when try enable. + */ + while ((OSC.STATUS & OSC_RC32MRDY_bm) != OSC_RC32MRDY_bm) {} atxmega_set_prescaler(CPU_ATXMEGA_CLK_SCALE_INIT, CPU_ATXMEGA_BUS_SCALE_INIT);