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Merge pull request #13857 from benpicco/cpu/lpc2387/gpio-fix_port2

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cpu/lpc2387: gpio: Fix interrupts on PORT2
This commit is contained in:
Marian Buschsieweke 2020-04-13 13:55:26 +02:00 committed by GitHub
commit 54822ab5be
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GPG Key ID: 4AEE18F83AFDEB23
2 changed files with 29 additions and 30 deletions
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1
boards/mcb2388/include/board.h
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@ -93,6 +93,7 @@ extern "C" {
*/
#define BTN0_PIN GPIO_PIN(2, 10)
#define BTN0_MODE GPIO_IN
#define BTN0_INT_FLANK GPIO_FALLING
/** @} */
/**

58
cpu/lpc2387/periph/gpio.c
View File

@ -43,6 +43,11 @@ static uint8_t _gpio_isr_map[64]; /* only ports 0+2 can have ISRs */
static void _gpio_configure(gpio_t pin, unsigned rising, unsigned falling);
static inline int _isr_map_entry2(unsigned port, unsigned pin)
{
return pin + (port ? 32 : 0);
}
static int _isr_map_entry(gpio_t pin) {
unsigned _pin = pin & 31;
unsigned port = pin >> 5;
@ -52,11 +57,7 @@ static int _isr_map_entry(gpio_t pin) {
return -1;
}
if (port) {
_pin += 32;
}
return _pin;
return _isr_map_entry2(port, _pin);
}
#endif /* MODULE_PERIPH_GPIO_IRQ */
@ -267,22 +268,25 @@ void gpio_irq_disable(gpio_t dev)
_gpio_configure(dev, 0, 0);
}
static void test_irq(int port, unsigned long f_mask, unsigned long r_mask)
static void test_irq(int port, unsigned long active_pins)
{
/* Test each bit of rising and falling masks, if set trigger interrupt
* on corresponding device */
unsigned bit = 0x1;
int n = 0;
while (bit) {
if ((r_mask & bit) | (f_mask & bit)) {
int _state_index = _gpio_isr_map[n + (port<<1)];
if (_state_index != 0xff) {
_gpio_states[_state_index].cb(_gpio_states[_state_index].arg);
}
while (active_pins) {
/* we want the position of the first one bit, so N_bits - (N_leading_zeros + 1) */
unsigned pin = 32 - __builtin_clz(active_pins) - 1;
/* get the index of the configured interrupt */
int _state_index = _gpio_isr_map[_isr_map_entry2(port, pin)];
/* check if interrupt is configured */
if (_state_index != 0xff) {
_gpio_states[_state_index].cb(_gpio_states[_state_index].arg);
}
bit <<= 1;
n++;
/* clear bit */
active_pins &= ~(1 << pin);
}
}
@ -290,24 +294,18 @@ void GPIO_IRQHandler(void) __attribute__((interrupt("IRQ")));
void GPIO_IRQHandler(void)
{
unsigned long int_stat;
if (IO_INT_STAT & BIT0) { /* interrupt(s) on PORT0 pending */
unsigned long int_stat_f = IO0_INT_STAT_F; /* save content */
unsigned long int_stat_r = IO0_INT_STAT_R; /* save content */
IO0_INT_CLR = int_stat_f; /* clear flags of fallen pins */
IO0_INT_CLR = int_stat_r; /* clear flags of risen pins */
test_irq(0, int_stat_f, int_stat_r);
int_stat = IO0_INT_STAT_F | IO0_INT_STAT_R; /* get risen & fallen pin IRQs */
IO0_INT_CLR = int_stat; /* clear IRQ flags */
test_irq(0, int_stat);
}
if (IO_INT_STAT & BIT2) { /* interrupt(s) on PORT2 pending */
unsigned long int_stat_f = IO2_INT_STAT_F; /* save content */
unsigned long int_stat_r = IO2_INT_STAT_R; /* save content */
IO2_INT_CLR = int_stat_f; /* clear flags of fallen pins */
IO2_INT_CLR = int_stat_r; /* clear flags of risen pins */
test_irq(2, int_stat_f, int_stat_r);
int_stat = IO2_INT_STAT_F | IO2_INT_STAT_R; /* get risen & fallen pin IRQs */
IO2_INT_CLR = int_stat; /* clear IRQ flags */
test_irq(2, int_stat);
}
VICVectAddr = 0; /* Acknowledge Interrupt */