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Merge pull request #5254 from haukepetersen/opt_atmega_timer
cpu/atmega2560: reworked timer implementation
This commit is contained in:
Hauke Petersen
commit
553d18ac9e
@ -51,6 +51,7 @@ extern "C" {
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* @brief xtimer configuration values
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* @{
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*/
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#define XTIMER_MASK (0xffff0000)
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#define XTIMER_SHIFT (2)
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#define XTIMER_SHIFT_ON_COMPARE (8)
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#define XTIMER_BACKOFF (40)
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@ -31,109 +31,28 @@ extern "C" {
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/** @} */
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/**
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* @brief Timer peripheral configuration
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* @brief Timer configuration
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*
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* The ATmega2560 has 6 timers. Timer0 and Timer2 are 8 Bit Timers,
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* Timer0 has special uses too and therefore we'll avoid using it.
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* Timer5 has special uses with certain Arduino Shields, too.
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* Therefore we'll also avoid using Timer5.
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* This results in the following mapping to use the left over 16 Bit
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* timers:
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*
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* Timer1 -> TIMER_0
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* Timer3 -> TIMER_1
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* Timer4 -> TIMER_2
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* The timer driver only supports the four 16-bit timers (Timer1, Timer3,
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* Timer4, Timer5), so those are the only onces we can use here.
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*
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* @{
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*/
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#define TIMER_NUMOF (3U)
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#define TIMER_0_EN 1
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#define TIMER_1_EN 0
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#define TIMER_2_EN 0
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#define TIMER_NUMOF (2U)
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/* Timer 0 configuration */
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#define TIMER_0_CHANNELS 3
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#define TIMER_0_MAX_VALUE (0xffff)
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#define TIMER_0 MEGA_TIMER1
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#define TIMER_0_MASK &TIMSK1
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#define TIMER_0_FLAG &TIFR1
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#define TIMER_0_ISRA TIMER1_COMPA_vect
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#define TIMER_0_ISRB TIMER1_COMPB_vect
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#define TIMER_0_ISRC TIMER1_COMPC_vect
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/* Timer 0 register and flags */
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#define TIMER0_CONTROL_A TCCR1A
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#define TIMER0_CONTROL_B TCCR1B
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#define TIMER0_CONTROL_C TCCR1C
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#define TIMER0_COUNTER TCNT1
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#define TIMER0_IRQ_FLAG_REG TIFR1
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#define TIMER0_IRQ_MASK_REG TIMSK1
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#define TIMER0_COMP_A OCR1A
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#define TIMER0_COMP_B OCR1B
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#define TIMER0_COMP_C OCR1C
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#define TIMER0_COMP_A_FLAG OCF1A
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#define TIMER0_COMP_B_FLAG OCF1B
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#define TIMER0_COMP_C_FLAG OCF1C
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#define TIMER0_COMP_A_EN OCIE1A
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#define TIMER0_COMP_B_EN OCIE1B
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#define TIMER0_COMP_C_EN OCIE1C
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#define TIMER0_FREQ_16MHZ (0 << CS12) | (0 << CS11) | (1 << CS10)
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#define TIMER0_FREQ_2MHZ (0 << CS12) | (1 << CS11) | (0 << CS10)
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#define TIMER0_FREQ_250KHZ (0 << CS12) | (1 << CS11) | (1 << CS10)
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#define TIMER0_FREQ_DISABLE (0 << CS12) | (0 << CS11) | (0 << CS10)
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#define TIMER0_COMPA_ISR TIMER1_COMPA_vect
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#define TIMER0_COMPB_ISR TIMER1_COMPB_vect
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#define TIMER0_COMPC_ISR TIMER1_COMPC_vect
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/* Timer 1 configuration */
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#define TIMER_1_CHANNELS 3
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#define TIMER_1_MAX_VALUE (0xffff)
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/* Timer 1 register and flags */
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#define TIMER1_CONTROL_A TCCR3A
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#define TIMER1_CONTROL_B TCCR3B
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#define TIMER1_CONTROL_C TCCR3C
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#define TIMER1_COUNTER TCNT3
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#define TIMER1_IRQ_FLAG_REG TIFR3
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#define TIMER1_IRQ_MASK_REG TIMSK3
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#define TIMER1_COMP_A OCR3A
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#define TIMER1_COMP_B OCR3B
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#define TIMER1_COMP_C OCR3C
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#define TIMER1_COMP_A_FLAG OCF3A
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#define TIMER1_COMP_B_FLAG OCF3B
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#define TIMER1_COMP_C_FLAG OCF3C
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#define TIMER1_COMP_A_EN OCIE3A
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#define TIMER1_COMP_B_EN OCIE3B
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#define TIMER1_COMP_C_EN OCIE3C
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#define TIMER1_FREQ_16MHZ (0 << CS32) | (0 << CS31) | (1 << CS30)
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#define TIMER1_FREQ_2MHZ (0 << CS32) | (1 << CS31) | (0 << CS30)
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#define TIMER1_FREQ_250KHZ (0 << CS32) | (1 << CS31) | (1 << CS30)
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#define TIMER1_FREQ_DISABLE (0 << CS32) | (0 << CS31) | (0 << CS30)
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#define TIMER1_COMPA_ISR TIMER3_COMPA_vect
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#define TIMER1_COMPB_ISR TIMER3_COMPB_vect
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#define TIMER1_COMPC_ISR TIMER3_COMPC_vect
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/* Timer 2 configuration */
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#define TIMER_2_CHANNELS 3
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#define TIMER_2_MAX_VALUE (0xffff)
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/* Timer 2 register and flags */
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#define TIMER2_CONTROL_A TCCR4A
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#define TIMER2_CONTROL_B TCCR4B
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#define TIMER2_CONTROL_C TCCR4C
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#define TIMER2_COUNTER TCNT4
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#define TIMER2_IRQ_FLAG_REG TIFR4
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#define TIMER2_IRQ_MASK_REG TIMSK4
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#define TIMER2_COMP_A OCR4A
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#define TIMER2_COMP_B OCR4B
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#define TIMER2_COMP_C OCR4C
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#define TIMER2_COMP_A_FLAG OCF4A
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#define TIMER2_COMP_B_FLAG OCF4B
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#define TIMER2_COMP_C_FLAG OCF4C
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#define TIMER2_COMP_A_EN OCIE4A
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#define TIMER2_COMP_B_EN OCIE4B
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#define TIMER2_COMP_C_EN OCIE4C
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#define TIMER2_FREQ_16MHZ (0 << CS42) | (0 << CS41) | (1 << CS40)
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#define TIMER2_FREQ_2MHZ (0 << CS42) | (1 << CS41) | (0 << CS40)
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#define TIMER2_FREQ_250KHZ (0 << CS42) | (1 << CS41) | (1 << CS40)
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#define TIMER2_FREQ_DISABLE (0 << CS42) | (0 << CS41) | (0 << CS40)
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#define TIMER2_COMPA_ISR TIMER4_COMPA_vect
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#define TIMER2_COMPB_ISR TIMER4_COMPB_vect
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#define TIMER2_COMPC_ISR TIMER4_COMPC_vect
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#define TIMER_1 MEGA_TIMER4
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#define TIMER_1_MASK &TIMSK4
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#define TIMER_1_FLAG &TIFR4
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#define TIMER_1_ISRA TIMER4_COMPA_vect
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#define TIMER_1_ISRB TIMER4_COMPB_vect
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#define TIMER_1_ISRC TIMER4_COMPC_vect
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/** @} */
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/**
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74
cpu/atmega2560/include/atmega2560_regs.h
Normal file
74
cpu/atmega2560/include/atmega2560_regs.h
Normal file
@ -0,0 +1,74 @@
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/*
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* Copyright (C) 2016 Freie Universität Berlin
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*
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* This file is subject to the terms and conditions of the GNU Lesser
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* General Public License v2.1. See the file LICENSE in the top level
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* directory for more details.
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*/
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/**
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* @ingroup cpu_atmega2560
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* @{
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*
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* @file
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* @brief CMSIS style register definitions for the atmega2560
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*
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* @author Hauke Petersen <hauke.petersen@fu-berlin.de>
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*/
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#ifndef ATMEGA2560_REGS_H
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#define ATMEGA2560_REGS_H
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#include <avr/io.h>
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#ifdef __cplusplus
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extern "C" {
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#endif
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/**
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* @brief Register types
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* @{
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*/
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#define REG8 volatile uint8_t
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#define REG16 volatile uint16_t
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/** @} */
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/**
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* @brief Timer register map
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*/
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typedef struct {
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REG8 CRA; /**< control A */
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REG8 CRB; /**< control B */
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REG8 CRC; /**< control C */
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REG8 reserved; /**< reserved */
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REG16 CNT; /**< counter */
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REG16 ICR; /**< input capture */
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REG16 OCR[3]; /**< output compare */
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} mega_timer_t;
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/**
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* @brief Base register address definitions
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* @{
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*/
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#define MEGA_TIMER1_BASE (uint16_t *)(&TCCR1A)
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#define MEGA_TIMER3_BASE (uint16_t *)(&TCCR3A)
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#define MEGA_TIMER4_BASE (uint16_t *)(&TCCR4A)
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#define MEGA_TIMER5_BASE (uint16_t *)(&TCCR5A)
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/** @} */
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/**
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* @brief Peripheral instances
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* @{
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*/
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#define MEGA_TIMER1 ((mega_timer_t *)MEGA_TIMER1_BASE)
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#define MEGA_TIMER3 ((mega_timer_t *)MEGA_TIMER3_BASE)
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#define MEGA_TIMER4 ((mega_timer_t *)MEGA_TIMER4_BASE)
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#define MEGA_TIMER5 ((mega_timer_t *)MEGA_TIMER5_BASE)
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/** @} */
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#ifdef __cplusplus
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}
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#endif
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#endif /* ATMEGA2560_REGS_H */
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/** @} */
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@ -7,6 +7,7 @@
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*/
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/**
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* @ingroup cpu_atmega2560
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* @{
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*
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* @file
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@ -19,6 +20,7 @@
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#ifndef __CPU_CONF_H
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#define __CPU_CONF_H
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#include "atmega2560_regs.h"
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#ifdef __cplusplus
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extern "C" {
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@ -19,9 +19,6 @@
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* @}
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*/
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#include <stdlib.h>
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#include <stdio.h>
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#include <avr/interrupt.h>
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#include "board.h"
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@ -31,449 +28,231 @@
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#include "periph/timer.h"
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#include "periph_conf.h"
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#define IRQ_DISABLED 0x00
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/**
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* @brief All timers have three channels
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*/
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#define CHANNELS (3)
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/**
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* @brief Timer state memory
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* @brief We have 5 possible prescaler values
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*/
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static timer_isr_ctx_t config[TIMER_NUMOF];
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#define PRESCALE_NUMOF (5U)
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/**
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* @brief Possible prescaler values, encoded as 2 ^ val
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*/
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static const uint8_t prescalers[] = { 0, 3, 6, 8, 10 };
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/**
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* @brief Timer state context
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*/
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typedef struct {
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mega_timer_t *dev; /**< timer device */
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volatile uint8_t *mask; /**< address of interrupt mask register */
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volatile uint8_t *flag; /**< address of interrupt flag register */
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timer_cb_t cb; /**< interrupt callback */
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void *arg; /**< interrupt callback argument */
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uint8_t mode; /**< remember the configured mode */
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uint8_t isrs; /**< remember the interrupt state */
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} ctx_t;
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/**
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* @brief Allocate memory for saving the device states
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* @{
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*/
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#if TIMER_NUMOF
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static ctx_t ctx[] = {
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#ifdef TIMER_0
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{ TIMER_0, TIMER_0_MASK, TIMER_0_FLAG, NULL, NULL, 0, 0 },
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#endif
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#ifdef TIMER_1
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{ TIMER_1, TIMER_1_MASK, TIMER_1_FLAG, NULL, NULL, 0, 0 },
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#endif
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#ifdef TIMER_2
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{ TIMER_2, TIMER_2_MASK, TIMER_2_FLAG, NULL, NULL, 0, 0 },
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#endif
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#ifdef TIMER_3
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{ TIMER_3, TIMER_3_MASK, TIMER_3_FLAG, NULL, NULL, 0, 0 },
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#endif
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};
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#else
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/* fallback if no timer is configured */
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static ctx_t *ctx[] = {{ NULL }};
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#endif
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/** @} */
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/**
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* @brief Setup the given timer
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*
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*/
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int timer_init(tim_t dev, unsigned long freq, timer_cb_t cb, void *arg)
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int timer_init(tim_t tim, unsigned long freq, timer_cb_t cb, void *arg)
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{
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/* reject impossible freq values
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* todo: Add support for 2 MHz and 16 MHz */
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if ((freq != 250000ul)) {
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uint8_t pre = 0;
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/* make sure given device is valid */
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if (tim >= TIMER_NUMOF) {
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return -1;
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}
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/* select the timer and enable the timer specific peripheral clocks */
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switch (dev) {
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#if TIMER_0_EN
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case TIMER_0:
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TIMER0_COUNTER = 0;
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TIMER0_CONTROL_B |= TIMER0_FREQ_250KHZ;
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/* figure out if freq is applicable */
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for (; pre < PRESCALE_NUMOF; pre++) {
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if ((CLOCK_CORECLOCK >> prescalers[pre]) == freq) {
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break;
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#endif
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#if TIMER_1_EN
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case TIMER_1:
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TIMER1_COUNTER = 0;
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TIMER1_CONTROL_B |= TIMER1_FREQ_250KHZ;
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break;
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#endif
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#if TIMER_2_EN
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case TIMER_2:
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TIMER2_COUNTER = 0;
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TIMER2_CONTROL_B |= TIMER2_FREQ_250KHZ;
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break;
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#endif
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case TIMER_UNDEFINED:
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default:
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return -1;
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}
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}
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if (pre == PRESCALE_NUMOF) {
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return -1;
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}
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/* save callback */
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config[dev].cb = cb;
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config[dev].arg = arg;
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/* stop and reset timer */
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ctx[tim].dev->CRA = 0;
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ctx[tim].dev->CRB = 0;
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ctx[tim].dev->CRC = 0;
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ctx[tim].dev->CNT = 0;
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/* save interrupt context and timer mode */
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ctx[tim].cb = cb;
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ctx[tim].arg = arg;
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ctx[tim].mode = (pre + 1);
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/* enable timer with calculated prescaler */
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ctx[tim].dev->CRB = (pre + 1);
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return 0;
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}
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int timer_set(tim_t dev, int channel, unsigned int timeout)
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int timer_set(tim_t tim, int channel, unsigned int timeout)
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{
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return timer_set_absolute(dev, channel, timer_read(dev) + timeout);
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return timer_set_absolute(tim, channel, timer_read(tim) + timeout);
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}
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int timer_set_absolute(tim_t dev, int channel, unsigned int value)
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int timer_set_absolute(tim_t tim, int channel, unsigned int value)
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{
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unsigned state = irq_disable();
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switch (dev) {
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#if TIMER_0_EN
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case TIMER_0:
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switch (channel) {
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case 0:
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TIMER0_COMP_A = (uint16_t) value;
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TIMER0_IRQ_FLAG_REG &= ~(1 << TIMER0_COMP_A_FLAG);
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TIMER0_IRQ_MASK_REG |= (1 << TIMER0_COMP_A_EN);
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break;
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case 1:
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TIMER0_COMP_B = (uint16_t) value;
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TIMER0_IRQ_FLAG_REG &= ~(1 << TIMER0_COMP_B_FLAG);
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TIMER0_IRQ_MASK_REG |= (1 << TIMER0_COMP_B_EN);
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break;
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case 2:
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TIMER0_COMP_C = (uint16_t) value;
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TIMER0_IRQ_FLAG_REG &= ~(1 << TIMER0_COMP_C_FLAG);
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TIMER0_IRQ_MASK_REG |= (1 << TIMER0_COMP_C_EN);
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break;
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default:
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irq_restore(state);
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return -1;
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}
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break;
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#endif
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#if TIMER_1_EN
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case TIMER_1:
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switch (channel) {
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case 0:
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TIMER1_COMP_A = (uint16_t) value;
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TIMER1_IRQ_FLAG_REG &= ~(1 << TIMER1_COMP_A_FLAG);
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TIMER1_IRQ_MASK_REG |= (1 << TIMER1_COMP_A_EN);
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break;
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case 1:
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TIMER1_COMP_B = (uint16_t) value;
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TIMER1_IRQ_FLAG_REG &= ~(1 << TIMER1_COMP_B_FLAG);
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TIMER1_IRQ_MASK_REG |= (1 << TIMER1_COMP_B_EN);
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break;
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case 2:
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TIMER1_COMP_C = (uint16_t) value;
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TIMER1_IRQ_FLAG_REG &= ~(1 << TIMER1_COMP_C_FLAG);
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TIMER1_IRQ_MASK_REG |= (1 << TIMER1_COMP_C_EN);
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break;
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default:
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irq_restore(state);
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return -1;
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}
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break;
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#endif
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#if TIMER_2_EN
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case TIMER_2:
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switch (channel) {
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case 0:
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TIMER2_COMP_A = (uint16_t) value;
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TIMER2_IRQ_FLAG_REG &= ~(1 << TIMER2_COMP_A_FLAG);
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TIMER2_IRQ_MASK_REG |= (1 << TIMER2_COMP_A_EN);
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break;
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case 1:
|
||||
TIMER2_COMP_B = (uint16_t) value;
|
||||
TIMER2_IRQ_FLAG_REG &= ~(1 << TIMER2_COMP_B_FLAG);
|
||||
TIMER2_IRQ_MASK_REG |= (1 << TIMER2_COMP_B_EN);
|
||||
break;
|
||||
|
||||
case 2:
|
||||
TIMER2_COMP_C = (uint16_t) value;
|
||||
TIMER2_IRQ_FLAG_REG &= ~(1 << TIMER2_COMP_C_FLAG);
|
||||
TIMER2_IRQ_MASK_REG |= (1 << TIMER2_COMP_C_EN);
|
||||
break;
|
||||
|
||||
default:
|
||||
irq_restore(state);
|
||||
return -1;
|
||||
}
|
||||
|
||||
break;
|
||||
#endif
|
||||
|
||||
case TIMER_UNDEFINED:
|
||||
default:
|
||||
irq_restore(state);
|
||||
return -1;
|
||||
if (channel >= CHANNELS) {
|
||||
return -1;
|
||||
}
|
||||
|
||||
/* enable interrupts for given timer */
|
||||
timer_irq_enable(dev);
|
||||
irq_restore(state);
|
||||
ctx[tim].dev->OCR[channel] = (uint16_t)value;
|
||||
*ctx[tim].flag &= ~(1 << (channel + OCF1A));
|
||||
*ctx[tim].mask |= (1 << (channel + OCIE1A));
|
||||
|
||||
return 1;
|
||||
return 0;
|
||||
}
|
||||
|
||||
int timer_clear(tim_t dev, int channel)
|
||||
int timer_clear(tim_t tim, int channel)
|
||||
{
|
||||
switch (dev) {
|
||||
#if TIMER_0_EN
|
||||
case TIMER_0:
|
||||
switch (channel) {
|
||||
case 0:
|
||||
TIMER0_IRQ_FLAG_REG &= ~(1 << TIMER0_COMP_A_FLAG);
|
||||
break;
|
||||
|
||||
case 1:
|
||||
TIMER0_IRQ_FLAG_REG &= ~(1 << TIMER0_COMP_B_FLAG);
|
||||
break;
|
||||
|
||||
case 2:
|
||||
TIMER0_IRQ_FLAG_REG &= ~(1 << TIMER0_COMP_C_FLAG);
|
||||
break;
|
||||
|
||||
default:
|
||||
return -1;
|
||||
}
|
||||
|
||||
break;
|
||||
#endif
|
||||
#if TIMER_1_EN
|
||||
case TIMER_1:
|
||||
switch (channel) {
|
||||
case 0:
|
||||
TIMER1_IRQ_FLAG_REG &= ~(1 << TIMER1_COMP_A_FLAG);
|
||||
break;
|
||||
|
||||
case 1:
|
||||
TIMER1_IRQ_FLAG_REG &= ~(1 << TIMER1_COMP_B_FLAG);
|
||||
break;
|
||||
|
||||
case 2:
|
||||
TIMER1_IRQ_FLAG_REG &= ~(1 << TIMER1_COMP_C_FLAG);
|
||||
break;
|
||||
|
||||
default:
|
||||
return -1;
|
||||
break;
|
||||
}
|
||||
|
||||
break;
|
||||
#endif
|
||||
#if TIMER_2_EN
|
||||
|
||||
case TIMER_2:
|
||||
switch (channel) {
|
||||
case 0:
|
||||
TIMER2_IRQ_FLAG_REG &= ~(1 << TIMER2_COMP_A_FLAG);
|
||||
break;
|
||||
|
||||
case 1:
|
||||
TIMER2_IRQ_FLAG_REG &= ~(1 << TIMER2_COMP_B_FLAG);
|
||||
break;
|
||||
|
||||
case 2:
|
||||
TIMER2_IRQ_FLAG_REG &= ~(1 << TIMER2_COMP_C_FLAG);
|
||||
break;
|
||||
|
||||
default:
|
||||
return -1;
|
||||
break;
|
||||
}
|
||||
|
||||
break;
|
||||
#endif
|
||||
|
||||
case TIMER_UNDEFINED:
|
||||
default:
|
||||
return -1;
|
||||
if (channel >= CHANNELS) {
|
||||
return -1;
|
||||
}
|
||||
|
||||
timer_irq_disable(dev);
|
||||
return 1;
|
||||
*ctx[tim].mask &= ~(1 << (channel + OCIE1A));
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
unsigned int timer_read(tim_t dev)
|
||||
unsigned int timer_read(tim_t tim)
|
||||
{
|
||||
uint16_t a;
|
||||
uint16_t b;
|
||||
/*
|
||||
* Disabling interrupts globally because read from 16 Bit register can
|
||||
* otherwise be messed up
|
||||
*/
|
||||
unsigned state = irq_disable();
|
||||
|
||||
switch (dev) {
|
||||
#if TIMER_0_EN
|
||||
|
||||
case TIMER_0:
|
||||
do {
|
||||
a = TIMER0_COUNTER;
|
||||
b = TIMER0_COUNTER;
|
||||
} while (a != b);
|
||||
break;
|
||||
#endif
|
||||
#if TIMER_1_EN
|
||||
|
||||
case TIMER_1:
|
||||
do {
|
||||
a = TIMER1_COUNTER;
|
||||
b = TIMER1_COUNTER;
|
||||
} while (a != b);
|
||||
break;
|
||||
#endif
|
||||
#if TIMER_2_EN
|
||||
|
||||
case TIMER_2:
|
||||
do {
|
||||
a = TIMER2_COUNTER;
|
||||
b = TIMER2_COUNTER;
|
||||
} while (a != b);
|
||||
break;
|
||||
#endif
|
||||
|
||||
case TIMER_UNDEFINED:
|
||||
default:
|
||||
(void)b;
|
||||
a = 0;
|
||||
}
|
||||
|
||||
irq_restore(state);
|
||||
return a;
|
||||
return (unsigned int)ctx[tim].dev->CNT;
|
||||
}
|
||||
|
||||
void timer_stop(tim_t dev)
|
||||
void timer_stop(tim_t tim)
|
||||
{
|
||||
switch (dev) {
|
||||
#if TIMER_0_EN
|
||||
|
||||
case TIMER_0:
|
||||
TIMER0_CONTROL_B = TIMER0_FREQ_DISABLE;
|
||||
break;
|
||||
#endif
|
||||
#if TIMER_1_EN
|
||||
|
||||
case TIMER_1:
|
||||
TIMER1_CONTROL_B = TIMER1_FREQ_DISABLE;
|
||||
break;
|
||||
#endif
|
||||
#if TIMER_2_EN
|
||||
|
||||
case TIMER_2:
|
||||
TIMER2_CONTROL_B = TIMER2_FREQ_DISABLE;
|
||||
break;
|
||||
#endif
|
||||
|
||||
case TIMER_UNDEFINED:
|
||||
break;
|
||||
}
|
||||
ctx[tim].dev->CRB = 0;
|
||||
}
|
||||
|
||||
void timer_start(tim_t dev)
|
||||
void timer_start(tim_t tim)
|
||||
{
|
||||
switch (dev) {
|
||||
#if TIMER_0_EN
|
||||
|
||||
case TIMER_0:
|
||||
TIMER0_CONTROL_B |= TIMER0_FREQ_250KHZ;
|
||||
break;
|
||||
#endif
|
||||
#if TIMER_1_EN
|
||||
|
||||
case TIMER_1:
|
||||
TIMER1_CONTROL_B |= TIMER1_FREQ_250KHZ;
|
||||
break;
|
||||
#endif
|
||||
#if TIMER_2_EN
|
||||
|
||||
case TIMER_2:
|
||||
TIMER1_CONTROL_B |= TIMER1_FREQ_250KHZ;
|
||||
break;
|
||||
#endif
|
||||
|
||||
case TIMER_UNDEFINED:
|
||||
break;
|
||||
}
|
||||
ctx[tim].dev->CRB = ctx[tim].mode;
|
||||
}
|
||||
|
||||
void timer_irq_enable(tim_t dev)
|
||||
void timer_irq_enable(tim_t tim)
|
||||
{
|
||||
(void) dev;
|
||||
#ifdef DEVELHELP
|
||||
printf("timer_irq_enable not implemented\n");
|
||||
#endif
|
||||
*ctx[tim].mask = ctx[tim].isrs;
|
||||
}
|
||||
|
||||
void timer_irq_disable(tim_t dev)
|
||||
void timer_irq_disable(tim_t tim)
|
||||
{
|
||||
switch (dev) {
|
||||
#if TIMER_0_EN
|
||||
case TIMER_0:
|
||||
TIMER0_IRQ_MASK_REG &= ~(1 << TIMER0_COMP_A_EN);
|
||||
TIMER0_IRQ_MASK_REG &= ~(1 << TIMER0_COMP_B_EN);
|
||||
TIMER0_IRQ_MASK_REG &= ~(1 << TIMER0_COMP_C_EN);
|
||||
break;
|
||||
#endif
|
||||
#if TIMER_1_EN
|
||||
case TIMER_1:
|
||||
TIMER1_IRQ_MASK_REG &= ~(1 << TIMER1_COMP_A_EN);
|
||||
TIMER1_IRQ_MASK_REG &= ~(1 << TIMER1_COMP_B_EN);
|
||||
TIMER1_IRQ_MASK_REG &= ~(1 << TIMER1_COMP_C_EN);
|
||||
break;
|
||||
#endif
|
||||
#if TIMER_2_EN
|
||||
case TIMER_2:
|
||||
TIMER2_IRQ_MASK_REG &= ~(1 << TIMER2_COMP_A_EN);
|
||||
TIMER2_IRQ_MASK_REG &= ~(1 << TIMER2_COMP_B_EN);
|
||||
TIMER2_IRQ_MASK_REG &= ~(1 << TIMER2_COMP_C_EN);
|
||||
break;
|
||||
#endif
|
||||
case TIMER_UNDEFINED:
|
||||
break;
|
||||
}
|
||||
ctx[tim].isrs = *(ctx[tim].mask);
|
||||
*ctx[tim].mask = 0;
|
||||
}
|
||||
|
||||
static inline void _isr(int timer, int chan)
|
||||
static inline void _isr(int num, int chan)
|
||||
{
|
||||
__enter_isr();
|
||||
timer_clear(timer, chan);
|
||||
|
||||
config[timer].cb(config[timer].arg, chan);
|
||||
*ctx[num].mask &= ~(1 << (chan + OCIE1A));
|
||||
ctx[num].cb(ctx[num].arg, chan);
|
||||
|
||||
if (sched_context_switch_request) {
|
||||
thread_yield();
|
||||
}
|
||||
|
||||
__exit_isr();
|
||||
}
|
||||
|
||||
#if TIMER_0_EN
|
||||
ISR(TIMER0_COMPA_ISR, ISR_BLOCK)
|
||||
#ifdef TIMER_0
|
||||
ISR(TIMER_0_ISRA, ISR_BLOCK)
|
||||
{
|
||||
_isr(0, 0);
|
||||
}
|
||||
|
||||
ISR(TIMER0_COMPB_ISR, ISR_BLOCK)
|
||||
ISR(TIMER_0_ISRB, ISR_BLOCK)
|
||||
{
|
||||
_isr(0, 1);
|
||||
}
|
||||
|
||||
ISR(TIMER0_COMPC_ISR, ISR_BLOCK)
|
||||
ISR(TIMER_0_ISRC, ISR_BLOCK)
|
||||
{
|
||||
_isr(0, 2);
|
||||
}
|
||||
#endif /* TIMER_0_EN */
|
||||
#endif /* TIMER_0 */
|
||||
|
||||
#if TIMER_1_EN
|
||||
ISR(TIMER1_COMPA_ISR, ISR_BLOCK)
|
||||
#ifdef TIMER_1
|
||||
ISR(TIMER_1_ISRA, ISR_BLOCK)
|
||||
{
|
||||
_isr(1, 0);
|
||||
}
|
||||
|
||||
ISR(TIMER1_COMPB_ISR, ISR_BLOCK)
|
||||
ISR(TIMER_1_ISRB, ISR_BLOCK)
|
||||
{
|
||||
_isr(1, 1);
|
||||
}
|
||||
|
||||
ISR(TIMER1_COMPC_ISR, ISR_BLOCK)
|
||||
ISR(TIMER_1_ISRC, ISR_BLOCK)
|
||||
{
|
||||
_isr(1, 2);
|
||||
}
|
||||
#endif /* TIMER_1_EN */
|
||||
#endif /* TIMER_1 */
|
||||
|
||||
#if TIMER_2_EN
|
||||
ISR(TIMER2_COMPA_ISR, ISR_BLOCK)
|
||||
#ifdef TIMER_2
|
||||
ISR(TIMER_2_ISRA, ISR_BLOCK)
|
||||
{
|
||||
_isr(2, 0);
|
||||
}
|
||||
|
||||
ISR(TIMER2_COMPB_ISR, ISR_BLOCK)
|
||||
ISR(TIMER_2_ISRB, ISR_BLOCK)
|
||||
{
|
||||
_isr(2, 1);
|
||||
}
|
||||
|
||||
ISR(TIMER2_COMPC_ISR, ISR_BLOCK)
|
||||
ISR(TIMER_2_ISRC, ISR_BLOCK)
|
||||
{
|
||||
_isr(2, 2);
|
||||
}
|
||||
#endif /* TIMER_2_EN */
|
||||
#endif /* TIMER_2 */
|
||||
|
||||
#ifdef TIMER_3
|
||||
ISR(TIMER_3_ISRA, ISR_BLOCK)
|
||||
{
|
||||
_isr(2, 0);
|
||||
}
|
||||
|
||||
ISR(TIMER_3_ISRB, ISR_BLOCK)
|
||||
{
|
||||
_isr(2, 1);
|
||||
}
|
||||
|
||||
ISR(TIMER_3_ISRC, ISR_BLOCK)
|
||||
{
|
||||
_isr(2, 2);
|
||||
}
|
||||
#endif /* TIMER_3 */
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user