From 3c74301718d193c6acad1f71c8632b7a831fd9ee Mon Sep 17 00:00:00 2001 From: Hendrik van Essen Date: Fri, 20 Jun 2025 09:53:05 +0200 Subject: [PATCH 1/3] cpu/sam0_common/periph/dac.c: dont use DAC_CTRLA_SWRST DAC_CTRLA_SWRST clears all registers, so it also clears the config of the first DAC line after configuring the second DAC line. --- cpu/sam0_common/periph/dac.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/cpu/sam0_common/periph/dac.c b/cpu/sam0_common/periph/dac.c index bacd3ab40b..96d7a62420 100644 --- a/cpu/sam0_common/periph/dac.c +++ b/cpu/sam0_common/periph/dac.c @@ -110,8 +110,8 @@ int8_t dac_init(dac_t line) _dac_init_clock(line); - /* Settings can only be changed when DAC is disabled, reset config */ - DAC->CTRLA.reg = DAC_CTRLA_SWRST; + /* Settings can only be changed when DAC is disabled */ + DAC->CTRLA.reg &= ~DAC_CTRLA_ENABLE; _sync(); #ifdef DAC_DACCTRL_ENABLE @@ -126,7 +126,7 @@ int8_t dac_init(dac_t line) #endif ; - DAC->CTRLA.reg = DAC_CTRLA_ENABLE; + DAC->CTRLA.reg |= DAC_CTRLA_ENABLE; _sync(); #ifdef DAC_STATUS_READY From 4af71d9bc783489b4d5dded542c7391a89fd52ab Mon Sep 17 00:00:00 2001 From: Hendrik van Essen Date: Fri, 20 Jun 2025 09:54:33 +0200 Subject: [PATCH 2/3] cpu/sam0_common/periph/dac.c: add option to keep DAC running in standby --- cpu/sam0_common/periph/dac.c | 16 ++++++++++++++-- 1 file changed, 14 insertions(+), 2 deletions(-) diff --git a/cpu/sam0_common/periph/dac.c b/cpu/sam0_common/periph/dac.c index 96d7a62420..1a0a8da725 100644 --- a/cpu/sam0_common/periph/dac.c +++ b/cpu/sam0_common/periph/dac.c @@ -27,6 +27,10 @@ #define DAC_VAL(in) (in >> (16 - DAC_RES_BITS)) +#ifndef CONFIG_SAM0_DAC_RUN_ON_STANDBY +#define CONFIG_SAM0_DAC_RUN_ON_STANDBY 0 +#endif + static void _dac_init_clock(dac_t line) { sam0_gclk_enable(DAC_CLOCK); @@ -116,8 +120,12 @@ int8_t dac_init(dac_t line) #ifdef DAC_DACCTRL_ENABLE DAC->DACCTRL[line].reg = DAC_DACCTRL_ENABLE - | _get_CCTRL(sam0_gclk_freq(DAC_CLOCK)); + | _get_CCTRL(sam0_gclk_freq(DAC_CLOCK)) #endif +#if CONFIG_SAM0_DAC_RUN_ON_STANDBY && defined(DAC_DACCTRL_RUNSTDBY) + | DAC_DACCTRL_RUNSTDBY +#endif + ; /* Set Reference Voltage & enable Output if needed */ DAC->CTRLB.reg = DAC_VREF @@ -126,7 +134,11 @@ int8_t dac_init(dac_t line) #endif ; - DAC->CTRLA.reg |= DAC_CTRLA_ENABLE; + DAC->CTRLA.reg = DAC_CTRLA_ENABLE +#if CONFIG_SAM0_DAC_RUN_ON_STANDBY && defined(DAC_CTRLA_RUNSTDBY) + | DAC_CTRLA_RUNSTDBY +#endif + ; _sync(); #ifdef DAC_STATUS_READY From b157d5ca3e0d9340d12959722c989389832cb7ae Mon Sep 17 00:00:00 2001 From: Hendrik van Essen Date: Fri, 20 Jun 2025 09:55:07 +0200 Subject: [PATCH 3/3] cpu/sam0_common/periph/dac.c: do conversion refresh by default --- cpu/sam0_common/periph/dac.c | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/cpu/sam0_common/periph/dac.c b/cpu/sam0_common/periph/dac.c index 1a0a8da725..00b14e2301 100644 --- a/cpu/sam0_common/periph/dac.c +++ b/cpu/sam0_common/periph/dac.c @@ -27,6 +27,10 @@ #define DAC_VAL(in) (in >> (16 - DAC_RES_BITS)) +#ifndef CONFIG_SAM0_DAC_REFRESH +#define CONFIG_SAM0_DAC_REFRESH 2 +#endif + #ifndef CONFIG_SAM0_DAC_RUN_ON_STANDBY #define CONFIG_SAM0_DAC_RUN_ON_STANDBY 0 #endif @@ -127,6 +131,18 @@ int8_t dac_init(dac_t line) #endif ; +#ifdef DAC_DACCTRL_REFRESH + /** The DAC can only maintain its output on the desired value for approximately 100 μs. + * For static voltages the conversion must be refreshed periodically (see e.g. + * '47.6.9.3 Conversion Refresh' in the SAM D5xE5x family data sheet). + * + * Note: T_REFRESH = REFRESH * T_OSCULP32K + */ + static_assert(CONFIG_SAM0_DAC_REFRESH != 1, "DACCTRLx.REFRESH = 1 is reserved"); + + DAC->DACCTRL[line].bit.REFRESH = CONFIG_SAM0_DAC_REFRESH; +#endif + /* Set Reference Voltage & enable Output if needed */ DAC->CTRLB.reg = DAC_VREF #ifdef DAC_CTRLB_EOEN