diff --git a/boards/b-l072z-lrwan1/include/periph_conf.h b/boards/b-l072z-lrwan1/include/periph_conf.h
index 95ec36a4b3..25f0e0d66e 100644
--- a/boards/b-l072z-lrwan1/include/periph_conf.h
+++ b/boards/b-l072z-lrwan1/include/periph_conf.h
@@ -31,6 +31,7 @@ extern "C" {
  */
 #define CLOCK_HSI           (16000000U)         /* internal oscillator */
 #define CLOCK_CORECLOCK     (32000000U)         /* desired core clock frequency */
+#define CLOCK_LSE           (1)                 /* enable low speed external oscillator */
 
 /* configuration of PLL prescaler and multiply values */
 /* CORECLOCK := HSI / CLOCK_PLL_DIV * CLOCK_PLL_MUL */
diff --git a/boards/nucleo-l073rz/include/periph_conf.h b/boards/nucleo-l073rz/include/periph_conf.h
index f80178faad..59bec45bfd 100644
--- a/boards/nucleo-l073rz/include/periph_conf.h
+++ b/boards/nucleo-l073rz/include/periph_conf.h
@@ -35,6 +35,7 @@ extern "C" {
  */
 #define CLOCK_HSI           (16000000U)         /* internal oscillator */
 #define CLOCK_CORECLOCK     (32000000U)         /* desired core clock frequency */
+#define CLOCK_LSE           (1)                 /* enable low speed external oscillator */
 
 /* configuration of PLL prescaler and multiply values */
 /* CORECLOCK := HSI / CLOCK_PLL_DIV * CLOCK_PLL_MUL */
diff --git a/cpu/stm32_common/periph/rtc.c b/cpu/stm32_common/periph/rtc.c
index 143e85f5b3..8dafeb1b86 100644
--- a/cpu/stm32_common/periph/rtc.c
+++ b/cpu/stm32_common/periph/rtc.c
@@ -138,6 +138,14 @@
  * offset of 100 years. */
 #define YEAR_OFFSET         (100)
 
+/* Use a magic number to determine the initial RTC source. This will be used
+   to know if a reset of the RTC is required at initialization. */
+#if CLOCK_LSE
+#define MAGIC_CLCK_NUMBER       (0x1970)
+#else
+#define MAGIC_CLCK_NUMBER       (0x1971)
+#endif
+
 static struct {
     rtc_alarm_cb_t cb;          /**< callback called from RTC interrupt */
     void *arg;                  /**< argument passed to the callback */
@@ -186,6 +194,19 @@ static inline void rtc_lock(void)
 
 void rtc_init(void)
 {
+    stmclk_dbp_unlock();
+#if defined(CPU_FAM_STM32L0) || defined(CPU_FAM_STM32L1)
+    /* Compare the stored magic number with the current one. If it's different
+       it means the clock source has changed and thus a RTC reset is
+       required. */
+    if (RTC->BKP0R != MAGIC_CLCK_NUMBER) {
+        RCC->CSR |= RCC_CSR_RTCRST;
+        RCC->CSR &= ~RCC_CSR_RTCRST;
+        RTC->BKP0R = MAGIC_CLCK_NUMBER; /* Store the new magic number */
+    }
+#endif
+    stmclk_dbp_lock();
+
     /* enable low frequency clock */
     stmclk_enable_lfclk();