From 5f6b182a8dc627eb0a91ea37bfc9d282cf4d030d Mon Sep 17 00:00:00 2001
From: Toon Stegen <toon.stegen@altran.com>
Date: Thu, 19 May 2016 16:40:48 +0200
Subject: [PATCH] stm32f2: add initialization of PLL I2S for MCO2

To use it, add the following defines to your periph_conf.h:
/* prescaler for 8MHz I2S clock */
#define ENABLE_PLLI2S_MCO2  1
#define CLOCK_PLL_I2S_R     (6U)
#define CLOCK_PLL_I2S_N     (240U)
---
 cpu/stm32f2/cpu.c | 19 +++++++++++++++++++
 1 file changed, 19 insertions(+)

diff --git a/cpu/stm32f2/cpu.c b/cpu/stm32f2/cpu.c
index e02892b110..3d8f7ef123 100644
--- a/cpu/stm32f2/cpu.c
+++ b/cpu/stm32f2/cpu.c
@@ -91,6 +91,25 @@ static void clk_init(void)
     /* set main PLL division factor for USB OTG FS, SDIO and RNG clocks */
     RCC->PLLCFGR |= (CLOCK_PLL_Q & 0x0F) << 24;
 
+#ifdef ENABLE_PLLI2S_MCO2
+    /* reset PLL I2S config register */
+    RCC->PLLI2SCFGR = 0x00000000U;
+    /* set PLL I2S division factor */
+    RCC->PLLI2SCFGR |= (CLOCK_PLL_I2S_R & 0x07) << 28;
+    /* set PLL I2S multiplication factor */
+    RCC->PLLI2SCFGR |= (CLOCK_PLL_I2S_N & 0x1FF) << 6;
+
+    /* MCO2 output is PLLI2S */
+    RCC->CFGR |= (uint32_t) RCC_CFGR_MCO2_0;
+    RCC->CFGR &= ~(uint32_t) RCC_CFGR_MCO2_1;
+    /* MCO2 prescaler div by 5 */
+    RCC->CFGR |= (uint32_t) RCC_CFGR_MCO2PRE_0 | RCC_CFGR_MCO2PRE_1 | RCC_CFGR_MCO2PRE_2 ;
+    /* enable PLL I2S clock */
+    RCC->CR |= RCC_CR_PLLI2SON;
+    /* wait till PLL I2S clock is ready */
+    while ((RCC->CR & RCC_CR_PLLI2SRDY) == 0) {}
+#endif
+
     /* Enable PLL */
     RCC->CR |= RCC_CR_PLLON;
     /* Wait till PLL is ready */