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cpu/stm32l4: add support for stm32l496zg

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This commit is contained in:
Alexandre Abadie 2017-05-20 17:40:25 +02:00
parent ecb2e4767d
commit 601846c2ba
3 changed files with 19801 additions and 3 deletions
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6
cpu/stm32l4/include/cpu_conf.h
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@ -25,7 +25,9 @@
#include "cpu_conf_common.h"
#if defined(CPU_MODEL_STM32L476RG)
#if defined(CPU_MODEL_STM32L496ZG)
#include "vendor/stm32l496xx.h"
#elif defined(CPU_MODEL_STM32L476RG)
#include "vendor/stm32l476xx.h"
#elif defined(CPU_MODEL_STM32L475VG)
#include "vendor/stm32l475xx.h"
@ -48,6 +50,8 @@ extern "C" {
#define CPU_DEFAULT_IRQ_PRIO (1U)
#if defined(CPU_MODEL_STM32L432KC) || defined(CPU_MODEL_STM32L433RC)
#define CPU_IRQ_NUMOF (83U)
#elif defined(CPU_MODEL_STM32L496ZG)
#define CPU_IRQ_NUMOF (91U)
#else
#define CPU_IRQ_NUMOF (82U)
#endif

19768
cpu/stm32l4/include/vendor/stm32l496xx.h vendored Normal file
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File diff suppressed because it is too large Load Diff

30
cpu/stm32l4/vectors.c
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@ -34,8 +34,13 @@ WEAK_DEFAULT void isr_can1_rx0(void);
WEAK_DEFAULT void isr_can1_rx1(void);
WEAK_DEFAULT void isr_can1_sce(void);
WEAK_DEFAULT void isr_can1_tx(void);
WEAK_DEFAULT void isr_can2_rx0(void);
WEAK_DEFAULT void isr_can2_rx1(void);
WEAK_DEFAULT void isr_can2_sce(void);
WEAK_DEFAULT void isr_can2_tx(void);
WEAK_DEFAULT void isr_comp(void);
WEAK_DEFAULT void isr_crs(void);
WEAK_DEFAULT void isr_dcmi(void);
WEAK_DEFAULT void isr_dfsdm1_flt0(void);
WEAK_DEFAULT void isr_dfsdm1_flt1(void);
WEAK_DEFAULT void isr_dfsdm1_flt2(void);
@ -54,6 +59,7 @@ WEAK_DEFAULT void isr_dma2_channel4(void);
WEAK_DEFAULT void isr_dma2_channel5(void);
WEAK_DEFAULT void isr_dma2_channel6(void);
WEAK_DEFAULT void isr_dma2_channel7(void);
WEAK_DEFAULT void isr_dma2d(void);
WEAK_DEFAULT void isr_exti(void);
WEAK_DEFAULT void isr_flash(void);
WEAK_DEFAULT void isr_fmc(void);
@ -64,6 +70,8 @@ WEAK_DEFAULT void isr_i2c2_er(void);
WEAK_DEFAULT void isr_i2c2_ev(void);
WEAK_DEFAULT void isr_i2c3_er(void);
WEAK_DEFAULT void isr_i2c3_ev(void);
WEAK_DEFAULT void isr_i2c4_ev(void);
WEAK_DEFAULT void isr_i2c4_er(void);
WEAK_DEFAULT void isr_lcd(void);
WEAK_DEFAULT void isr_lptim1(void);
WEAK_DEFAULT void isr_lptim2(void);
@ -172,7 +180,7 @@ ISR_VECTOR(1) const isr_t vector_cpu[CPU_IRQ_NUMOF] = {
[CRS_IRQn ] = isr_crs, /* [82] CRS global interrupt */
#endif
#if defined(CPU_MODEL_STM32L476RG) || defined(CPU_MODEL_STM32L475VG) || \
defined(CPU_MODEL_STM32L452RE)
defined(CPU_MODEL_STM32L452RE) || defined(CPU_MODEL_STM32L496ZG)
[ADC1_2_IRQn ] = isr_adc1_2, /* [18] ADC1, ADC2 SAR global Interrupts */
[TIM1_TRG_COM_TIM17_IRQn ] = isr_tim1_trg_com_tim17, /* [26] TIM1 Trigger and Commutation Interrupt and TIM17 global interrupt */
[TIM3_IRQn ] = isr_tim3, /* [29] TIM3 global Interrupt */
@ -201,11 +209,29 @@ ISR_VECTOR(1) const isr_t vector_cpu[CPU_IRQ_NUMOF] = {
[SAI2_IRQn ] = isr_sai2, /* [75] Serial Audio Interface 2 global interrupt */
#endif
#if defined(CPU_MODEL_STM32L432KC) || defined(CPU_MODEL_STM32L476RG) || \
defined(CPU_MODEL_STM32L475VG)
defined(CPU_MODEL_STM32L475VG) || defined(CPU_MODEL_STM32L496ZG)
[TIM7_IRQn ] = isr_tim7, /* [55] TIM7 global interrupt */
[SWPMI1_IRQn ] = isr_swpmi1, /* [76] Serial Wire Interface 1 global interrupt */
#endif
#if defined(CPU_MODEL_STM32L476RG)
[LCD_IRQn ] = isr_lcd, /* [78] LCD global interrupt */
#endif
#if defined(CPU_MODEL_STM32L496ZG)
[TIM4_IRQn ] = isr_tim4, /* [30] TIM4 global Interrupt */
[TIM5_IRQn ] = isr_tim5, /* [50] TIM5 global Interrupt */
[UART5_IRQn ] = isr_uart5, /* [53] UART5 global Interrupt */
[DFSDM1_FLT2_IRQn ] = isr_dfsdm1_flt2, /* [63] DFSDM1 Filter 2 global Interrupt */
[OTG_FS_IRQn ] = isr_otg_fs, /* [67] USB OTG FS global Interrupt */
[SAI2_IRQn ] = isr_sai2, /* [75] Serial Audio Interface 2 global interrupt */
[LCD_IRQn ] = isr_lcd, /* [78] LCD global interrupt */
[CRS_IRQn ] = isr_crs, /* [82] CRS global interrupt */
[I2C4_EV_IRQn ] = isr_i2c4_ev, /* [83] I2C4 Event interrupt */
[I2C4_ER_IRQn ] = isr_i2c4_er, /* [84] I2C4 Error interrupt */
[DCMI_IRQn ] = isr_dcmi, /* [85] DCMI global interrupt */
[CAN2_TX_IRQn ] = isr_can2_tx, /* [86] CAN2 TX interrupt */
[CAN2_RX0_IRQn ] = isr_can2_rx0, /* [87] CAN2 RX0 interrupt */
[CAN2_RX1_IRQn ] = isr_can2_rx1, /* [88] CAN2 RX1 interrupt */
[CAN2_SCE_IRQn ] = isr_can2_sce, /* [89] CAN2 SCE interrupt */
[DMA2D_IRQn ] = isr_dma2d, /* [90] DMA2D global interrupt */
#endif
};