diff --git a/cpu/k22f/include/cpu_conf.h b/cpu/k22f/include/cpu_conf.h index 167305a367..e77181614a 100644 --- a/cpu/k22f/include/cpu_conf.h +++ b/cpu/k22f/include/cpu_conf.h @@ -22,52 +22,19 @@ #ifndef CPU_CONF_H #define CPU_CONF_H -#include "cpu_conf_common.h" - #ifdef CPU_MODEL_MK22FN512VLH12 #include "vendor/MK22F51212.h" #else #error "undefined CPU_MODEL" #endif +#include "cpu_conf_kinetis.h" + #ifdef __cplusplus extern "C" { #endif -/** - * @name ARM Cortex-M specific CPU configuration - * @{ - */ -#define CPU_DEFAULT_IRQ_PRIO (1U) -#define CPU_IRQ_NUMOF (89U) -#define CPU_FLASH_BASE (0x00000000) -/** @} */ - -/** - * @name GPIO pin mux function numbers - * @{ - */ -#define PIN_MUX_FUNCTION_ANALOG 0 -#define PIN_MUX_FUNCTION_GPIO 1 -/** @} */ -/** - * @name GPIO interrupt flank settings - * @{ - */ -#define PIN_INTERRUPT_RISING 0b1001 -#define PIN_INTERRUPT_FALLING 0b1010 -#define PIN_INTERRUPT_EDGE 0b1011 -/** @} */ - -/** - * @name Timer hardware information - * @{ - */ -#define LPTMR_CLKEN() (bit_set32(&SIM->SCGC5, SIM_SCGC5_LPTMR_SHIFT)) /**< Enable LPTMR0 clock gate */ -#define PIT_CLKEN() (bit_set32(&SIM->SCGC6, SIM_SCGC6_PIT_SHIFT)) /**< Enable PIT clock gate */ -/** @} */ - #ifdef __cplusplus } #endif diff --git a/cpu/k60/include/cpu_conf.h b/cpu/k60/include/cpu_conf.h index 8c92986641..942d954bcd 100644 --- a/cpu/k60/include/cpu_conf.h +++ b/cpu/k60/include/cpu_conf.h @@ -7,9 +7,10 @@ */ /** - * @defgroup cpu_k60 Freescale Kinetis K60 + * @defgroup cpu_k60 NXP Kinetis K60 * @ingroup cpu - * @brief CPU specific implementations for the Freescale Kinetis K60 + * @brief CPU specific implementations for the NXP Kinetis K60 + * Cortex-M4 MCU * @{ * * @file @@ -21,15 +22,6 @@ #ifndef CPU_CONF_H #define CPU_CONF_H -#include "cpu_conf_common.h" - -#ifdef __cplusplus -extern "C" -{ -#endif - -#include - #if defined(CPU_MODEL_MK60DN512VLL10) || defined(CPU_MODEL_MK60DN256VLL10) #include "vendor/MK60D10.h" @@ -39,44 +31,18 @@ extern "C" #error Unknown CPU model. Update Makefile.include in the board directory. #endif +#include "cpu_conf_kinetis.h" + +#ifdef __cplusplus +extern "C" +{ +#endif + /** * @brief This CPU provides an additional ADC clock divider as CFG1[ADICLK]=1 */ #define KINETIS_HAVE_ADICLK_BUS_DIV_2 1 -/** - * @brief ARM Cortex-M specific CPU configuration - * @{ - */ -#define CPU_DEFAULT_IRQ_PRIO (1U) -#define CPU_IRQ_NUMOF (104U) -#define CPU_FLASH_BASE (0x00000000) -/** @} */ - -/** - * @name GPIO pin mux function numbers - */ -/** @{ */ -#define PIN_MUX_FUNCTION_ANALOG 0 -#define PIN_MUX_FUNCTION_GPIO 1 -/** @} */ -/** - * @name GPIO interrupt flank settings - */ -/** @{ */ -#define PIN_INTERRUPT_RISING 0b1001 -#define PIN_INTERRUPT_FALLING 0b1010 -#define PIN_INTERRUPT_EDGE 0b1011 -/** @} */ - -/** - * @name Timer hardware information - */ -/** @{ */ -#define LPTMR_CLKEN() (bit_set32(&SIM->SCGC5, SIM_SCGC5_LPTMR_SHIFT)) /**< Enable LPTMR0 clock gate */ -#define PIT_CLKEN() (bit_set32(&SIM->SCGC6, SIM_SCGC6_PIT_SHIFT)) /**< Enable PIT clock gate */ -/** @} */ - #ifdef __cplusplus } #endif diff --git a/cpu/k64f/include/cpu_conf.h b/cpu/k64f/include/cpu_conf.h index 22ce06c6b4..19ee767eca 100644 --- a/cpu/k64f/include/cpu_conf.h +++ b/cpu/k64f/include/cpu_conf.h @@ -24,52 +24,19 @@ #ifndef CPU_CONF_H #define CPU_CONF_H -#include "cpu_conf_common.h" - #ifdef CPU_MODEL_MK64FN1M0VLL12 #include "vendor/MK64F12.h" #else #error "undefined CPU_MODEL" #endif +#include "cpu_conf_kinetis.h" + #ifdef __cplusplus extern "C" { #endif -/** - * @brief ARM Cortex-M specific CPU configuration - * @{ - */ -#define CPU_DEFAULT_IRQ_PRIO (1U) -#define CPU_IRQ_NUMOF (86U) -#define CPU_FLASH_BASE (0x00000000) -/** @} */ - -/** - * @name GPIO pin mux function numbers - */ -/** @{ */ -#define PIN_MUX_FUNCTION_ANALOG 0 -#define PIN_MUX_FUNCTION_GPIO 1 -/** @} */ -/** - * @name GPIO interrupt flank settings - */ -/** @{ */ -#define PIN_INTERRUPT_RISING 0b1001 -#define PIN_INTERRUPT_FALLING 0b1010 -#define PIN_INTERRUPT_EDGE 0b1011 -/** @} */ - -/** - * @name Timer hardware information - */ -/** @{ */ -#define LPTMR_CLKEN() (bit_set32(&SIM->SCGC5, SIM_SCGC5_LPTMR_SHIFT)) /**< Enable LPTMR0 clock gate */ -#define PIT_CLKEN() (bit_set32(&SIM->SCGC6, SIM_SCGC6_PIT_SHIFT)) /**< Enable PIT clock gate */ -/** @} */ - #ifdef __cplusplus } #endif diff --git a/cpu/kinetis_common/include/cpu_conf_kinetis.h b/cpu/kinetis_common/include/cpu_conf_kinetis.h new file mode 100644 index 0000000000..f1bd12c509 --- /dev/null +++ b/cpu/kinetis_common/include/cpu_conf_kinetis.h @@ -0,0 +1,77 @@ +/* + * Copyright (C) 2017 Eistec AB + * + * This file is subject to the terms and conditions of the GNU Lesser + * General Public License v2.1. See the file LICENSE in the top level + * directory for more details. + */ + +/** + * @ingroup cpu_kinetis_common + * @{ + * + * @file + * @brief CPU specific definitions common to all Kinetis CPUs + * + * @author Joakim Nohlgård + */ + +#ifndef CPU_CONF_KINETIS_H +#define CPU_CONF_KINETIS_H + +#include "cpu_conf_common.h" + +#ifdef __cplusplus +extern "C" +{ +#endif + +/** + * @name ARM Cortex-M specific CPU configuration + * @{ + */ +#define CPU_DEFAULT_IRQ_PRIO (1U) +/* Each interrupt priority setting is 8 bits wide, for both CM4 and CM0+, but + * they are laid out differently. CM0+ concatenates the settings into 32 bit + * words, CM4 and CM7 uses direct 8 bit access */ +#define CPU_IRQ_NUMOF (sizeof(NVIC->IP)) +#define CPU_FLASH_BASE (0x00000000) +/** @} */ + +/** + * @name GPIO pin mux function numbers + * @{ + */ +#define PIN_MUX_FUNCTION_ANALOG 0 +#define PIN_MUX_FUNCTION_GPIO 1 +/** @} */ + +/** + * @name GPIO interrupt flank settings + * @{ + */ +#define PIN_INTERRUPT_RISING 0b1001 +#define PIN_INTERRUPT_FALLING 0b1010 +#define PIN_INTERRUPT_EDGE 0b1011 +/** @} */ + +/** + * @name Timer hardware information + * @{ + */ +#ifdef SIM_SCGC5_LPTMR_SHIFT +/** Enable LPTMR clock gate */ +#define LPTMR_CLKEN() (bit_set32(&SIM->SCGC5, SIM_SCGC5_LPTMR_SHIFT)) +#endif +#ifdef SIM_SCGC6_PIT_SHIFT +/** Enable PIT clock gate */ +#define PIT_CLKEN() (bit_set32(&SIM->SCGC6, SIM_SCGC6_PIT_SHIFT)) +#endif +/** @} */ + +#ifdef __cplusplus +} +#endif + +#endif /* CPU_CONF_KINETIS_H */ +/** @} */ diff --git a/cpu/kw2xd/include/cpu_conf.h b/cpu/kw2xd/include/cpu_conf.h index 25b3fc0b49..be17035c3f 100644 --- a/cpu/kw2xd/include/cpu_conf.h +++ b/cpu/kw2xd/include/cpu_conf.h @@ -25,8 +25,6 @@ #ifndef CPU_CONF_H #define CPU_CONF_H -#include "cpu_conf_common.h" - #ifdef CPU_MODEL_KW21D256 #include "vendor/MKW22D5.h" #elif CPU_MODEL_KW21D512 @@ -37,41 +35,18 @@ #error "undefined CPU_MODEL" #endif +#include "cpu_conf_kinetis.h" + #ifdef __cplusplus extern "C" { #endif -/** - * @brief ARM Cortex-M specific CPU configuration - * @{ - */ -#define CPU_DEFAULT_IRQ_PRIO (1U) -#define CPU_IRQ_NUMOF (65U) -#define CPU_FLASH_BASE (0x00000000) -/** @} */ - /** * @brief This CPU provides an additional ADC clock divider as CFG1[ADICLK]=1 */ #define KINETIS_HAVE_ADICLK_BUS_DIV_2 1 -/** - * @name GPIO pin mux function numbers - */ -/** @{ */ -#define PIN_MUX_FUNCTION_ANALOG 0 -#define PIN_MUX_FUNCTION_GPIO 1 -/** @} */ -/** - * @name GPIO interrupt flank settings - */ -/** @{ */ -#define PIN_INTERRUPT_RISING 0b1001 -#define PIN_INTERRUPT_FALLING 0b1010 -#define PIN_INTERRUPT_EDGE 0b1011 -/** @} */ - /** @name PORT module clock gates */ /** @{ */ #define PORTA_CLOCK_GATE (BITBAND_REG32(SIM->SCGC5, SIM_SCGC5_PORTA_SHIFT)) @@ -81,14 +56,6 @@ extern "C" #define PORTE_CLOCK_GATE (BITBAND_REG32(SIM->SCGC5, SIM_SCGC5_PORTE_SHIFT)) /** @} */ -/** - * @name Timer hardware information - */ -/** @{ */ -#define LPTMR_CLKEN() (bit_set32(&SIM->SCGC5, SIM_SCGC5_LPTMR_SHIFT)) /**< Enable LPTMR0 clock gate */ -#define PIT_CLKEN() (bit_set32(&SIM->SCGC6, SIM_SCGC6_PIT_SHIFT)) /**< Enable PIT clock gate */ -/** @} */ - /** * @name KW2XD SiP internal interconnects between MCU and Modem. *