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Merge pull request #14219 from btcven/2020_06_07-ccfg

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cpu/cc26xx_cc13xx: add & link CCFG configuration
This commit is contained in:
benpicco 2020-09-30 15:16:25 +02:00 committed by GitHub
commit 615561b53a
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11 changed files with 882 additions and 13 deletions
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4
cpu/cc26x0/Makefile.include
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@ -3,10 +3,8 @@ CPU_VARIANT = x0
ROM_START_ADDR ?= 0x00000000
RAM_START_ADDR ?= 0x20000000
ROM_LEN ?= 128K
ROM_LEN ?= 0x1FFA8 # 128K - 88 bytes
RAM_LEN ?= 20K
LINKER_SCRIPT ?= cortexm.ld
include ${RIOTCPU}/cc26xx_cc13xx/Makefile.include
include $(RIOTMAKE)/arch/cortexm.inc.mk

8
cpu/cc26x0/include/cpu_conf.h
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@ -21,6 +21,14 @@
#ifndef CPU_CONF_H
#define CPU_CONF_H
#ifndef SET_MODE_CONF_1_ALT_DCDC_IPEAK
#define SET_MODE_CONF_1_ALT_DCDC_IPEAK 0x2 /**< 32 mA */
#endif
#ifndef SET_MODE_CONF_XOSC_FREQ
#define SET_MODE_CONF_XOSC_FREQ 0x3 /**< 24 MHz xtal */
#endif
#include "cpu_conf_cc26xx_cc13xx.h"
#include "cc26x0_aux.h"

1
cpu/cc26x2_cc13x2/Kconfig
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@ -8,6 +8,7 @@
config CPU_FAM_CC13X2
bool
select CPU_COMMON_CC26XX_CC13XX
select CPU_FAM_CC13XX
select CPU_CORE_CORTEX_M4F
select HAS_CPU_CC26X2_CC13X2
select HAS_CORTEXM_MPU

4
cpu/cc26x2_cc13x2/Makefile.include
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@ -2,10 +2,8 @@ CPU_VARIANT = x2
ROM_START_ADDR ?= 0x00000000
RAM_START_ADDR ?= 0x20000000
ROM_LEN ?= 352K
ROM_LEN ?= 0x57FA8 # 352K - 88 config bytes
RAM_LEN ?= 80K
LINKER_SCRIPT ?= cortexm.ld
include ${RIOTCPU}/cc26xx_cc13xx/Makefile.include
include $(RIOTMAKE)/arch/cortexm.inc.mk

10
cpu/cc26x2_cc13x2/include/cpu_conf.h
View File

@ -21,7 +21,15 @@
#ifndef CPU_CONF_H
#define CPU_CONF_H
#define __FPU_PRESENT 1U /**< Presence of FPU */
#ifndef SET_MODE_CONF_1_ALT_DCDC_IPEAK
#define SET_MODE_CONF_1_ALT_DCDC_IPEAK 0x2 /**< 12 mA */
#endif
#ifndef SET_MODE_CONF_XOSC_FREQ
#define SET_MODE_CONF_XOSC_FREQ 0x2 /**< 48 MHz xtal */
#endif
#define __FPU_PRESENT 1U /**< Presence of FPU */
#include "cpu_conf_cc26xx_cc13xx.h"
#include "cc26x2_cc13x2_aux.h"

72
cpu/cc26xx_cc13xx/Kconfig
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@ -11,4 +11,76 @@ config CPU_COMMON_CC26XX_CC13XX
select HAS_PERIPH_UART
select HAS_PERIPH_UART_MODECFG
config CPU_FAM_CC13XX
bool
menuconfig CC26XX_CC13XX_UPDATE_CCFG
bool "Update CCFG"
help
This includes the CCFG configuration in the binary for flashing
onto the micro-controller.
CCFG stands for Customer Configueration, it's different from the
FCFG which is the Factory Configuration of the device.
if CC26XX_CC13XX_UPDATE_CCFG
config CC26XX_CC13XX_FORCE_VDDR_HH
bool "Force VDDR high"
depends on CPU_FAM_CC13XX
help
Force VDDR high setting, enables higher output power but also higher
power consumption.
This is also called "boost mode".
config CC26XX_CC13XX_GPRAM
bool "Enable GPRAM"
help
Enable GPRAM and use 8K VIMS RAM as GPRAM (instead of cache).
Notes:
- Enabling GPRAM disables CACHE and will reduce CPU execution speed
(up to 60%).
- GPRAM is 8KB in size and located at 0x11000000-0x11001FFF if
enabled.
menuconfig CC26XX_CC13XX_ROM_BOOTLOADER
bool "Enable ROM bootloader"
help
Enables the ROM bootloader and the bootloader backdoor to
read/write flash memory using a serial interface.
if CC26XX_CC13XX_ROM_BOOTLOADER
choice
bool "Bootloader backdoor DIO level"
default CC26XX_CC13XX_BL_LEVEL_ACTIVE_HIGH
help
This configures the level need to enter the bootloader backdoor at boot
time.
config CC26XX_CC13XX_BL_LEVEL_ACTIVE_HIGH
bool "Active high"
config CC26XX_CC13XX_BL_LEVEL_ACTIVE_LOW
bool "Active low"
endchoice
config CC26XX_CC13XX_BL_PIN_EN
bool "Enable bootloader backdoor DIO"
config CC26XX_CC13XX_BL_PIN
int "Bootloader backdoor DIO number"
range 0 31
depends on CC26XX_CC13XX_BL_PIN_EN
help
DIO (pin) number used to enter the bootloader backdoor at
boot time.
endif # CC26XX_CC13XX_ROM_BOOTLOADER
endif # CC26XX_CC13XX_UPDATE_CCFG
source "$(RIOTCPU)/cortexm_common/Kconfig"

2
cpu/cc26xx_cc13xx/Makefile.include
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@ -1,4 +1,6 @@
VARIANT = $(shell echo $(CPU_VARIANT) | tr 'a-z-' 'A-Z_')
CFLAGS += -DCPU_VARIANT_$(VARIANT)
LINKER_SCRIPT ?= $(RIOTCPU)/cc26xx_cc13xx/ldscripts/cc26xx_cc13xx.ld
INCLUDES += -I${RIOTCPU}/cc26xx_cc13xx/include

86
cpu/cc26xx_cc13xx/include/cc26xx_cc13xx_ccfg.h
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@ -54,11 +54,87 @@ typedef struct {
* @brief CCFG register values
* @{
*/
#define CCFG_MODE_CONF_1_ALT_DCDC_IPEAK_s 16
#define CCFG_MODE_CONF_VDDR_EXT_LOAD 0x02000000
#define CCFG_MODE_CONF_VDDS_BOD_LEVEL 0x01000000
#define CCFG_SIZE_AND_DIS_FLAGS_DIS_GPRAM 0x00000004
#define CCFG_SIZE_AND_DIS_FLAGS_DIS_ALT_DCDC_SETTING 0x00000002
#define CCFG_EXT_LF_CLK_DIO_m 0xFF000000
#define CCFG_EXT_LF_CLK_DIO_s 24
#define CCFG_EXT_LF_CLK_RTC_INCREMENT_m 0x00FFFFFF
#define CCFG_EXT_LF_CLK_RTC_INCREMENT_s 0
#define CCFG_MODE_CONF_1_TCXO_TYPE_m 0x80000000
#define CCFG_MODE_CONF_1_TCXO_TYPE_s 31
#define CCFG_MODE_CONF_1_TCXO_MAX_START_m 0x7F000000
#define CCFG_MODE_CONF_1_TCXO_MAX_START_s 24
#define CCFG_MODE_CONF_1_ALT_DCDC_VMIN_m 0x00F00000
#define CCFG_MODE_CONF_1_ALT_DCDC_VMIN_s 20
#define CCFG_MODE_CONF_1_ALT_DCDC_DITHER_EN_m 0x00080000
#define CCFG_MODE_CONF_1_ALT_DCDC_DITHER_EN_s 19
#define CCFG_MODE_CONF_1_ALT_DCDC_IPEAK_m 0x00070000
#define CCFG_MODE_CONF_1_ALT_DCDC_IPEAK_s 16
#define CCFG_MODE_CONF_1_DELTA_IBIAS_INIT_m 0x0000F000
#define CCFG_MODE_CONF_1_DELTA_IBIAS_INIT_s 12
#define CCFG_MODE_CONF_1_DELTA_IBIAS_OFFSET_m 0x00000F00
#define CCFG_MODE_CONF_1_DELTA_IBIAS_OFFSET_s 8
#define CCFG_MODE_CONF_1_XOSC_MAX_START_m 0x000000FF
#define CCFG_MODE_CONF_1_XOSC_MAX_START_s 0
#define CCFG_SIZE_AND_DIS_FLAGS_SIZE_OF_CCFG_m 0xFFFF0000
#define CCFG_SIZE_AND_DIS_FLAGS_SIZE_OF_CCFG_s 16
#define CCFG_SIZE_AND_DIS_FLAGS_DISABLE_FLAGS_m 0x0000FFF0
#define CCFG_SIZE_AND_DIS_FLAGS_DISABLE_FLAGS_s 4
#define CCFG_SIZE_AND_DIS_FLAGS_DIS_TCXO_m 0x00000008
#define CCFG_SIZE_AND_DIS_FLAGS_DIS_TCXO_s 3
#define CCFG_SIZE_AND_DIS_FLAGS_DIS_GPRAM_m 0x00000004
#define CCFG_SIZE_AND_DIS_FLAGS_DIS_GPRAM_s 2
#define CCFG_SIZE_AND_DIS_FLAGS_DIS_ALT_DCDC_SETTING 0x00000002
#define CCFG_SIZE_AND_DIS_FLAGS_DIS_ALT_DCDC_SETTING_m 0x00000002
#define CCFG_SIZE_AND_DIS_FLAGS_DIS_ALT_DCDC_SETTING_s 1
#define CCFG_SIZE_AND_DIS_FLAGS_DIS_XOSC_OVR_m 0x00000001
#define CCFG_SIZE_AND_DIS_FLAGS_DIS_XOSC_OVR_s 0
#define CCFG_MODE_CONF_VDDR_TRIM_SLEEP_DELTA_m 0xF0000000
#define CCFG_MODE_CONF_VDDR_TRIM_SLEEP_DELTA_s 28
#define CCFG_MODE_CONF_DCDC_RECHARGE_m 0x08000000
#define CCFG_MODE_CONF_DCDC_RECHARGE_s 27
#define CCFG_MODE_CONF_DCDC_ACTIVE_m 0x04000000
#define CCFG_MODE_CONF_DCDC_ACTIVE_s 26
#define CCFG_MODE_CONF_VDDR_EXT_LOAD 0x02000000
#define CCFG_MODE_CONF_VDDR_EXT_LOAD_m 0x02000000
#define CCFG_MODE_CONF_VDDR_EXT_LOAD_s 25
#define CCFG_MODE_CONF_VDDS_BOD_LEVEL 0x01000000
#define CCFG_MODE_CONF_VDDS_BOD_LEVEL_m 0x01000000
#define CCFG_MODE_CONF_VDDS_BOD_LEVEL_s 24
#define CCFG_MODE_CONF_SCLK_LF_OPTION_m 0x00C00000
#define CCFG_MODE_CONF_SCLK_LF_OPTION_s 22
#define CCFG_MODE_CONF_VDDR_TRIM_SLEEP_TC_m 0x00200000
#define CCFG_MODE_CONF_VDDR_TRIM_SLEEP_TC_s 21
#define CCFG_MODE_CONF_RTC_COMP_m 0x00100000
#define CCFG_MODE_CONF_RTC_COMP_s 20
#define CCFG_MODE_CONF_XOSC_FREQ_m 0x000C0000
#define CCFG_MODE_CONF_XOSC_FREQ_s 18
#define CCFG_MODE_CONF_XOSC_CAP_MOD_m 0x00020000
#define CCFG_MODE_CONF_XOSC_CAP_MOD_s 17
#define CCFG_MODE_CONF_HF_COMP_m 0x00010000
#define CCFG_MODE_CONF_HF_COMP_s 16
#define CCFG_MODE_CONF_XOSC_CAPARRAY_DELTA_m 0x0000FF00
#define CCFG_MODE_CONF_XOSC_CAPARRAY_DELTA_s 8
#define CCFG_MODE_CONF_VDDR_CAP_m 0x000000FF
#define CCFG_MODE_CONF_VDDR_CAP_s 0
#define CCFG_BL_CONFIG_BOOTLOADER_ENABLE_m 0xFF000000
#define CCFG_BL_CONFIG_BOOTLOADER_ENABLE_s 24
#define CCFG_BL_CONFIG_BL_LEVEL_m 0x00010000
#define CCFG_BL_CONFIG_BL_LEVEL_s 16
#define CCFG_BL_CONFIG_BL_PIN_NUMBER_m 0x0000FF00
#define CCFG_BL_CONFIG_BL_PIN_NUMBER_s 8
#define CCFG_BL_CONFIG_BL_ENABLE_m 0x000000FF
#define CCFG_BL_CONFIG_BL_ENABLE_s 0
#define CCFG_ERASE_CONF_CHIP_ERASE_DIS_N_m 0x00000100
#define CCFG_ERASE_CONF_CHIP_ERASE_DIS_N_s 8
#define CCFG_ERASE_CONF_BANK_ERASE_DIS_N_m 0x00000001
#define CCFG_ERASE_CONF_BANK_ERASE_DIS_N_s 0
#define CCFG_CCFG_TI_OPTIONS_TI_FA_ENABLE_m 0x000000FF
#define CCFG_CCFG_TI_OPTIONS_TI_FA_ENABLE_s 0
#define CCFG_CCFG_TAP_DAP_0_CPU_DAP_ENABLE_m 0x00FF0000
#define CCFG_CCFG_TAP_DAP_0_CPU_DAP_ENABLE_s 16
#define CCFG_CCFG_TAP_DAP_0_PWRPROF_TAP_ENABLE_m 0x0000FF00
#define CCFG_CCFG_TAP_DAP_0_PWRPROF_TAP_ENABLE_s 8
#define CCFG_CCFG_TAP_DAP_0_TEST_TAP_ENABLE_m 0x000000FF
#define CCFG_CCFG_TAP_DAP_0_TEST_TAP_ENABLE_s 0
/** @} */
/**

483
cpu/cc26xx_cc13xx/include/cpu_conf_cc26xx_cc13xx.h
View File

@ -1,5 +1,6 @@
/*
* Copyright (C) 2016 Leon George
* Copyright (C) 2020 Locha Inc
*
* This file is subject to the terms and conditions of the GNU Lesser
* General Public License v2.1. See the file LICENSE in the top level
@ -14,12 +15,14 @@
* @brief Implementation specific CPU configuration options
*
* @author Leon M. George <leon@georgemail.eu>
*
* @author Jean Pierre Dudey <jeandudey@hotmail.com>
*/
#ifndef CPU_CONF_CC26XX_CC13XX_H
#define CPU_CONF_CC26XX_CC13XX_H
#include "kernel_defines.h"
#include "cpu_conf_common.h"
#include "cc26xx_cc13xx.h"
@ -49,6 +52,484 @@ extern "C" {
#define CPU_FLASH_BASE FLASH_BASE
/** @} */
/**
* @brief CC26xx/CC13xx specific CPU configuration
* @{
*/
/**
* @brief This includes the CCFG configuration in the binary for flashing
* onto the micro-controller.
*/
#ifndef CONFIG_CC26XX_CC13XX_UPDATE_CCFG
#define CONFIG_CC26XX_CC13XX_UPDATE_CCFG 0
#endif
/**
* @brief Force VDDR high setting, enables higher output power but also higher
* power consumption.
*
* This is also called "boost mode".
*/
#ifndef CONFIG_CC26XX_CC13XX_FORCE_VDDR_HH
#define CONFIG_CC26XX_CC13XX_FORCE_VDDR_HH 0
#endif
/**
* @brief Enable GPRAM and use 8K VIMS RAM as GPRAM (instead of cache).
*
* @note Enabling GPRAM disables CACHE and will reduce CPU execution speed
(up to 60%).
* @note GPRAM is 8KB in size and located at 0x11000000-0x11001FFF if
* enabled.
*/
#ifndef CONFIG_CC26XX_CC13XX_GPRAM
#define CONFIG_CC26XX_CC13XX_GPRAM 0
#endif
/**
* @brief This configures the level need to enter the bootloader backdoor at
* boot time.
*/
#if IS_ACTIVE(CONFIG_CC26XX_CC13XX_BL_LEVEL_ACTIVE_HIGH)
#define CONFIG_CC26XX_CC13XX_BL_LEVEL 0x1
#elif IS_ACTIVE(CONFIG_CC26XX_CC13XX_BL_LEVEL_ACTIVE_LOW)
#define CONFIG_CC26XX_CC13XX_BL_LEVEL 0x0
#endif
#ifndef CONFIG_CC26XX_CC13XX_BL_LEVEL
#define CONFIG_CC26XX_CC13XX_BL_LEVEL 0x1
#endif
/**
* @brief DIO (pin) number used to enter the bootloader backdoor at
* boot time.
*/
#ifndef CONFIG_CC26XX_CC13XX_BL_PIN
#define CONFIG_CC26XX_CC13XX_BL_PIN 0xFF
#endif
/* high VDDR is available only on CC13xx CPUs */
#if IS_ACTIVE(CONFIG_CPU_FAM_CC13XX)
#if IS_ACTIVE(CONFIG_CC26XX_CC13XX_FORCE_VDDR_HH)
#define SET_MODE_CONF_1_ALT_DCDC_VMIN 0xC /**< 2.5V */
#define SET_MODE_CONF_VDDR_EXT_LOAD 0x1 /**< Special setting */
#endif
#endif /* IS_ACTIVE(CONFIG_CPU_FAM_CC13XX) */
#if !IS_ACTIVE(CONFIG_CC26XX_CC13XX_GPRAM)
#define SET_SIZE_AND_DIS_FLAGS_DIS_GPRAM 0x1 /**< Disable GPRAM */
#endif
#if IS_ACTIVE(CONFIG_CC26XX_CC13XX_ROM_BOOTLOADER)
#define SET_BL_CONFIG_BOOTLOADER_ENABLE 0xC5 /**< Enable */
#define SET_BL_CONFIG_BL_ENABLE 0xC5 /**< Enable */
#if defined(CONFIG_CC26XX_CC13XX_BL_LEVEL)
#define SET_BL_CONFIG_BL_LEVEL CONFIG_CC26XX_CC13XX_BL_LEVEL
#endif
#if IS_ACTIVE(CONFIG_CC26XX_CC13XX_BL_PIN_EN)
#define SET_BL_CONFIG_BL_PIN_NUMBER CONFIG_CC26XX_CC13XX_BL_PIN
#endif
#endif /* IS_USED(CONFIG_CC26XX_CC13XX_ROM_BOOTLOADER) */
/* when GPRAM is not disabled, use it as a backup RAM */
#if IS_ACTIVE(CONFIG_CC26XX_CC13XX_DIS_GPRAM)
#define NUM_HEAPS (1)
#else
#define NUM_HEAPS (2)
#endif
/** @} */
/**
* @brief Customer Configuration (CCFG)
* @{
*/
/**
* @brief Selects the DIO to supply external 32kHz clock as SCLK_LF when
* @ref SET_MODE_CONF_SCLK_LF_OPTION is set to "external LF". The
*/
#ifndef SET_EXT_LF_CLK_DIO
#define SET_EXT_LF_CLK_DIO 0x01
#endif
/**
* @brief The input frequency of the external clock and is written to
* `AON_RTC:SUBSECINC.VALUEINC`.
*
* Defined as follows:
*
* `EXT_LF_CLK.RTC_INCREMENT = 2^38/InputClockFrequency in Hertz`
*
* For exmaple:
*
* `RTC_INCREMENT=0x800000` for `InputClockFrequency=32768 Hz`
*/
#ifndef SET_EXT_LF_CLK_RTC_INCREMENT
#define SET_EXT_LF_CLK_RTC_INCREMENT 0x800000
#endif
#if defined(CPU_VARIANT_X2) || defined(DOXYGEN)
/**
* @brief Selects the TCXO type.
* @details 0h = CMOS type. Internal common-mode bias will not be enabled.
* 1h = Clipped-sine type. Internal common-mode bias will be enabled
* when TCXO is used.
*
* @note x2 CPUs only.
*
* @note Value is only valid if @ref SET_MODE_CONF_XOSC_FREQ is equal to 0.
*/
#ifndef SET_MODE_CONF_1_TCXO_TYPE
#define SET_MODE_CONF_1_TCXO_TYPE 0x01
#endif
/**
* @brief Maximum TCXO startup time in units of 100us.
*
* @note x2 CPUs only.
*
* @note Value is only valid if @ref SET_MODE_CONF_XOSC_FREQ is equal to 0.
*/
#ifndef SET_MODE_CONF_1_TCXO_MAX_START
#define SET_MODE_CONF_1_TCXO_MAX_START 0x7F
#endif
#endif /* defined(CPU_VARIANT_X2) || defined(DOXYGEN) */
/**
* @brief Minimum voltage for when DC/DC should be used if alternate DC/DC
* setting is enabled.
*
* The VMIN voltage is defnied as follows:
*
* `Voltage = (28 + ALT_DCDC_VMIN) / 16`
*
* For example:
*
* 0 = 1.75 V
* 1 = 1.8125 V
* ...
* 8 = 2.25 V
* ...
* 14 = 2.625 V
* 15 = 2.6875 V
*/
#ifndef SET_MODE_CONF_1_ALT_DCDC_VMIN
#define SET_MODE_CONF_1_ALT_DCDC_VMIN 0x8
#endif
/**
* @brief Enable DC/DC dithering if alternate DC/DC setting is enabled.
* @details 0h = Dither disable
* 1h = Dither enable
*/
#ifndef SET_MODE_CONF_1_ALT_DCDC_DITHER_EN
#define SET_MODE_CONF_1_ALT_DCDC_DITHER_EN 0x0
#endif
/**
* @brief Inductor peak current if alternate DC/DC setting is enabled.
*
* @note Assuming 10uH external inductor!
*
* @note Values changes between x2 and x0 CPUs.
*/
#ifndef SET_MODE_CONF_1_ALT_DCDC_IPEAK
#define SET_MODE_CONF_1_ALT_DCDC_IPEAK 0x0
#endif
/**
* @brief Signed delta value for IBIAS_INIT.
*/
#ifndef SET_MODE_CONF_1_DELTA_IBIAS_INIT
#define SET_MODE_CONF_1_DELTA_IBIAS_INIT 0x0
#endif
/**
* @brief Signed delta value for IBIAS_OFFSET.
*/
#ifndef SET_MODE_CONF_1_DELTA_IBIAS_OFFSET
#define SET_MODE_CONF_1_DELTA_IBIAS_OFFSET 0x0
#endif
/**
* @brief Maximum XOSC startup time (worst case) in units of 100us.
*/
#ifndef SET_MODE_CONF_1_XOSC_MAX_START
#define SET_MODE_CONF_1_XOSC_MAX_START 0x10
#endif
/**
* @brief Total size of the CCFG in bytes
*/
#ifndef SET_SIZE_AND_DIS_FLAGS_SIZE_OF_CCFG
#define SET_SIZE_AND_DIS_FLAGS_SIZE_OF_CCFG 0x0058
#endif
/**
* @brief Reserved by Texas Instruments for future use.
*/
#ifndef SET_SIZE_AND_DIS_FLAGS_DISABLE_FLAGS
#define SET_SIZE_AND_DIS_FLAGS_DISABLE_FLAGS \
(CCFG_SIZE_AND_DIS_FLAGS_DISABLE_FLAGS_m >> \
CCFG_SIZE_AND_DIS_FLAGS_DISABLE_FLAGS_s)
#endif
/**
* @brief Disable TCXO.
* @details 0h = TCXO functionality enabled.
* 1h = TCXO functionality disabled.
*/
#ifndef SET_SIZE_AND_DIS_FLAGS_DIS_TCXO
#define SET_SIZE_AND_DIS_FLAGS_DIS_TCXO 0x1
#endif
/**
* @brief Disable GPRAM (or use the 8K VIMS RAM as CACHE RAM).
* @details 0h = GPRAM is enabled and hence CACHE disabled.
* 1h = GPRAM is disabled and instead CACHE is enabled (default).
*
* @note Disabling CACHE will reduce CPU execution speed (up to 60%).
* @note GPRAM is 8 K-bytes in size and located at 0x11000000-0x11001FFF if
*/
#ifndef SET_SIZE_AND_DIS_FLAGS_DIS_GPRAM
#define SET_SIZE_AND_DIS_FLAGS_DIS_GPRAM 0x0
#endif
/**
* @brief Disable alternate DC/DC settings.
* @details 0h = Enable alternate DC/DC settings.
* 1h = Disable alternate DC/DC settings.
*
* @see @ref SET_MODE_CONF_1_ALT_DCDC_VMIN
* @see @ref SET_MODE_CONF_1_ALT_DCDC_DITHER_EN
* @see @ref SET_MODE_CONF_1_ALT_DCDC_IPEAK
*/
#ifndef SET_SIZE_AND_DIS_FLAGS_DIS_ALT_DCDC_SETTING
#define SET_SIZE_AND_DIS_FLAGS_DIS_ALT_DCDC_SETTING 0x0
#endif
/**
* @brief Disable XOSC override functionality.
* @details 0h = Enable XOSC override functionality.
* 1h = Disable XOSC override functionality.
*
* @see @ref SET_MODE_CONF_1_DELTA_IBIAS_INIT
* @see @ref SET_MODE_CONF_1_DELTA_IBIAS_OFFSET
* @see @ref SET_MODE_CONF_1_XOSC_MAX_START
*/
#ifndef SET_SIZE_AND_DIS_FLAGS_DIS_XOSC_OVR
#define SET_SIZE_AND_DIS_FLAGS_DIS_XOSC_OVR 0x1
#endif
/**
* @brief Signed delta value to apply to the VDDR_TRIM_SLEEP target, minus one.
*
* 0x8 (-8) : Delta = -7
* ...
* 0xF (-1) : Delta = 0
* 0x0 (0) : Delta = +1
* ...
* 0x7 (7) : Delta = +8
*/
#ifndef SET_MODE_CONF_VDDR_TRIM_SLEEP_DELTA
#define SET_MODE_CONF_VDDR_TRIM_SLEEP_DELTA 0xF
#endif
/**
* @brief DC/DC during recharge in powerdown.
* @details 0h = Use the DC/DC during recharge in powerdown.
* 1h = Do not use the DC/DC during recharge in powerdown (default).
*/
#ifndef SET_MODE_CONF_DCDC_RECHARGE
#define SET_MODE_CONF_DCDC_RECHARGE 0x0
#endif
/**
* @brief DC/DC in active mode.
* @details 0h = Use the DC/DC during active mode.
* 1h = Do not use the DC/DC during active mode (default).
*/
#ifndef SET_MODE_CONF_DCDC_ACTIVE
#define SET_MODE_CONF_DCDC_ACTIVE 0x0
#endif
/**
* @brief Reserved for future use byte TI. However it's used to
* enable VDDR_HH setting, with an "special value".
*/
#ifndef SET_MODE_CONF_VDDR_EXT_LOAD
#define SET_MODE_CONF_VDDR_EXT_LOAD 0x0
#endif
/**
* @brief VDDS BOD level.
* @details 0h = VDDS BOD level is 2.0V (necessary for external load mode, or
* for maximum PA output power on CC13xx).
* 1h = VDDS BOD level is 1.8V (or 1.65V for external regulator mode)
* (default).
*/
#ifndef SET_MODE_CONF_VDDS_BOD_LEVEL
#define SET_MODE_CONF_VDDS_BOD_LEVEL 0x1
#endif
/**
* @brief LF clock option
* @details 0h = LF clock derived from HF clock. Note: using this configuration
* will block the device from entering Standby mode.
* 1h = External LF clock.
* 2h = LF XOSC.
* 3h = LF RCOSC.
*/
#ifndef SET_MODE_CONF_SCLK_LF_OPTION
#define SET_MODE_CONF_SCLK_LF_OPTION 0x2
#endif
/**
* @brief VDDR_TRIM_SLEEP_DELTA temperature compensation.
* @details 1h = VDDR_TRIM_SLEEP_DELTA is not temperature compensated.
* 0h = RTOS/driver temperature compensates VDDR_TRIM_SLEEP_DELTA
* every time standby mode is entered. This improves
* low-temperature RCOSC_LF frequency stability in standby mode.
*
* When temperature compensation is performed, the delta is calculates this way:
*
* Delta = max (delta, min(8, floor(62-temp)/8))
*
* Here, delta is given by VDDR_TRIM_SLEEP_DELTA, and temp is the current
* temperature in degrees C.
*/
#ifndef SET_MODE_CONF_VDDR_TRIM_SLEEP_TC
#define SET_MODE_CONF_VDDR_TRIM_SLEEP_TC 0x1
#endif
/**
* @brief Reserved for future use by TI.
*/
#ifndef SET_MODE_CONF_RTC_COMP
#define SET_MODE_CONF_RTC_COMP 0x1
#endif
/**
* @brief External crystal frequency.
* @details 1h = HPOSC
* 2h = 48 MHz
* 3h = 24 MHz
*
* On x2 chips 48 MHz is the default, on x0 chips it's 24 MHz
*/
#ifndef SET_MODE_CONF_XOSC_FREQ
#define SET_MODE_CONF_XOSC_FREQ 0x2
#endif
/**
* @brief Enable modification (delta) to XOSC cap-array. Value specified in
* XOSC_CAPARRAY_DELTA.
* @details 0h = Apply cap-array delta.
* 1h = Do not apply cap-array delta (default).
*/
#ifndef SET_MODE_CONF_XOSC_CAP_MOD
#define SET_MODE_CONF_XOSC_CAP_MOD 0x1
#endif
/**
* @brief Reserved for future use by TI.
*/
#ifndef SET_MODE_CONF_HF_COMP
#define SET_MODE_CONF_HF_COMP 0x1
#endif
/**
* @brief Modifies trimmed XOSC cap-array step value.
*
* Enabled by @ref SET_MODE_CONF_XOSC_CAP_MOD.
*/
#ifndef SET_MODE_CONF_XOSC_CAPARRAY_DELTA
#define SET_MODE_CONF_XOSC_CAPARRAY_DELTA 0xFF
#endif
/**
* @brief Represents the minimum decoupling capacitance (worst case) on VDDR,
* in units of 100nF.
*
* This should take into account capacitor tolerance and voltage dependent
* capacitance variation. This bit affects the recharge period calculation when
* going into powerdown or standby.
*/
#ifndef SET_MODE_CONF_VDDR_CAP
#define SET_MODE_CONF_VDDR_CAP 0x3A
#endif
/**
* @brief Bootloader enable. Boot loader can be accessed if
* IMAGE_VALID_CONF.IMAGE_VALID is non-zero or BL_ENABLE is enabled
* (and conditions for boot loader backdoor are met).
* @details C5h = Boot loader is enabled.
* Any other value = Boot loader is disabled.
*/
#ifndef SET_BL_CONFIG_BOOTLOADER_ENABLE
#define SET_BL_CONFIG_BOOTLOADER_ENABLE 0x00
#endif
/**
* @brief Sets the active level of the selected DIO number BL_PIN_NUMBER if
* boot loader backdoor is enabled by the BL_ENABLE field.
* @details 0h = Active low.
* 1h = Active high.
*/
#ifndef SET_BL_CONFIG_BL_LEVEL
#define SET_BL_CONFIG_BL_LEVEL 0x1
#endif
/**
* @brief DIO number that is level checked if the boot loader backdoor is
* enabled by the @ref SET_BL_CONFIG_BL_ENABLE setting.
*/
#ifndef SET_BL_CONFIG_BL_PIN_NUMBER
#define SET_BL_CONFIG_BL_PIN_NUMBER 0xFF
#endif
/**
* @brief Enables the boot loader backdoor.
* @details C5h = Boot loader backdoor is enabled.
* Any other value = Boot loader backdoor is disabled.
*/
#ifndef SET_BL_CONFIG_BL_ENABLE
#define SET_BL_CONFIG_BL_ENABLE 0xFF
#endif
/**
* @brief Enable CPU DAP.
* @details C5h = Main CPU DAP access is enabled.
* Any other value = Main CPU DAP access will remain disabled.
*/
#ifndef SET_CCFG_TAP_DAP_0_CPU_DAP_ENABLE
#define SET_CCFG_TAP_DAP_0_CPU_DAP_ENABLE 0xC5
#endif
/**
* @brief Enable PWRPROF TAP (PRCM on x0 CPUs).
* @details C5h = PWRPROF TAP access is enabled.
* Any other value = PWRPROF TAP access will remain disabled.
*/
#ifndef SET_CCFG_TAP_DAP_0_PWRPROF_TAP_ENABLE
#define SET_CCFG_TAP_DAP_0_PWRPROF_TAP_ENABLE 0xC5
#endif
/**
* @brief Enable Test TAP.
* @details C5h = TEST TAP access is enabled.
* Any other value = TEST TAP access will remain disabled.
*/
#ifndef SET_CCFG_TAP_DAP_0_TEST_TAP_ENABLE
#define SET_CCFG_TAP_DAP_0_TEST_TAP_ENABLE 0x00
#endif
/** @} */
#ifdef __cplusplus
}
#endif

53
cpu/cc26xx_cc13xx/ldscripts/cc26xx_cc13xx.ld Normal file
View File

@ -0,0 +1,53 @@
/*
* Copyright (C) 2020 Locha Inc
*
* This file is subject to the terms and conditions of the GNU Lesser
* General Public License v2.1. See the file LICENSE in the top level
* directory for more details.
*/
/**
* @addtogroup cpu_cc26x2_cc13x2
* @{
*
* @file
* @brief Linker script for the CC26x2/CC13x2 MCUs
*
* @author Jean Pierre Dudey <jeandudey@hotmail.com>
*/
INCLUDE cortexm_rom_offset.ld
/* Memory Space Definitions: */
MEMORY
{
rom (rx) : ORIGIN = _rom_start_addr + _rom_offset, LENGTH = _fw_rom_length
ccfg (rx) : ORIGIN = 0x00057FA8, LENGTH = 88
/* GPRAM is only available when cache is disabled. When GPRAM is enabled it
* is used as a backup RAM at the expense of slower CPU execution time */
gpram : ORIGIN = 0x11000000, LENGTH = 8K
ram (w!rx) : ORIGIN = _ram_start_addr, LENGTH = _ram_length
}
/* MCU Sepcific Section Definitions */
SECTIONS
{
.ccfg :
{
KEEP(*(.ccfg))
} > ccfg
.gpram :
{
} > gpram
.heap_gpram (NOLOAD) : ALIGN(4)
{
_sheap1 = . ;
_eheap1 = ORIGIN(gpram) + LENGTH(gpram);
} > gpram
}
INCLUDE cortexm_base.ld
/* @} */

172
cpu/cc26xx_cc13xx/vectors.c
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@ -1,5 +1,6 @@
/*
* Copyright (C) 2016 Leon George
* Copyright (C) 2020 Locha Inc
*
* This file is subject to the terms and conditions of the GNU Lesser
* General Public License v2.1. See the file LICENSE in the top level
@ -15,6 +16,7 @@
*
* @author Leon M. George <leon@georgemail.eu>
* @author Anton Gerasimov <tossel@gmail.com>
* @author Jean Pierre Dudey <jeandudey@hotmail.com>
*/
#include <stdint.h>
@ -114,4 +116,174 @@ ISR_VECTOR(1) const isr_t vector_cpu[] = {
#endif // CPU_VARIANT_X2
};
#if IS_USED(CONFIG_CC26XX_CC13XX_UPDATE_CCFG)
/**
* @brief Set the bits of a CCFG bit field.
*
* Allows safe concatenation of values and protects with the mask
* from setting unwanted bits.
*
* Example:
*
* ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ {.c}
* uint32_t value = CCFG_SET_BITS(0xCA, 24, 0xFF000000)
& CCFG_SET_BITS(0xFE, 16, 0x00FF0000);
* ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
*
* @param value The bit value to set.
* @param shift_amount The (to left) shift amount.
* @param mask The bit mask.
*/
#define CCFG_SET_BITS(value, shift_amount, mask) \
(((uint32_t)(value)) << (shift_amount) | ~(mask))
extern cortexm_base_t cortex_vector_base;
__attribute__((section(".ccfg"), used))
ccfg_regs_t cc26xx_cc13xx_ccfg = {
/* external LF clock configuration */
.EXT_LF_CLK = CCFG_SET_BITS(SET_EXT_LF_CLK_DIO,
CCFG_EXT_LF_CLK_DIO_s,
CCFG_EXT_LF_CLK_DIO_m)
& CCFG_SET_BITS(SET_EXT_LF_CLK_RTC_INCREMENT,
CCFG_EXT_LF_CLK_RTC_INCREMENT_s,
CCFG_EXT_LF_CLK_RTC_INCREMENT_m),
/* misc */
.MODE_CONF_1 =
#ifdef CPU_VARIANT_X2
/* only x2 CPUs allow TCXO settings */
CCFG_SET_BITS(SET_MODE_CONF_1_TCXO_TYPE,
CCFG_MODE_CONF_1_TCXO_TYPE_s,
CCFG_MODE_CONF_1_TCXO_TYPE_m)
& CCFG_SET_BITS(SET_MODE_CONF_1_TCXO_MAX_START,
CCFG_MODE_CONF_1_TCXO_MAX_START_s,
CCFG_MODE_CONF_1_TCXO_MAX_START_m)
#else
0
#endif /* CPU_VARIANT_X2 */
& CCFG_SET_BITS(SET_MODE_CONF_1_ALT_DCDC_VMIN,
CCFG_MODE_CONF_1_ALT_DCDC_VMIN_s,
CCFG_MODE_CONF_1_ALT_DCDC_VMIN_m)
& CCFG_SET_BITS(SET_MODE_CONF_1_ALT_DCDC_DITHER_EN,
CCFG_MODE_CONF_1_ALT_DCDC_DITHER_EN_s,
CCFG_MODE_CONF_1_ALT_DCDC_DITHER_EN_m)
& CCFG_SET_BITS(SET_MODE_CONF_1_ALT_DCDC_IPEAK,
CCFG_MODE_CONF_1_ALT_DCDC_IPEAK_s,
CCFG_MODE_CONF_1_ALT_DCDC_IPEAK_m)
& CCFG_SET_BITS(SET_MODE_CONF_1_DELTA_IBIAS_INIT,
CCFG_MODE_CONF_1_DELTA_IBIAS_INIT_s,
CCFG_MODE_CONF_1_DELTA_IBIAS_INIT_m)
& CCFG_SET_BITS(SET_MODE_CONF_1_DELTA_IBIAS_OFFSET,
CCFG_MODE_CONF_1_DELTA_IBIAS_OFFSET_s,
CCFG_MODE_CONF_1_DELTA_IBIAS_OFFSET_m)
& CCFG_SET_BITS(SET_MODE_CONF_1_XOSC_MAX_START,
CCFG_MODE_CONF_1_XOSC_MAX_START_s,
CCFG_MODE_CONF_1_XOSC_MAX_START_m),
/* misc */
.SIZE_AND_DIS_FLAGS = CCFG_SET_BITS(SET_SIZE_AND_DIS_FLAGS_SIZE_OF_CCFG,
CCFG_SIZE_AND_DIS_FLAGS_SIZE_OF_CCFG_s,
CCFG_SIZE_AND_DIS_FLAGS_SIZE_OF_CCFG_m)
& CCFG_SET_BITS(SET_SIZE_AND_DIS_FLAGS_DISABLE_FLAGS,
CCFG_SIZE_AND_DIS_FLAGS_DISABLE_FLAGS_s,
CCFG_SIZE_AND_DIS_FLAGS_DISABLE_FLAGS_m)
& CCFG_SET_BITS(SET_SIZE_AND_DIS_FLAGS_DIS_TCXO,
CCFG_SIZE_AND_DIS_FLAGS_DIS_TCXO_s,
CCFG_SIZE_AND_DIS_FLAGS_DIS_TCXO_m)
& CCFG_SET_BITS(SET_SIZE_AND_DIS_FLAGS_DIS_GPRAM,
CCFG_SIZE_AND_DIS_FLAGS_DIS_GPRAM_s,
CCFG_SIZE_AND_DIS_FLAGS_DIS_GPRAM_m)
& CCFG_SET_BITS(SET_SIZE_AND_DIS_FLAGS_DIS_ALT_DCDC_SETTING,
CCFG_SIZE_AND_DIS_FLAGS_DIS_ALT_DCDC_SETTING_s,
CCFG_SIZE_AND_DIS_FLAGS_DIS_ALT_DCDC_SETTING_m)
& CCFG_SET_BITS(SET_SIZE_AND_DIS_FLAGS_DIS_XOSC_OVR,
CCFG_SIZE_AND_DIS_FLAGS_DIS_XOSC_OVR_s,
CCFG_SIZE_AND_DIS_FLAGS_DIS_XOSC_OVR_m),
/* misc */
.MODE_CONF = CCFG_SET_BITS(SET_MODE_CONF_VDDR_TRIM_SLEEP_DELTA,
CCFG_MODE_CONF_VDDR_TRIM_SLEEP_DELTA_s,
CCFG_MODE_CONF_VDDR_TRIM_SLEEP_DELTA_m)
& CCFG_SET_BITS(SET_MODE_CONF_DCDC_RECHARGE,
CCFG_MODE_CONF_DCDC_RECHARGE_s,
CCFG_MODE_CONF_DCDC_RECHARGE_m)
& CCFG_SET_BITS(SET_MODE_CONF_DCDC_ACTIVE,
CCFG_MODE_CONF_DCDC_ACTIVE_s,
CCFG_MODE_CONF_DCDC_ACTIVE_m)
& CCFG_SET_BITS(SET_MODE_CONF_VDDR_EXT_LOAD,
CCFG_MODE_CONF_VDDR_EXT_LOAD_s,
CCFG_MODE_CONF_VDDR_EXT_LOAD_m)
& CCFG_SET_BITS(SET_MODE_CONF_VDDS_BOD_LEVEL,
CCFG_MODE_CONF_VDDS_BOD_LEVEL_s,
CCFG_MODE_CONF_VDDS_BOD_LEVEL_m)
& CCFG_SET_BITS(SET_MODE_CONF_SCLK_LF_OPTION,
CCFG_MODE_CONF_SCLK_LF_OPTION_s,
CCFG_MODE_CONF_SCLK_LF_OPTION_m)
& CCFG_SET_BITS(SET_MODE_CONF_VDDR_TRIM_SLEEP_TC,
CCFG_MODE_CONF_VDDR_TRIM_SLEEP_TC_s,
CCFG_MODE_CONF_VDDR_TRIM_SLEEP_TC_m)
& CCFG_SET_BITS(SET_MODE_CONF_RTC_COMP,
CCFG_MODE_CONF_RTC_COMP_s,
CCFG_MODE_CONF_RTC_COMP_m)
& CCFG_SET_BITS(SET_MODE_CONF_XOSC_FREQ,
CCFG_MODE_CONF_XOSC_FREQ_s,
CCFG_MODE_CONF_RTC_COMP_m)
& CCFG_SET_BITS(SET_MODE_CONF_XOSC_CAP_MOD,
CCFG_MODE_CONF_XOSC_CAP_MOD_s,
CCFG_MODE_CONF_XOSC_CAP_MOD_m)
& CCFG_SET_BITS(SET_MODE_CONF_HF_COMP,
CCFG_MODE_CONF_HF_COMP_s,
CCFG_MODE_CONF_HF_COMP_m)
& CCFG_SET_BITS(SET_MODE_CONF_XOSC_CAPARRAY_DELTA,
CCFG_MODE_CONF_XOSC_CAPARRAY_DELTA_s,
CCFG_MODE_CONF_XOSC_CAPARRAY_DELTA_m)
& CCFG_SET_BITS(SET_MODE_CONF_VDDR_CAP,
CCFG_MODE_CONF_VDDR_CAP_s,
CCFG_MODE_CONF_VDDR_CAP_m),
/* reserved for "future use" by Texas Instruments */
.VOLT_LOAD_0 = 0xFFFFFFFF,
.VOLT_LOAD_1 = 0xFFFFFFFF,
.RTC_OFFSET = 0xFFFFFFFF,
.FREQ_OFFSET = 0xFFFFFFFF,
/* IEEE 802.15.4g MAC address */
.IEEE_MAC_0 = 0xFFFFFFFF,
.IEEE_MAC_1 = 0xFFFFFFFF,
/* BLE MAC address */
.IEEE_BLE_0 = 0xFFFFFFFF,
.IEEE_BLE_1 = 0xFFFFFFFF,
/* bootloader */
.BL_CONFIG = CCFG_SET_BITS(SET_BL_CONFIG_BOOTLOADER_ENABLE,
CCFG_BL_CONFIG_BOOTLOADER_ENABLE_s,
CCFG_BL_CONFIG_BOOTLOADER_ENABLE_m)
& CCFG_SET_BITS(SET_BL_CONFIG_BL_LEVEL,
CCFG_BL_CONFIG_BL_LEVEL_s,
CCFG_BL_CONFIG_BL_LEVEL_m)
& CCFG_SET_BITS(SET_BL_CONFIG_BL_PIN_NUMBER,
CCFG_BL_CONFIG_BL_PIN_NUMBER_s,
CCFG_BL_CONFIG_BL_PIN_NUMBER_m)
& CCFG_SET_BITS(SET_BL_CONFIG_BL_ENABLE,
CCFG_BL_CONFIG_BL_ENABLE_s,
CCFG_BL_CONFIG_BL_ENABLE_m),
.ERASE_CONF = 0,
/* debugging */
.CCFG_TI_OPTIONS = 0,
.CCFG_TAP_DAP_0 = CCFG_SET_BITS(SET_CCFG_TAP_DAP_0_CPU_DAP_ENABLE,
CCFG_CCFG_TAP_DAP_0_CPU_DAP_ENABLE_s,
CCFG_CCFG_TAP_DAP_0_CPU_DAP_ENABLE_m)
& CCFG_SET_BITS(SET_CCFG_TAP_DAP_0_PWRPROF_TAP_ENABLE,
CCFG_CCFG_TAP_DAP_0_PWRPROF_TAP_ENABLE_s,
CCFG_CCFG_TAP_DAP_0_PWRPROF_TAP_ENABLE_m)
& CCFG_SET_BITS(SET_CCFG_TAP_DAP_0_TEST_TAP_ENABLE,
CCFG_CCFG_TAP_DAP_0_TEST_TAP_ENABLE_s,
CCFG_CCFG_TAP_DAP_0_TEST_TAP_ENABLE_m),
/* PBIST2, PBIST1 and AON disabled by default */
.CCFG_TAP_DAP_1 = 0,
/* flash image vector table */
.IMAGE_VALID_CONF = (reg32_t)&cortex_vector_base,
/* flash sector write protections */
.CCFG_PROT_31_0 = 0xFFFFFFFF,
.CCFG_PROT_63_32 = 0xFFFFFFFF,
.CCFG_PROT_95_64 = 0xFFFFFFFF,
.CCFG_PROT_127_96 = 0xFFFFFFFF,
};
#endif /* IS_USED(CONFIG_CC26XX_CC13XX_UPDATE_CCFG) */
/** @} */