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cpu/stm32/periph_adc: fix CKMODE setting for L4

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Setting the `ADC_CCR_CKMODE` did only work for the reset state. It is now cleared before it is set. Instead of using the `ADC_CCR_CKMODE_x` bits to set the mode, the mode defines are used.
This commit is contained in:
Gunar Schorcht 2023-05-15 14:23:48 +02:00
parent af8a87ad99
commit 6247b2aea4
1 changed files with 7 additions and 4 deletions
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11
cpu/stm32/periph/adc_l4.c
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@ -64,6 +64,9 @@
This specifies the first channel that goes to SMPR2 instead of SMPR1. */
#define ADC_SMPR2_FIRST_CHAN (10)
#define ADC_CCR_CKMODE_HCLK_1 (ADC_CCR_CKMODE_0)
#define ADC_CCR_CKMODE_HCLK_2 (ADC_CCR_CKMODE_1)
/**
* @brief Default VBAT undefined value
*/
@ -140,14 +143,14 @@ int adc_init(adc_t line)
/* set prescaler to 0 to let the ADC run with maximum speed */
ADC->CCR &= ~(ADC_CCR_PRESC);
/* Setting ADC clock to HCLK/1 is only allowed if AHB clock prescaler is 1*/
ADC->CCR &= ~(ADC_CCR_CKMODE);
if (!(RCC->CFGR & RCC_CFGR_HPRE_3)) {
/* set ADC clock to HCLK/1 */
ADC->CCR |= (ADC_CCR_CKMODE_0);
/* set ADC clock to HCLK/1, only allowed if AHB clock prescaler is 1 */
ADC->CCR |= ADC_CCR_CKMODE_HCLK_1 << ADC_CCR_CKMODE_Pos;
}
else {
/* set ADC clock to HCLK/2 otherwise */
ADC->CCR |= (ADC_CCR_CKMODE_1);
ADC->CCR |= ADC_CCR_CKMODE_HCLK_2 << ADC_CCR_CKMODE_Pos;
}
/* configure the pin */