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cpu/sam3: changed timer vendor header

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- made channel cc registers accessible as array
This commit is contained in:
Hauke Petersen 2016-02-24 18:35:11 +01:00
parent 94c287c4c2
commit 6b9088aa11
1 changed files with 1 additions and 3 deletions
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4
cpu/sam3/include/sam3x8e/component/component_tc.h
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@ -49,9 +49,7 @@ typedef struct {
RwReg TC_SMMR; /**< \brief (TcChannel Offset: 0x8) Stepper Motor Mode Register */
RoReg Reserved1[1];
RwReg TC_CV; /**< \brief (TcChannel Offset: 0x10) Counter Value */
RwReg TC_RA; /**< \brief (TcChannel Offset: 0x14) Register A */
RwReg TC_RB; /**< \brief (TcChannel Offset: 0x18) Register B */
RwReg TC_RC; /**< \brief (TcChannel Offset: 0x1C) Register C */
RwReg TC_R[3]; /**< \brief (TcChannel Offset: 0x14) Register A-C */
RwReg TC_SR; /**< \brief (TcChannel Offset: 0x20) Status Register */
RwReg TC_IER; /**< \brief (TcChannel Offset: 0x24) Interrupt Enable Register */
RwReg TC_IDR; /**< \brief (TcChannel Offset: 0x28) Interrupt Disable Register */