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cpu/esp32: use ESP-IDF for interrupt handling
This commit is contained in:
Gunar Schorcht
parent
a7ade355da
commit
6bd6afbd22
@ -46,8 +46,15 @@ extern "C" {
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#define CPU_INUM_ETH 18 /**< Level interrupt with low priority 1 */
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#define CPU_INUM_TIMER 19 /**< Level interrupt with medium priority 2 */
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#define CPU_INUM_FRC2 20 /**< Level interrupt with medium priority 2 */
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#define CPU_INUM_SYSTIMER 20 /**< Level interrupt with medium priority 2 */
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#define CPU_INUM_CACHEERR 25 /**< Level interrupt with high priority 4 */
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/** @} */
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/**
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* @brief Initialize architecture specific interrupt handling
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*/
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void esp_irq_init(void);
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#ifdef __cplusplus
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}
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#endif
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@ -1,5 +1,5 @@
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/*
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* Copyright (C) 2018 Gunar Schorcht
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* Copyright (C) 2022 Gunar Schorcht
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*
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* This file is subject to the terms and conditions of the GNU Lesser
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* General Public License v2.1. See the file LICENSE in the top level
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@ -19,58 +19,101 @@
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*/
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#include "irq_arch.h"
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#include "esp_attr.h"
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#include "esp_err.h"
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#include "esp32/rom/ets_sys.h"
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#include "soc/dport_reg.h"
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#include "xtensa/xtensa_api.h"
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#include "freertos/FreeRTOS.h"
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#include "hal/interrupt_controller_types.h"
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#include "hal/interrupt_controller_ll.h"
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#include "rom/ets_sys.h"
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#include "soc/periph_defs.h"
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#include "esp_intr_alloc.h"
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#define ENABLE_DEBUG 0
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#include "debug.h"
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struct _irq_alloc_table_t {
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int src; /* peripheral interrupt source */
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uint32_t intr; /* interrupt number */
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#ifndef ETS_CAN_INTR_SOURCE
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#define ETS_CAN_INTR_SOURCE ETS_TWAI_INTR_SOURCE
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#endif
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typedef struct intr_handle_data_t {
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int src; /* peripheral interrupt source */
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uint8_t intr; /* interrupt number */
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uint8_t level;
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} intr_handle_data_t;
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/* TODO change to a clearer approach */
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static const struct intr_handle_data_t _irq_data_table[] = {
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{ ETS_FROM_CPU_INTR0_SOURCE, CPU_INUM_SOFTWARE, 1 },
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{ ETS_TG0_WDT_LEVEL_INTR_SOURCE, CPU_INUM_WDT, 1 },
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{ ETS_TG0_T0_LEVEL_INTR_SOURCE, CPU_INUM_RTC, 1 },
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#if defined(MCU_ESP32) || defined(MCU_ESP32S2) || defined(MCU_ESP32S3)
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{ ETS_TG0_T1_LEVEL_INTR_SOURCE, CPU_INUM_TIMER, 2 },
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#endif
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#if defined(MCU_ESP32) || defined(MCU_ESP32S2)
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{ ETS_TG0_LACT_LEVEL_INTR_SOURCE, CPU_INUM_TIMER, 2 },
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#endif
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#if !defined(MCU_ESP32C2)
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{ ETS_TG1_T0_LEVEL_INTR_SOURCE, CPU_INUM_TIMER, 2 },
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#endif
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#if defined(MCU_ESP32) || defined(MCU_ESP32S2) || defined(MCU_ESP32S3)
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{ ETS_TG1_T1_LEVEL_INTR_SOURCE, CPU_INUM_TIMER, 2 },
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#endif
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{ ETS_UART0_INTR_SOURCE, CPU_INUM_UART, 1 },
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{ ETS_UART1_INTR_SOURCE, CPU_INUM_UART, 1 },
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#if defined(MCU_ESP32) || defined(MCU_ESP32S2) || defined(MCU_ESP32S3)
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{ ETS_UART2_INTR_SOURCE, CPU_INUM_UART, 1 },
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#endif
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{ ETS_GPIO_INTR_SOURCE, CPU_INUM_GPIO, 1 },
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{ ETS_I2C_EXT0_INTR_SOURCE, CPU_INUM_I2C, 1 },
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#if defined(MCU_ESP32) || defined(MCU_ESP32S2) || defined(MCU_ESP32S3)
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{ ETS_I2C_EXT1_INTR_SOURCE, CPU_INUM_I2C, 1 },
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#endif
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#if defined(MCU_ESP32)
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{ ETS_ETH_MAC_INTR_SOURCE, CPU_INUM_ETH, 1 },
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#endif
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#if !defined(MCU_ESP32C2)
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{ ETS_TWAI_INTR_SOURCE, CPU_INUM_CAN, 1 },
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{ ETS_TIMER2_INTR_SOURCE, CPU_INUM_FRC2, 2 },
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#endif
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#if !defined(MCU_ESP32)
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{ ETS_SYSTIMER_TARGET2_EDGE_INTR_SOURCE, CPU_INUM_SYSTIMER, 2 },
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#endif
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};
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static const struct _irq_alloc_table_t _irq_alloc_table[] = {
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{ ETS_FROM_CPU_INTR0_SOURCE, CPU_INUM_SOFTWARE },
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{ ETS_TG0_WDT_LEVEL_INTR_SOURCE, CPU_INUM_WDT },
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{ ETS_TG0_LACT_LEVEL_INTR_SOURCE, CPU_INUM_RTC },
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{ ETS_TG0_T1_LEVEL_INTR_SOURCE, CPU_INUM_TIMER },
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{ ETS_TG1_T0_LEVEL_INTR_SOURCE, CPU_INUM_TIMER },
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{ ETS_TG1_T1_LEVEL_INTR_SOURCE, CPU_INUM_TIMER },
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{ ETS_UART0_INTR_SOURCE, CPU_INUM_UART },
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{ ETS_UART1_INTR_SOURCE, CPU_INUM_UART },
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{ ETS_UART2_INTR_SOURCE, CPU_INUM_UART },
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{ ETS_GPIO_INTR_SOURCE, CPU_INUM_GPIO },
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{ DPORT_PRO_RTC_CORE_INTR_MAP_REG, CPU_INUM_RTC },
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{ ETS_I2C_EXT0_INTR_SOURCE, CPU_INUM_I2C },
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{ ETS_I2C_EXT1_INTR_SOURCE, CPU_INUM_I2C },
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{ ETS_ETH_MAC_INTR_SOURCE, CPU_INUM_ETH },
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{ ETS_CAN_INTR_SOURCE, CPU_INUM_CAN },
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{ ETS_TIMER2_INTR_SOURCE, CPU_INUM_FRC2 },
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};
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#define IRQ_DATA_TABLE_SIZE ARRAY_SIZE(_irq_data_table)
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typedef void (*intr_handler_t)(void *arg);
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void esp_irq_init(void)
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{
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#ifdef SOC_CPU_HAS_FLEXIBLE_INTC
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/* to avoid to do it in every component, we initialize levels here once */
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for (unsigned i = 0; i < IRQ_DATA_TABLE_SIZE; i++) {
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intr_cntrl_ll_set_int_level(_irq_data_table[i].intr, _irq_data_table[i].level);
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}
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#endif
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}
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#define IRQ_ALLOC_TABLE_SIZE ARRAY_SIZE(_irq_alloc_table)
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#define ESP_INTR_FLAG_INTRDISABLED (1<<11)
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void esp_intr_enable_source(int inum)
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{
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intr_cntrl_ll_enable_interrupts(BIT(inum));
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}
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typedef unsigned intr_handle_t;
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void esp_intr_disable_source(int inum)
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{
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intr_cntrl_ll_disable_interrupts(BIT(inum));
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}
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esp_err_t esp_intr_enable(intr_handle_t handle)
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{
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assert(handle < IRQ_ALLOC_TABLE_SIZE);
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const struct _irq_alloc_table_t *entry = &_irq_alloc_table[handle];
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xt_ints_on(BIT(entry->intr));
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assert(handle != NULL);
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esp_intr_enable_source(handle->intr);
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return ESP_OK;
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}
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esp_err_t esp_intr_disable(intr_handle_t handle)
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{
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assert(handle < IRQ_ALLOC_TABLE_SIZE);
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const struct _irq_alloc_table_t *entry = &_irq_alloc_table[handle];
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xt_ints_off(BIT(entry->intr));
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assert(handle != NULL);
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esp_intr_disable_source(handle->intr);
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return ESP_OK;
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}
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@ -88,29 +131,34 @@ esp_err_t esp_intr_alloc(int source, int flags, intr_handler_t handler,
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void *arg, intr_handle_t *ret_handle)
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{
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unsigned i;
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for (i = 0; i < IRQ_ALLOC_TABLE_SIZE; i++) {
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if (_irq_alloc_table[i].src == source) {
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for (i = 0; i < IRQ_DATA_TABLE_SIZE; i++) {
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if (_irq_data_table[i].src == source) {
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break;
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}
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}
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if (i == IRQ_ALLOC_TABLE_SIZE) {
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if (i == IRQ_DATA_TABLE_SIZE) {
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return ESP_ERR_NOT_FOUND;
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}
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/* route the interrupt source to the CPU interrupt */
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intr_matrix_set(PRO_CPU_NUM, _irq_alloc_table[i].src, _irq_alloc_table[i].intr);
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intr_matrix_set(PRO_CPU_NUM, _irq_data_table[i].src, _irq_data_table[i].intr);
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/* set the interrupt handler */
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xt_set_interrupt_handler(_irq_alloc_table[i].intr, handler, arg);
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intr_cntrl_ll_set_int_handler(_irq_data_table[i].intr, handler, arg);
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#ifdef SOC_CPU_HAS_FLEXIBLE_INTC
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/* set interrupt level given by flags */
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intr_cntrl_ll_set_int_level(_irq_data_table[i].intr, esp_intr_flags_to_level(flags));
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#endif
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/* enable the interrupt if ESP_INTR_FLAG_INTRDISABLED is not set */
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if ((flags & ESP_INTR_FLAG_INTRDISABLED) == 0) {
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xt_ints_on(BIT(_irq_alloc_table[i].intr));
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intr_cntrl_ll_enable_interrupts(BIT(_irq_data_table[i].intr));
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}
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if (ret_handle) {
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*((intr_handle_t *)ret_handle) = i;
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*((intr_handle_t *)ret_handle) = (const intr_handle_t)&_irq_data_table[i];
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}
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return ESP_OK;
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@ -120,3 +168,8 @@ esp_err_t esp_intr_free(intr_handle_t handle)
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{
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return esp_intr_disable(handle);
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}
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int esp_intr_get_cpu(intr_handle_t handle)
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{
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return PRO_CPU_NUM;
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}
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