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boards/common/wsn30: cleanup clock configuration
This commit is contained in:
Hauke Petersen
parent
ea0dc223a4
commit
70aa86e5e6
@ -1,6 +1,6 @@
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/*
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* board_init.c - Implementation of functions to init board.
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* Copyright (C) 2013 Milan Babel <babel@inf.fu-berlin.de>
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* 2017 Freie Universität Berlin
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*
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* This file is subject to the terms and conditions of the GNU Lesser
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* General Public License v2.1. See the file LICENSE in the top level
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@ -15,103 +15,76 @@
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* @brief Board initialization for WSN430
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*
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* @author Milan Babel <babel@inf.fu-berlin.de>
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* @author Hauke Petersen <hauke.petersen@fu-berlin.de>
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*
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* @}
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*/
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#include "cpu.h"
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#include "irq.h"
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#include "board.h"
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#include "msp430.h"
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#include "debug.h"
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#include "assert.h"
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#include "uart_stdio.h"
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#include "periph_conf.h"
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static volatile uint32_t __msp430_cpu_speed = MSP430_INITIAL_CPU_SPEED;
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void msp430_init_dco(void);
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typedef enum {
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MCLK_2MHZ_SCLK_1MHZ = 1000002uL,
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MCLK_4MHZ_SCLK_1MHZ = 1000004uL,
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MCLK_8MHZ_SCLK_1MHZ = 1000008uL,
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MCLK_8MHZ_SCLK_8MHZ = 8000000uL
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}speed_t;
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enum {
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MCLK_2MHZ_SCLK_1MHZ = (SELM_2 | DIVM_2 | SELS | DIVS_3),
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MCLK_4MHZ_SCLK_1MHZ = (SELM_2 | DIVM_1 | SELS | DIVS_3),
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MCLK_8MHZ_SCLK_1MHZ = (SELM_2 | SELS | DIVS_3),
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MCLK_8MHZ_SCLK_8MHZ = (SELM_2 | SELS),
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};
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static void msb_ports_init(void)
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{
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// Port 1: GDO, Flash, BSL TX
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P1SEL = 0x02; // Port1 Select: 00000010 = 0x02
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P1OUT = 0x00; // Port1 Output: 00000000 = 0x00
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P1DIR = 0x87; // Port1 Direction: 10000111 = 0x87
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/* Port 1: GDO, Flash, BSL TX */
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P1SEL = 0x02; /* Port1 Select: 00000010 = 0x02 */
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P1OUT = 0x00; /* Port1 Output: 00000000 = 0x00 */
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P1DIR = 0x87; /* Port1 Direction: 10000111 = 0x87 */
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// Port 2: GPIO, BSL RX, 1wire
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P2SEL = 0x04; // Port2 Select: 00000100 = 0x04
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P2OUT = 0x00; // Port2 Output: 00000000 = 0x00
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P2DIR = 0xFF; // Port2 Direction: 11111111 = 0xFF
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/* Port 2: GPIO, BSL RX, 1wire */
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P2SEL = 0x04; /* Port2 Select: 00000100 = 0x04 */
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P2OUT = 0x00; /* Port2 Output: 00000000 = 0x00 */
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P2DIR = 0xFF; /* Port2 Direction: 11111111 = 0xFF */
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// Port 3: UART
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P3SEL = 0xFE; // Port3 Select: 11111110 = 0xFE
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P3OUT = 0x00; // Port3 Output: 00000000 = 0x00
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P3DIR = 0xFF; // Port3 Direction: 11111111 = 0xFF
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/* Port 3: UART */
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P3SEL = 0xFE; /* Port3 Select: 11111110 = 0xFE */
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P3OUT = 0x00; /* Port3 Output: 00000000 = 0x00 */
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P3DIR = 0xFF; /* Port3 Direction: 11111111 = 0xFF */
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// Port 4: CS
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P4SEL = 0x00; // Port4 Select: 00000000 = 0x00
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P4OUT = 0x14; // Port4 Output: 00010100 = 0x14
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P4DIR = 0xFF; // Port4 Direction: 11111111 = 0xFF
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/* Port 4: CS */
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P4SEL = 0x00; /* Port4 Select: 00000000 = 0x00 */
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P4OUT = 0x14; /* Port4 Output: 00010100 = 0x14 */
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P4DIR = 0xFF; /* Port4 Direction: 11111111 = 0xFF */
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// Port 5: SPI, LED
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P5SEL = 0x0E; // Port5 Select: 00001110 = 0x0E
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P5OUT = 0x70; // Port5 Output: 01110000 = 0x70
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P5DIR = 0x70; // Port5 Direction: 01110000 = 0x70
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/* Port 5: SPI, LED */
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P5SEL = 0x0E; /* Port5 Select: 00001110 = 0x0E */
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P5OUT = 0x70; /* Port5 Output: 01110000 = 0x70 */
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P5DIR = 0x70; /* Port5 Direction: 01110000 = 0x70 */
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P6SEL = 0xFF; // Port6 Select: 11111111 = 0xFF
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P6OUT = 0x00; // Port6 Output: 00000000 = 0x00
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P6DIR = 0xFF; // Port6 Direction: 11111000 = 0xF8
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P6SEL = 0xFF; /* Port6 Select: 11111111 = 0xFF */
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P6OUT = 0x00; /* Port6 Output: 00000000 = 0x00 */
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P6DIR = 0xFF; /* Port6 Direction: 11111000 = 0xF8 */
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}
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void msp430_set_cpu_speed(uint32_t speed)
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static void msp430_init_cpuclk(uint8_t speed)
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{
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irq_disable();
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__msp430_cpu_speed = speed;
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msp430_init_dco();
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irq_enable();
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}
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/* stop watchdog */
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WDTCTL = WDTPW + WDTHOLD;
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BCSCTL1 = RSEL2;
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/*---------------------------------------------------------------------------*/
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void msp430_init_dco(void)
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{
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/*----------------------- use external oszillator -------------------------*/
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uint16_t i;
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/* wait for XTAL to stabilize */
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do {
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/* clear oscillator fault flag */
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IFG1 &= ~OFIFG;
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/* time for flag to set */
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for (uint16_t i = 0xFF; i > 0; i--) {}
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} while ((IFG1 & OFIFG) != 0);
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// Stop watchdog
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WDTCTL = WDTPW + WDTHOLD;
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BCSCTL1 = RSEL2;
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// Wait for xtal to stabilize
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do {
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IFG1 &= ~OFIFG; // Clear oscillator fault flag
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for (i = 0xFF; i > 0; i--); // Time for flag to set
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}
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while ((IFG1 & OFIFG) != 0); // Oscillator fault flag still set?
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switch (__msp430_cpu_speed) {
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case MCLK_2MHZ_SCLK_1MHZ:
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BCSCTL2 = (SELM_2 | DIVM_2) | (SELS | DIVS_3);
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break;
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case MCLK_4MHZ_SCLK_1MHZ:
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BCSCTL2 = (SELM_2 | DIVM_1) | (SELS | DIVS_3);
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break;
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case MCLK_8MHZ_SCLK_1MHZ:
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BCSCTL2 = SELM_2 | (SELS | DIVS_3);
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break;
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default:
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BCSCTL2 = SELM_2 + SELS; // MCLK and SMCLK = XT2 (safe)
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break;
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}
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/* apply clock config */
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BCSCTL2 = speed;
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}
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void board_init(void)
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@ -119,7 +92,10 @@ void board_init(void)
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msp430_cpu_init();
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msb_ports_init();
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msp430_set_cpu_speed(MCLK_8MHZ_SCLK_8MHZ);
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/* initialize CPU clock */
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unsigned state = irq_disable();
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msp430_init_cpuclk(CLOCK_MODE);
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irq_restore(state);
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/* initialize STDIO over UART */
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uart_stdio_init();
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@ -43,18 +43,6 @@ extern "C" {
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#define XTIMER_BACKOFF (40)
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/** @} */
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/**
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* @name CPU core configuration
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* @{
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*/
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/** @todo Move this to the periph_conf.h */
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#define MSP430_INITIAL_CPU_SPEED 800000uL
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#define F_CPU MSP430_INITIAL_CPU_SPEED
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#define F_RC_OSCILLATOR 32768
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#define MSP430_HAS_DCOR 0
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#define MSP430_HAS_EXTERNAL_CRYSTAL 1
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/** @} */
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/**
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* @name LED pin definitions and handlers
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* @{
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@ -15,7 +15,7 @@
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* @brief WSN430 peripheral configuration
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*
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* @author Oliver Hahm <oliver.hahm@inria.fr>
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* Hauke Petersen <hauke.petersen@fu-berlin.de>
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* @author Hauke Petersen <hauke.petersen@fu-berlin.de>
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*/
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#ifndef PERIPH_CONF_H
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@ -29,9 +29,9 @@ extern "C" {
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* @name Clock configuration
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* @{
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*/
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#define CLOCK_CORECLOCK (8000000U)
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#define CLOCK_CMCLK CLOCK_CORECLOCK /* no divider programmed */
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#define CLOCK_CORECLOCK (8000000UL)
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#define CLOCK_MODE (MCLK_8MHZ_SCLK_8MHZ)
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#define CLOCK_CMCLK (CLOCK_CORECLOCK) /* no divider programmed */
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/** @} */
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/**
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@ -91,3 +91,4 @@ extern "C" {
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#endif
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#endif /* PERIPH_CONF_H */
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/** @} */
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