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stm32f2: update timer and pwm drivers

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This commit is contained in:
Vincent Dupont 2016-04-14 14:44:19 +02:00
parent d01da278ac
commit 70c8bff842
3 changed files with 204 additions and 326 deletions
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51
cpu/stm32f2/include/periph_cpu.h
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@ -1,5 +1,6 @@
/*
* Copyright (C) 2015 Engineering-Spirit
* Copyright (C) 2016 OTA keys S.A.
*
* This file is subject to the terms and conditions of the GNU Lesser
* General Public License v2.1. See the file LICENSE in the top level
@ -14,6 +15,7 @@
* @brief CPU specific definitions for internal peripheral handling
*
* @author Nick v. IJzendoorn <nijzendoorn@engineering-spirit.nl>
* @author Aurelien Gonce <aurelien.gonce@altran.fr>
*/
#ifndef PERIPH_CPU_H
@ -50,6 +52,15 @@ typedef enum {
} gpio_mode_t;
/** @} */
/**
* @brief Available peripheral buses
*/
enum {
AHB1, /**< AHB1 bus */
AHB2, /**< AHB2 bus */
AHB3 /**< AHB3 bus */
};
/**
* @brief Available ports on the STM32F2 family
*/
@ -86,6 +97,38 @@ typedef enum {
GPIO_AF14 /**< use alternate function 14 */
} gpio_af_t;
/**
* @name PWM configuration
* @{
*/
typedef struct {
uint8_t tim; /**< timer used */
GPIO_TypeDef *port; /**< pwm device */
uint8_t bus; /**< AHBx bus */
uint32_t rcc_mask; /**< corresponding bit in the RCC register */
uint8_t CH0; /**< channel 0 */
uint8_t CH1; /**< channel 1 */
uint8_t CH2; /**< channel 2 */
uint8_t CH3; /**< channel 3 */
uint8_t AF; /**< alternate function */
} pwm_conf_t;
/**
* @brief Timer configuration
* @{
*/
typedef struct {
TIM_TypeDef *dev; /**< timer device */
uint8_t channels; /**< number of channel */
uint32_t freq; /**< frequency */
uint32_t rcc_mask; /**< corresponding bit in the RCC register */
uint8_t bus; /**< APBx bus the timer is clock from */
uint8_t irqn; /**< global IRQ channel */
uint8_t priority; /**< priority */
} timer_conf_t;
/** @} */
/**
* @brief Structure for UART configuration data
* @{
@ -197,13 +240,13 @@ static inline int dma_hl(int stream)
static inline uint32_t dma_ifc(int stream)
{
switch (stream & 0x3) {
case 0:
case 0: /* 0 and 4 */
return (1 << 5);
case 1:
case 1: /* 1 and 5 */
return (1 << 11);
case 2:
case 2: /* 2 and 6 */
return (1 << 21);
case 3:
case 3: /* 3 and 7 */
return (1 << 27);
default:
return 0;

253
cpu/stm32f2/periph/pwm.c
View File

@ -1,5 +1,6 @@
/*
* Copyright (C) 2015 Engineering-Spirit
* Copyright (C) 2016 OTA keys S.A.
*
* This file is subject to the terms and conditions of the GNU Lesser General
* Public License v2.1. See the file LICENSE in the top level directory for more
@ -16,6 +17,7 @@
* @author Hauke Petersen <mail@haukepetersen.de>
* @author Fabian Nack <nack@inf.fu-berlin.de>
* @author Nick v. IJzendoorn <nijzendoorn@engineering-spirit.nl>
* @author Aurelien Gonce <aurelien.gonce@altran.fr>
*
* @}
*/
@ -26,62 +28,57 @@
#include "cpu.h"
#include "periph/pwm.h"
#include "periph_conf.h"
#include "periph/timer.h"
/* ignore file in case no PWM devices are defined */
#if PWM_0_EN || PWM_1_EN
#if (PWM_NUMOF > 0)
int pwm_init(pwm_t dev, pwm_mode_t mode, unsigned int frequency, unsigned int resolution)
/**
* @brief Get the timer device
*/
static inline TIM_TypeDef *get_tim_dev(pwm_t tim)
{
TIM_TypeDef *tim = NULL;
GPIO_TypeDef *port = NULL;
uint32_t pins[PWM_MAX_CHANNELS];
uint32_t af = 0;
uint32_t pwm_clk = 0;
int channels = 0;
return timer_config[tim].dev;
}
pwm_poweron(dev);
/**
* @brief Get the pwm device
*/
static inline GPIO_TypeDef *get_pwm_port(pwm_t pwm)
{
return pwm_config[pwm].port;
}
switch (dev) {
#if PWM_0_EN
case PWM_0:
tim = PWM_0_DEV;
port = PWM_0_PORT;
pins[0] = PWM_0_PIN_CH0;
#if (PWM_0_CHANNELS > 1)
pins[1] = PWM_0_PIN_CH1;
#endif
#if (PWM_0_CHANNELS > 2)
pins[2] = PWM_0_PIN_CH2;
#endif
#if (PWM_0_CHANNELS > 3)
pins[3] = PWM_0_PIN_CH3;
#endif
af = PWM_0_PIN_AF;
channels = PWM_0_CHANNELS;
pwm_clk = PWM_0_CLK;
PWM_0_PORT_CLKEN();
break;
#endif
#if PWM_1_EN
case PWM_1:
tim = PWM_1_DEV;
port = PWM_1_PORT;
pins[0] = PWM_1_PIN_CH0;
#if (PWM_1_CHANNELS > 1)
pins[1] = PWM_1_PIN_CH1;
#endif
#if (PWM_1_CHANNELS > 2)
pins[2] = PWM_1_PIN_CH2;
#endif
#if (PWM_1_CHANNELS > 3)
pins[3] = PWM_1_PIN_CH3;
#endif
af = PWM_1_PIN_AF;
channels = PWM_1_CHANNELS;
pwm_clk = PWM_1_CLK;
PWM_1_PORT_CLKEN();
break;
#endif
uint32_t pwm_init(pwm_t dev, pwm_mode_t mode, uint32_t freq, uint16_t res)
{
GPIO_TypeDef *port = get_pwm_port(dev);
tim_t tim = pwm_config[dev].tim;
TIM_TypeDef *timer_dev = get_tim_dev(tim);
uint8_t channels = pwm_channels(tim);
uint32_t pins[channels];
/* enable timer peripheral clock */
pwm_poweron(tim);
/* pins configuration */
pins[0] = pwm_config[dev].CH0;
if (channels > 1) {
pins[1] = pwm_config[dev].CH1;
}
if (channels > 2) {
pins[2] = pwm_config[dev].CH2;
}
if (channels > 3) {
pins[3] = pwm_config[dev].CH3;
}
/* enable pwm peripheral */
if (pwm_config[dev].bus == AHB1) {
RCC->AHB1ENR |= pwm_config[dev].rcc_mask;
} else if (pwm_config[dev].bus == AHB2) {
RCC->AHB2ENR |= pwm_config[dev].rcc_mask;
} else {
RCC->AHB3ENR |= pwm_config[dev].rcc_mask;
}
/* setup pins: alternate function */
@ -90,189 +87,133 @@ int pwm_init(pwm_t dev, pwm_mode_t mode, unsigned int frequency, unsigned int re
port->MODER |= (2 << (pins[i] * 2));
if (pins[i] < 8) {
port->AFR[0] &= ~(0xf << (pins[i] * 4));
port->AFR[0] |= (af << (pins[i] * 4));
port->AFR[0] |= (pwm_config[dev].AF << (pins[i] * 4));
} else {
port->AFR[1] &= ~(0xf << ((pins[i] - 8) * 4));
port->AFR[1] |= (af << ((pins[i] - 8) * 4));
port->AFR[1] |= (pwm_config[dev].AF << ((pins[i] - 8) * 4));
}
}
/* Reset C/C and timer configuration register */
switch (channels) {
case 4:
tim->CCR4 = 0;
timer_dev->CCR4 = 0;
/* Fall through */
case 3:
tim->CCR3 = 0;
tim->CR2 = 0;
timer_dev->CCR3 = 0;
timer_dev->CR2 = 0;
/* Fall through */
case 2:
tim->CCR2 = 0;
timer_dev->CCR2 = 0;
/* Fall through */
case 1:
tim->CCR1 = 0;
tim->CR1 = 0;
timer_dev->CCR1 = 0;
timer_dev->CR1 = 0;
break;
}
/* set prescale and auto-reload registers to matching values for resolution and frequency */
if (resolution > 0xffff || (resolution * frequency) > pwm_clk) {
return -2;
if (res > 0xffff || (res * freq) > timer_config[tim].freq) {
return 0;
}
tim->PSC = (pwm_clk / (resolution * frequency)) - 1;
tim->ARR = resolution - 1;
timer_dev->PSC = (timer_config[tim].freq / (res * freq)) - 1;
timer_dev->ARR = res - 1;
/* calculate the actual PWM frequency */
frequency = (pwm_clk / (resolution * (tim->PSC + 1)));
freq = (timer_config[tim].freq / (res * (timer_dev->PSC + 1)));
/* set PWM mode */
switch (mode) {
case PWM_LEFT:
tim->CCMR1 = (TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_2 |
TIM_CCMR1_OC2M_1 | TIM_CCMR1_OC2M_2);
timer_dev->CCMR1 = (TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_2 |
TIM_CCMR1_OC2M_1 | TIM_CCMR1_OC2M_2);
if (channels > 2) {
tim->CCMR2 = (TIM_CCMR2_OC3M_1 | TIM_CCMR2_OC3M_2 |
TIM_CCMR2_OC4M_1 | TIM_CCMR2_OC4M_2);
timer_dev->CCMR2 = (TIM_CCMR2_OC3M_1 | TIM_CCMR2_OC3M_2 |
TIM_CCMR2_OC4M_1 | TIM_CCMR2_OC4M_2);
}
break;
case PWM_RIGHT:
tim->CCMR1 = (TIM_CCMR1_OC1M_0 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_2 |
TIM_CCMR1_OC2M_0 | TIM_CCMR1_OC2M_1 | TIM_CCMR1_OC2M_2);
timer_dev->CCMR1 = (TIM_CCMR1_OC1M_0 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_2 |
TIM_CCMR1_OC2M_0 | TIM_CCMR1_OC2M_1 | TIM_CCMR1_OC2M_2);
if (channels > 2) {
tim->CCMR2 = (TIM_CCMR2_OC3M_0 | TIM_CCMR2_OC3M_1 | TIM_CCMR2_OC3M_2 |
TIM_CCMR2_OC4M_0 | TIM_CCMR2_OC4M_1 | TIM_CCMR2_OC4M_2);
timer_dev->CCMR2 = (TIM_CCMR2_OC3M_0 | TIM_CCMR2_OC3M_1 | TIM_CCMR2_OC3M_2 |
TIM_CCMR2_OC4M_0 | TIM_CCMR2_OC4M_1 | TIM_CCMR2_OC4M_2);
}
break;
case PWM_CENTER:
tim->CCMR1 = 0;
timer_dev->CCMR1 = 0;
if (channels > 2) {
tim->CCMR2 = 0;
timer_dev->CCMR2 = 0;
}
tim->CR1 |= (TIM_CR1_CMS_0 | TIM_CR1_CMS_1);
timer_dev->CR1 |= (TIM_CR1_CMS_0 | TIM_CR1_CMS_1);
break;
}
/* enable output on PWM pins */
tim->CCER = (TIM_CCER_CC1E | TIM_CCER_CC2E | TIM_CCER_CC3E | TIM_CCER_CC4E);
timer_dev->CCER = (TIM_CCER_CC1E | TIM_CCER_CC2E | TIM_CCER_CC3E | TIM_CCER_CC4E);
/* enable PWM outputs */
tim->BDTR = TIM_BDTR_MOE;
timer_dev->BDTR = TIM_BDTR_MOE;
/* enable timer ergo the PWM generation */
pwm_start(dev);
pwm_start(tim);
return frequency;
return freq;
}
int pwm_set(pwm_t dev, int channel, unsigned int value)
{
TIM_TypeDef *tim = NULL;
uint8_t pwm_channels(pwm_t dev) {
return (timer_config[dev].channels);
}
switch (dev) {
#if PWM_0_EN
case PWM_0:
tim = PWM_0_DEV;
if (channel >= PWM_0_CHANNELS) {
return -1;
}
break;
#endif
#if PWM_1_EN
case PWM_1:
tim = PWM_1_DEV;
if (channel >= PWM_1_CHANNELS) {
return -1;
}
break;
#endif
void pwm_set(pwm_t dev, uint8_t channel, uint16_t value)
{
tim_t tim = pwm_config[dev].tim;
TIM_TypeDef *timer_dev = get_tim_dev(tim);
if (channel >= pwm_channels(tim)) {
return;
}
/* norm value to maximum possible value */
if (value > tim->ARR) {
value = (unsigned int) tim->ARR;
if (value > timer_dev->ARR) {
value = (uint16_t) timer_dev->ARR;
}
switch (channel) {
case 0:
tim->CCR1 = value;
timer_dev->CCR1 = value;
break;
case 1:
tim->CCR2 = value;
timer_dev->CCR2 = value;
break;
case 2:
tim->CCR3 = value;
timer_dev->CCR3 = value;
break;
case 3:
tim->CCR4 = value;
timer_dev->CCR4 = value;
break;
default:
return -1;
break;
}
return 0;
}
void pwm_start(pwm_t dev)
{
switch (dev) {
#if PWM_0_EN
case PWM_0:
PWM_0_DEV->CR1 |= TIM_CR1_CEN;
break;
#endif
#if PWM_1_EN
case PWM_1:
PWM_1_DEV->CR1 |= TIM_CR1_CEN;
break;
#endif
}
get_tim_dev(dev)->CR1 |= TIM_CR1_CEN;
}
void pwm_stop(pwm_t dev)
{
switch (dev) {
#if PWM_0_EN
case PWM_0:
PWM_0_DEV->CR1 &= ~(TIM_CR1_CEN);
break;
#endif
#if PWM_1_EN
case PWM_1:
PWM_1_DEV->CR1 &= ~(TIM_CR1_CEN);
break;
#endif
}
get_tim_dev(dev)->CR1 &= ~(TIM_CR1_CEN);
}
void pwm_poweron(pwm_t dev)
{
switch (dev) {
#if PWM_0_EN
case PWM_0:
PWM_0_CLKEN();
break;
#endif
#if PWM_1_EN
case PWM_1:
PWM_1_CLKEN();
break;
#endif
}
periph_clk_en(timer_config[dev].bus, timer_config[dev].rcc_mask);
}
void pwm_poweroff(pwm_t dev)
{
switch (dev) {
#if PWM_0_EN
case PWM_0:
PWM_0_CLKDIS();
break;
#endif
#if PWM_1_EN
case PWM_1:
PWM_1_CLKDIS();
break;
#endif
}
periph_clk_dis(timer_config[dev].bus, timer_config[dev].rcc_mask);
}
#endif /* PWM_0_EN || PWM_1_EN */
#endif /* PWM_NUMOF > 0*/

226
cpu/stm32f2/periph/timer.c
View File

@ -1,5 +1,6 @@
/*
* Copyright (C) 2014 Freie Universität Berlin
* Copyright (C) 2016 OTA keys S.A.
*
* This file is subject to the terms and conditions of the GNU Lesser General
* Public License v2.1. See the file LICENSE in the top level directory for more
@ -7,13 +8,14 @@
*/
/**
* @ingroup cpu_stm32f4
* @ingroup cpu_stm32f2
* @{
*
* @file
* @brief Low-level timer driver implementation
*
* @author Hauke Petersen <hauke.petersen@fu-berlin.de>
* @author Aurelien Gonce <aurelien.gonce@altran.fr>
*
* @}
*/
@ -33,49 +35,40 @@ static inline void irq_handler(tim_t timer, TIM_TypeDef *dev);
/** Timer state memory */
static timer_isr_ctx_t config[TIMER_NUMOF];
/**
* @brief Get the timer device
*/
static inline TIM_TypeDef *get_dev(tim_t tim)
{
return timer_config[tim].dev;
}
int timer_init(tim_t dev, unsigned long freq, timer_cb_t cb, void *arg)
{
TIM_TypeDef *timer;
switch (dev) {
#if TIMER_0_EN
case TIMER_0:
/* enable timer peripheral clock */
TIMER_0_CLKEN();
/* set timer's IRQ priority */
NVIC_SetPriority(TIMER_0_IRQ_CHAN, TIMER_IRQ_PRIO);
/* select timer */
timer = TIMER_0_DEV;
timer->PSC = (TIMER_0_FREQ / freq) - 1;
break;
#endif
#if TIMER_1_EN
case TIMER_1:
/* enable timer peripheral clock */
TIMER_1_CLKEN();
/* set timer's IRQ priority */
NVIC_SetPriority(TIMER_1_IRQ_CHAN, TIMER_IRQ_PRIO);
/* select timer */
timer = TIMER_1_DEV;
timer->PSC = (TIMER_1_FREQ / freq) - 1;
break;
#endif
case TIMER_UNDEFINED:
default:
return -1;
/* check if device is valid */
if (dev >= TIMER_NUMOF) {
return -1;
}
/* enable timer peripheral clock */
periph_clk_en(timer_config[dev].bus, timer_config[dev].rcc_mask);
/* set timer's IRQ priority */
NVIC_SetPriority(timer_config[dev].irqn, timer_config[dev].priority);
/* set prescaler */
get_dev(dev)->PSC = (timer_config[dev].freq / freq) - 1;
/* set callback function */
config[dev].cb = cb;
config[dev].arg = arg;
/* set timer to run in counter mode */
timer->CR1 = 0;
timer->CR2 = 0;
get_dev(dev)->CR1 = 0;
get_dev(dev)->CR2 = 0;
/* set auto-reload and prescaler values and load new values */
timer->EGR |= TIM_EGR_UG;
get_dev(dev)->EGR |= TIM_EGR_UG;
/* enable the timer's interrupt */
timer_irq_enable(dev);
@ -89,49 +82,35 @@ int timer_init(tim_t dev, unsigned long freq, timer_cb_t cb, void *arg)
int timer_set(tim_t dev, int channel, unsigned int timeout)
{
int now = timer_read(dev);
return timer_set_absolute(dev, channel, now + timeout - 1);
return timer_set_absolute(dev, channel, now + timeout);
}
int timer_set_absolute(tim_t dev, int channel, unsigned int value)
{
TIM_TypeDef *timer;
switch (dev) {
#if TIMER_0_EN
case TIMER_0:
timer = TIMER_0_DEV;
break;
#endif
#if TIMER_1_EN
case TIMER_1:
timer = TIMER_1_DEV;
break;
#endif
case TIMER_UNDEFINED:
default:
return -1;
if (channel >= timer_config[dev].channels || dev >= TIMER_NUMOF) {
return -1;
}
switch (channel) {
case 0:
timer->CCR1 = value;
timer->SR &= ~TIM_SR_CC1IF;
timer->DIER |= TIM_DIER_CC1IE;
get_dev(dev)->CCR1 = value;
get_dev(dev)->SR &= ~TIM_SR_CC1IF;
get_dev(dev)->DIER |= TIM_DIER_CC1IE;
break;
case 1:
timer->CCR2 = value;
timer->SR &= ~TIM_SR_CC2IF;
timer->DIER |= TIM_DIER_CC2IE;
get_dev(dev)->CCR2 = value;
get_dev(dev)->SR &= ~TIM_SR_CC2IF;
get_dev(dev)->DIER |= TIM_DIER_CC2IE;
break;
case 2:
timer->CCR3 = value;
timer->SR &= ~TIM_SR_CC3IF;
timer->DIER |= TIM_DIER_CC3IE;
get_dev(dev)->CCR3 = value;
get_dev(dev)->SR &= ~TIM_SR_CC3IF;
get_dev(dev)->DIER |= TIM_DIER_CC3IE;
break;
case 3:
timer->CCR4 = value;
timer->SR &= ~TIM_SR_CC4IF;
timer->DIER |= TIM_DIER_CC4IE;
get_dev(dev)->CCR4 = value;
get_dev(dev)->SR &= ~TIM_SR_CC4IF;
get_dev(dev)->DIER |= TIM_DIER_CC4IE;
break;
default:
return -1;
@ -142,143 +121,58 @@ int timer_set_absolute(tim_t dev, int channel, unsigned int value)
int timer_clear(tim_t dev, int channel)
{
TIM_TypeDef *timer;
switch (dev) {
#if TIMER_0_EN
case TIMER_0:
timer = TIMER_0_DEV;
break;
#endif
#if TIMER_1_EN
case TIMER_1:
timer = TIMER_1_DEV;
break;
#endif
case TIMER_UNDEFINED:
default:
return -1;
if (channel >= timer_config[dev].channels || dev >= TIMER_NUMOF) {
return -1;
}
switch (channel) {
case 0:
timer->DIER &= ~TIM_DIER_CC1IE;
break;
case 1:
timer->DIER &= ~TIM_DIER_CC2IE;
break;
case 2:
timer->DIER &= ~TIM_DIER_CC3IE;
break;
case 3:
timer->DIER &= ~TIM_DIER_CC4IE;
break;
default:
return -1;
}
get_dev(dev)->DIER &= ~(TIM_DIER_CC1IE << channel);
return 0;
}
unsigned int timer_read(tim_t dev)
{
switch (dev) {
#if TIMER_0_EN
case TIMER_0:
return TIMER_0_DEV->CNT;
break;
#endif
#if TIMER_1_EN
case TIMER_1:
return TIMER_1_DEV->CNT;
break;
#endif
case TIMER_UNDEFINED:
default:
return 0;
}
return (unsigned int)get_dev(dev)->CNT;
}
void timer_start(tim_t dev)
{
switch (dev) {
#if TIMER_0_EN
case TIMER_0:
TIMER_0_DEV->CR1 |= TIM_CR1_CEN;
break;
#endif
#if TIMER_1_EN
case TIMER_1:
TIMER_1_DEV->CR1 |= TIM_CR1_CEN;
break;
#endif
case TIMER_UNDEFINED:
break;
}
get_dev(dev)->CR1 |= TIM_CR1_CEN;
}
void timer_stop(tim_t dev)
{
switch (dev) {
#if TIMER_0_EN
case TIMER_0:
TIMER_0_DEV->CR1 &= ~TIM_CR1_CEN;
break;
#endif
#if TIMER_1_EN
case TIMER_1:
TIMER_1_DEV->CR1 &= ~TIM_CR1_CEN;
break;
#endif
case TIMER_UNDEFINED:
break;
}
get_dev(dev)->CR1 &= ~TIM_CR1_CEN;
}
void timer_irq_enable(tim_t dev)
{
switch (dev) {
#if TIMER_0_EN
case TIMER_0:
NVIC_EnableIRQ(TIMER_0_IRQ_CHAN);
break;
#endif
#if TIMER_1_EN
case TIMER_1:
NVIC_EnableIRQ(TIMER_1_IRQ_CHAN);
break;
#endif
case TIMER_UNDEFINED:
break;
}
NVIC_EnableIRQ(timer_config[dev].irqn);
}
void timer_irq_disable(tim_t dev)
{
switch (dev) {
#if TIMER_0_EN
case TIMER_0:
NVIC_DisableIRQ(TIMER_0_IRQ_CHAN);
break;
#endif
#if TIMER_1_EN
case TIMER_1:
NVIC_DisableIRQ(TIMER_1_IRQ_CHAN);
break;
#endif
case TIMER_UNDEFINED:
break;
}
NVIC_DisableIRQ(timer_config[dev].irqn);
}
void TIMER_0_ISR(void)
{
irq_handler(TIMER_0, TIMER_0_DEV);
irq_handler(TIMER_0, get_dev(TIMER_0));
}
void TIMER_1_ISR(void)
{
irq_handler(TIMER_1, TIMER_1_DEV);
irq_handler(TIMER_1, get_dev(TIMER_1));
}
void TIMER_2_ISR(void)
{
irq_handler(TIMER_2, get_dev(TIMER_2));
}
void TIMER_3_ISR(void)
{
irq_handler(TIMER_3, get_dev(TIMER_3));
}
static inline void irq_handler(tim_t timer, TIM_TypeDef *dev)