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nrf52: Add EasyDMA-based SPI periph driver
This commit is contained in:
Koen Zandberg
parent
1139c0737f
commit
720ccad7dd
@ -5,5 +5,12 @@ ifneq (,$(filter nrf802154,$(USEMODULE)))
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USEMODULE += netdev_ieee802154
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endif
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# The nrf52832 requires gpio IRQ with SPI to work around errata 58
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ifneq (,$(filter nrf52832xxaa,$(CPU_MODEL)))
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ifneq (,$(filter periph_spi,$(USEMODULE)))
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FEATURES_REQUIRED += periph_gpio_irq
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endif
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endif
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include $(RIOTCPU)/nrf5x_common/Makefile.dep
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include $(RIOTCPU)/cortexm_common/Makefile.dep
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@ -27,6 +27,14 @@
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extern "C" {
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#endif
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/**
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* @brief Enable the workaround for the SPI single byte transmit errata (No.
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* 58 on the nrf52832)
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*/
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#ifdef CPU_MODEL_NRF52832XXAA
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#define ERRATA_SPI_SINGLE_BYTE_WORKAROUND (1)
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#endif
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/**
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* @brief System core clock speed, fixed to 64MHz for all NRF52x CPUs
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*/
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@ -54,6 +62,14 @@ extern "C" {
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*/
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#define ADC_NUMOF (9U)
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/**
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* @brief SPI temporary buffer size for storing const data in RAM before
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* initiating DMA transfer
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*/
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#ifndef CONFIG_SPI_MBUF_SIZE
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#define CONFIG_SPI_MBUF_SIZE 64
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#endif
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/**
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* @brief nRF52 specific naming of ADC lines (for convenience)
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*/
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@ -180,6 +196,20 @@ typedef struct {
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} uart_conf_t;
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#endif
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/**
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* @brief SPI configuration values
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*/
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typedef struct {
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NRF_SPIM_Type *dev; /**< SPI device used */
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gpio_t sclk; /**< CLK pin */
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gpio_t mosi; /**< MOSI pin */
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gpio_t miso; /**< MISO pin */
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#if ERRATA_SPI_SINGLE_BYTE_WORKAROUND
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uint8_t ppi; /**< PPI channel */
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#endif
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} spi_conf_t;
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/**
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* @brief Common SPI/I2C interrupt callback
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*
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258
cpu/nrf52/periph/spi.c
Normal file
258
cpu/nrf52/periph/spi.c
Normal file
@ -0,0 +1,258 @@
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/*
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* Copyright (C) 2014-2016 Freie Universität Berlin
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* Copyright (C) 2020 Inria
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* Copyright (C) 2020 Koen Zandberg <koen@bergzand.net>
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*
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* This file is subject to the terms and conditions of the GNU Lesser
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* General Public License v2.1. See the file LICENSE in the top level
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* directory for more details.
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*/
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/**
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* @ingroup cpu_nrf52
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* @ingroup drivers_periph_spi
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* @{
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*
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* @file
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* @brief Low-level SPI driver implementation based on the SPIM peripheral
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*
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* @author Hauke Petersen <hauke.petersen@fu-berlin.de>
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* @author Frank Holtz <frank-riot2015@holtznet.de>
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* @author Jan Wagner <mail@jwagner.eu>
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* @author Koen Zandberg <koen@bergzand.net>
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*
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* @}
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*/
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#include "cpu.h"
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#include "mutex.h"
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#include "assert.h"
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#include "periph/spi.h"
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#include "periph/gpio.h"
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#include "periph_cpu.h"
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#include <string.h>
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#define RAM_MASK (0x20000000)
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/**
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* @brief array holding one pre-initialized mutex for each SPI device
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*/
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static mutex_t locks[SPI_NUMOF];
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/**
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* @brief array with a busy mutex for each SPI device, used to block the
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* thread until the transfer is done
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*/
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static mutex_t busy[SPI_NUMOF];
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static uint8_t _mbuf[SPI_NUMOF][CONFIG_SPI_MBUF_SIZE];
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static void spi_isr_handler(void *arg);
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static inline NRF_SPIM_Type *dev(spi_t bus)
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{
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return (NRF_SPIM_Type *)spi_config[bus].dev;
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}
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static inline bool _in_ram(const uint8_t *data)
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{
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return ((uint32_t)data & RAM_MASK);
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}
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#ifdef ERRATA_SPI_SINGLE_BYTE_WORKAROUND
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void spi_gpio_handler(void *arg)
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{
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spi_t bus = (spi_t)arg;
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/**
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* Immediately disable the IRQ, we only care about one PPI event per
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* transfer
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*/
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gpio_irq_disable(spi_config[bus].sclk);
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}
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#endif
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/**
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* @brief Work-around for transmitting 1 byte with SPIM on the nrf52832.
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* @warning Must not be used when transmitting multiple bytes.
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* @warning After this workaround is used, the user must reset the PPI channel
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* and the GPIOTE channel before attempting to transmit multiple bytes.
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*
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* @param bus The SPI instance that is in use.
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*/
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static void _setup_workaround_for_ftpan_58(spi_t bus)
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{
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#ifdef ERRATA_SPI_SINGLE_BYTE_WORKAROUND
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gpio_init_int(spi_config[bus].sclk, GPIO_OUT, GPIO_BOTH,
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spi_gpio_handler, (void *)bus);
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gpio_irq_disable(spi_config[bus].sclk);
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uint8_t channel = gpio_int_get_exti(spi_config[bus].sclk);
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assert(channel != 0xff);
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// Stop the spim instance when SCK toggles.
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NRF_PPI->CH[spi_config[bus].ppi].EEP =
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(uint32_t)&NRF_GPIOTE->EVENTS_IN[channel];
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NRF_PPI->CH[spi_config[bus].ppi].TEP = (uint32_t)&dev(bus)->TASKS_STOP;
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#else
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(void)bus;
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#endif
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}
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static void _enable_workaround(spi_t bus)
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{
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#ifdef ERRATA_SPI_SINGLE_BYTE_WORKAROUND
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/**
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* The spim instance cannot be stopped mid-byte, so it will finish
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* transmitting the first byte and then stop. Effectively ensuring
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* that only 1 byte is transmitted.
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*/
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NRF_PPI->CHENSET = 1U << spi_config[bus].ppi;
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gpio_irq_enable(spi_config[bus].sclk);
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#else
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(void)bus;
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#endif
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}
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static void _clear_workaround(spi_t bus)
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{
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#ifdef ERRATA_SPI_SINGLE_BYTE_WORKAROUND
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NRF_PPI->CHENCLR = 1U << spi_config[bus].ppi;
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#else
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(void)bus;
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#endif
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}
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void spi_init(spi_t bus)
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{
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assert(bus < SPI_NUMOF);
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/* initialize mutex */
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mutex_init(&locks[bus]);
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mutex_init(&busy[bus]);
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mutex_lock(&busy[bus]);
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/* initialize pins */
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spi_init_pins(bus);
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}
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void spi_init_pins(spi_t bus)
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{
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gpio_init(spi_config[bus].sclk, GPIO_OUT);
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gpio_init(spi_config[bus].mosi, GPIO_OUT);
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gpio_init(spi_config[bus].miso, GPIO_IN);
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/* select pins for the SPI device */
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SPI_SCKSEL = spi_config[bus].sclk;
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SPI_MOSISEL = spi_config[bus].mosi;
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SPI_MISOSEL = spi_config[bus].miso;
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_setup_workaround_for_ftpan_58(bus);
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spi_twi_irq_register_spi(dev(bus), spi_isr_handler, (void *)bus);
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}
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int spi_acquire(spi_t bus, spi_cs_t cs, spi_mode_t mode, spi_clk_t clk)
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{
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(void)cs;
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mutex_lock(&locks[bus]);
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/* configure bus */
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dev(bus)->CONFIG = mode;
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dev(bus)->FREQUENCY = clk;
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/* enable the bus */
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dev(bus)->ENABLE = SPIM_ENABLE_ENABLE_Enabled;
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return SPI_OK;
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}
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void spi_release(spi_t bus)
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{
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/* power off everything */
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dev(bus)->ENABLE = 0;
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mutex_unlock(&locks[bus]);
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}
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static size_t _transfer(spi_t bus, const uint8_t *out_buf, uint8_t *in_buf,
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size_t remaining_len)
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{
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uint8_t transfer_len = remaining_len > UINT8_MAX ? UINT8_MAX : remaining_len;
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const uint8_t *out_mbuf = out_buf;
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/**
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* Copy the out buffer in case it resides in flash, EasyDMA only works from
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* RAM
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*/
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if (out_buf && !_in_ram(out_buf)) {
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/* The SPI MBUF can be smaller than UINT8_MAX */
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transfer_len = transfer_len > CONFIG_SPI_MBUF_SIZE
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? CONFIG_SPI_MBUF_SIZE : transfer_len;
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memcpy(_mbuf[bus], out_buf, transfer_len);
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out_mbuf = _mbuf[bus];
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}
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uint8_t out_len = (out_buf) ? transfer_len : 0;
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uint8_t in_len = (in_buf) ? transfer_len : 0;
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dev(bus)->TXD.PTR = (uint32_t)out_mbuf;
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dev(bus)->RXD.PTR = (uint32_t)in_buf;
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dev(bus)->TXD.MAXCNT = out_len;
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dev(bus)->RXD.MAXCNT = in_len;
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/* clear any spurious END events */
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dev(bus)->EVENTS_END = 0;
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dev(bus)->TASKS_START = 1;
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return transfer_len;
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}
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void spi_transfer_bytes(spi_t bus, spi_cs_t cs, bool cont,
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const void *out, void *in, size_t len)
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{
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const uint8_t *out_buf = out;
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uint8_t *in_buf = in;
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assert(out_buf || in_buf);
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if (cs != SPI_CS_UNDEF) {
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gpio_clear((gpio_t)cs);
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}
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/* Enable the workaround when the length is only 1 byte */
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size_t _len = len;
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if (_len == 1) {
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_enable_workaround(bus);
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}
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/* Enable IRQ */
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dev(bus)->INTENSET = SPIM_INTENSET_END_Msk;
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do {
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size_t transfer_len = _transfer(bus, out_buf, in_buf, len);
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/* Block until the irq releases the mutex, then lock it again for the
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* next transfer */
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mutex_lock(&busy[bus]);
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out_buf += out_buf ? transfer_len : 0;
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in_buf += in_buf ? transfer_len : 0;
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len -= transfer_len;
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} while (len);
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/* Disable IRQ */
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dev(bus)->INTENCLR = SPIM_INTENCLR_END_Msk;
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/**
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* While we could always disable the workaround, only doing this when
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* required spares us some cycles by not having to write to volatile
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* registers
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*/
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if (_len == 1) {
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_clear_workaround(bus);
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}
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if ((cs != SPI_CS_UNDEF) && (!cont)) {
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gpio_set((gpio_t)cs);
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}
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}
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void spi_isr_handler(void *arg)
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{
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spi_t bus = (spi_t)arg;
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mutex_unlock(&busy[bus]);
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dev(bus)->EVENTS_END = 0;
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}
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