diff --git a/cpu/cortexm_common/cortexm_init.c b/cpu/cortexm_common/cortexm_init.c
new file mode 100644
index 0000000000..4d4f460b15
--- /dev/null
+++ b/cpu/cortexm_common/cortexm_init.c
@@ -0,0 +1,52 @@
+/*
+ * Copyright (C) 2015 Freie Universität Berlin
+ *
+ * This file is subject to the terms and conditions of the GNU Lesser
+ * General Public License v2.1. See the file LICENSE in the top level
+ * directory for more details.
+ */
+
+/**
+ * @ingroup     cpu_cortexm_common
+ * @{
+ *
+ * @file
+ * @brief       Cortex-M specific configuration and initialization options
+ *
+ * @author      Hauke Petersen <hauke.petersen@fu-berlin.de>
+ *
+ * @}
+ */
+
+#include "cpu.h"
+
+/**
+ * @name   Pattern to write into the co-processor Access Control Register to
+ *         allow full FPU access
+ */
+#define FULL_FPU_ACCESS         (0x00f00000)
+
+void cortexm_init(void)
+{
+    /* initialize the FPU on Cortex-M4F CPUs */
+#ifdef CPU_ARCH_CORTEX_M4F
+    /* give full access to the FPU */
+    SCB->CPACR |= (uint32_t)FULL_FPU_ACCESS;
+#endif
+
+    /* configure the vector table location to internal flash */
+#if defined(CPU_ARCH_CORTEX_M3) || defined(CPU_ARCH_CORTEX_M4) || \
+    defined(CPU_ARCH_CORTEX_M4F)
+    SCB->VTOR = CPU_FLASH_BASE;
+#endif
+
+    /* initialize the interrupt priorities */
+    /* set pendSV interrupt to lowest possible priority */
+    NVIC_SetPriority(PendSV_IRQn, 0xff);
+    /* set SVC interrupt to same priority as the rest */
+    NVIC_SetPriority(SVCall_IRQn, CPU_DEFAULT_IRQ_PRIO);
+    /* initialize all vendor specific interrupts with the same value */
+    for (int i = 0; i < CPU_IRQ_NUMOF; i++) {
+        NVIC_SetPriority(i, CPU_DEFAULT_IRQ_PRIO);
+    }
+}
diff --git a/cpu/cortexm_common/include/cpu.h b/cpu/cortexm_common/include/cpu.h
index 0c6d8bccc9..fcb80da5f4 100644
--- a/cpu/cortexm_common/include/cpu.h
+++ b/cpu/cortexm_common/include/cpu.h
@@ -25,13 +25,12 @@
  * @author      Joakim Gebart <joakim.gebart@eistec.se>
  */
 
-#ifndef CORTEXM_COMMON_H_
-#define CORTEXM_COMMON_H_
-
+#ifndef CPU_H_
+#define CPU_H_
 
 #include "cpu_conf.h"
 
-/**
+/*
  * TODO: remove once core was adjusted
  */
 #include "irq.h"
@@ -41,30 +40,87 @@ extern "C" {
 #endif
 
 /**
- * @brief   Deprecated interrupt control function for backward compatibility
+ * @brief    Configuration of default stack sizes
+ *
+ * As all members of the Cortex-M family behave identical in terms of stack
+ * usage, we define the default stack size values here centrally for all CPU
+ * implementations.
+ *
+ * If needed, you can overwrite these values the the `cpu_conf.h` file of the
+ * specific CPU implementation.
+ *
+ * TODO: Adjust values for Cortex-M4F with FPU?
+ * TODO: Configure second set if no newlib nano.specs are available?
  * @{
  */
-#define eINT            enableIRQ
-#define dINT            disableIRQ
+#ifndef THREAD_EXTRA_STACKSIZE_PRINTF
+#define THREAD_EXTRA_STACKSIZE_PRINTF   (512)
+#endif
+#ifndef THREAD_STACKSIZE_DEFAULT
+#define THREAD_STACKSIZE_DEFAULT        (1024)
+#endif
+#ifndef THREAD_STACKSIZE_IDLE
+#define THREAD_STACKSIZE_IDLE           (256)
+#endif
 /** @} */
 
 /**
- * @brief   Some members of the Cortex-M family have architecture specific atomic
- *          operations in atomic_arch.c
+ * @brief   UART0 buffer size definition for compatibility reasons
+ *
+ * TODO: remove once the remodeling of the uart0 driver is done
+ * @{
+ */
+#ifndef UART0_BUFSIZE
+#define UART0_BUFSIZE                   (128)
+#endif
+/** @} */
+
+/**
+ * @brief   Deprecated interrupt control function for backward compatibility
+ * @{
+ */
+#define eINT                            enableIRQ
+#define dINT                            disableIRQ
+/** @} */
+
+/**
+ * @brief   Some members of the Cortex-M family have architecture specific
+ *          atomic operations in atomic_arch.c
  */
 #if defined(CPU_ARCH_CORTEX_M3) || defined(CPU_ARCH_CORTEX_M4) || \
     defined(CPU_ARCH_CORTEX_M4F)
 #define ARCH_HAS_ATOMIC_COMPARE_AND_SWAP 1
 #endif
 
+/**
+ * @brief Definition of available panic modes
+ */
+typedef enum {
+    PANIC_NMI_HANDLER,       /**< non maskable interrupt */
+    PANIC_HARD_FAULT,        /**< hard fault */
+#if defined(CPU_ARCH_CORTEX_M3) || defined(CPU_ARCH_CORTEX_M4) || \
+    defined(CPU_ARCH_CORTEX_M4F)
+    PANIC_MEM_MANAGE,        /**< memory controller interrupt */
+    PANIC_BUS_FAULT,         /**< bus fault */
+    PANIC_USAGE_FAULT,       /**< undefined instruction or unaligned access */
+    PANIC_DEBUG_MON,         /**< debug interrupt */
+#endif
+    PANIC_DUMMY_HANDLER,     /**< unhandled interrupt */
+} panic_t;
+
 /**
  * @brief   Initialization of the CPU
  */
 void cpu_init(void);
 
+/**
+ * @brief   Initialize Cortex-M specific core parts of the CPU
+ */
+void cortexm_init(void);
+
 #ifdef __cplusplus
 }
 #endif
 
-#endif /* CORTEXM_COMMON_H_ */
+#endif /* CPU_H_ */
 /** @} */