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Merge pull request #1735 from haukepetersen/fix_stm32f1_somecleanup2

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cpu/board: cleanup for clock init on iot-lab_M3
This commit is contained in:
Hauke Petersen 2014-09-30 11:40:43 +02:00
commit 7aaaa62720
6 changed files with 79 additions and 179 deletions
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6
boards/iot-lab_M3/board.c
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@ -18,19 +18,13 @@
* @}
*/
#include "cmsis_system.h"
#include "board.h"
#include "cpu.h"
static void leds_init(void);
void board_init(void)
{
/* initialize core clocks via CMSIS function provided by ST */
SystemInit();
/* initialize the CPU */
cpu_init();

3
boards/iot-lab_M3/include/board.h
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@ -27,11 +27,12 @@
#include <stdint.h>
#include "cpu.h"
#include "periph_conf.h"
/**
* Define the nominal CPU core clock in this board
*/
#define F_CPU (72000000UL)
#define F_CPU CLOCK_CORECLOCK
/**
* @name Define the UART to be used as stdio and its baudrate

18
boards/iot-lab_M3/include/periph_conf.h
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@ -18,6 +18,24 @@
#ifndef __PERIPH_CONF_H
#define __PERIPH_CONF_H
/**
* @name Clock system configuration
* @{
**/
#define CLOCK_HSE (16000000U) /* frequency of external oscillator */
#define CLOCK_CORECLOCK (72000000U) /* targeted core clock frequency */
/* configuration of PLL prescaler and multiply values */
/* CORECLOCK := HSE / PLL_HSE_DIV * PLL_HSE_MUL */
#define CLOCK_PLL_HSE_DIV RCC_CFGR_PLLXTPRE_HSE_Div2
#define CLOCK_PLL_HSE_MUL RCC_CFGR_PLLMULL9
/* configuration of peripheral bus clock prescalers */
#define CLOCK_AHB_DIV RCC_CFGR_HPRE_DIV1 /* AHB clock -> 72MHz */
#define CLOCK_APB2_DIV RCC_CFGR_PPRE2_DIV1 /* APB2 clock -> 72MHz */
#define CLOCK_APB1_DIV RCC_CFGR_PPRE1_DIV2 /* APB1 clock -> 36MHz */
/* configuration of flash access cycles */
#define CLOCK_FLASH_LATENCY FLASH_ACR_LATENCY_2
/** @} */
/**
* @brief Timer configuration
* @{

128
boards/iot-lab_M3/system_stm32f1.c
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@ -1,128 +0,0 @@
/*
* Copyright (C) 2014 Freie Universität Berlin
*
* This file is subject to the terms and conditions of the GNU Lesser General
* Public License v2.1. See the file LICENSE in the top level directory for more
* details.
*/
/**
* @ingroup board_iot-lab_M3
* @{
*
* @file system_stm32f1.c
* @brief Board specific clock setup
*
* @author Thomas Eichinger <thomas.eichinger@fu-berlin.de>
*
* @}
*/
#include "stm32f10x.h"
#include "board.h"
uint32_t SystemCoreClock = F_CPU;
#define VECT_TAB_OFFSET 0x0
static void set_system_clock(void)
{
volatile uint32_t startup_counter = 0, HSE_status = 0;
/* SYSCLK, HCLK, PCLK2 and PCLK1 configuration */
/* Enable HSE */
RCC->CR |= ((uint32_t)RCC_CR_HSEON);
/* Wait till HSE is ready and if Time out is reached exit */
do {
HSE_status = RCC->CR & RCC_CR_HSERDY;
startup_counter++;
}
while ((HSE_status == 0) && (startup_counter != HSE_STARTUP_TIMEOUT));
if ((RCC->CR & RCC_CR_HSERDY) != RESET) {
HSE_status = (uint32_t)0x01;
}
else {
HSE_status = (uint32_t)0x00;
}
if (HSE_status == (uint32_t)0x01) {
/* Enable Prefetch Buffer */
FLASH->ACR |= FLASH_ACR_PRFTBE;
/* Flash 2 wait state */
FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;
/* HCLK = SYSCLK */
RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
/* PCLK2 = HCLK */
RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
/* PCLK1 = HCLK */
RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
/* NOTE : agilefox : modified to take into account the 16MHz
crystal instead of 8MHz */
/* PLL configuration: PLLCLK = HSE / 2 * 9 = 72 MHz */
RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC
| RCC_CFGR_PLLXTPRE
| RCC_CFGR_PLLMULL));
RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE
| RCC_CFGR_PLLXTPRE_HSE_Div2
| RCC_CFGR_PLLMULL9);
/* Enable PLL */
RCC->CR |= RCC_CR_PLLON;
/* Wait till PLL is ready */
while ((RCC->CR & RCC_CR_PLLRDY) == 0) {
}
/* Select PLL as system clock source */
RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
/* Wait till PLL is used as system clock source */
while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08) {
}
}
else {
/* If HSE fails to start-up, the application will have wrong clock
configuration. User can add here some code to deal with this error */
}
}
void SystemInit(void)
{
/* Reset the RCC clock configuration to the default reset state(for debug purpose) */
/* Set HSION bit */
RCC->CR |= (uint32_t)0x00000001;
/* Reset SW, HPRE, PPRE1, PPRE2, ADCPRE and MCO bits */
RCC->CFGR &= (uint32_t)0xF0FF0000;
/* Reset HSEON, CSSON and PLLON bits */
RCC->CR &= (uint32_t)0xFEF6FFFF;
/* Reset HSEBYP bit */
RCC->CR &= (uint32_t)0xFFFBFFFF;
/* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE/OTGFSPRE bits */
RCC->CFGR &= (uint32_t)0xFF80FFFF;
/* Disable all interrupts and clear pending bits */
RCC->CIR = 0x009F0000;
/* Configure the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers */
/* Configure the Flash Latency cycles and enable prefetch buffer */
set_system_clock();
/* Vector Table Relocation in Internal FLASH. */
SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET;
}

44
cpu/cortex-m3_common/include/cmsis_system.h
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@ -1,44 +0,0 @@
/*
* Copyright (C) 2014 Freie Universität Berlin
*
* This file is subject to the terms and conditions of the GNU Lesser General
* Public License v2.1. See the file LICENSE in the top level directory for more
* details.
*/
/**
* @ingroup cpu_cortexm3_common
* @{
*
* @file
* @brief CMSIS system header definitions for the Cortex-M3
*
* @author Hauke Petersen <hauke.petersen@fu-berlin.de>
*/
#ifndef __CMSIS_SYSTEM_H
#define __CMSIS_SYSTEM_H
#include <stdint.h>
/**
* @brief This variable holds the current CPU core clock frequency in Hz
*/
extern uint32_t SystemCoreClock;
/**
* @brief Initialize the system's clock system
*
* This function sets up the system's clock tree, concerning all options
* regarding PLL setup, external clock source configuration and prescaler
* setup for peripheral buses.
*/
void SystemInit(void);
/**
* @brief Update the `SystemCoreClock` variable with the current core clock value
*/
void SystemCoreClockUpdate(void);
#endif /* __CMSIS_SYSTEM_H */

59
cpu/stm32f1/cpu.c
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@ -17,14 +17,73 @@
* @author Stefan Pfeiffer <stefan.pfeiffer@fu-berlin.de>
* @author Alaeddine Weslati <alaeddine.weslati@inria.fr>
* @author Thomas Eichinger <thomas.eichinger@fu-berlin.de>
* @author Hauke Petersen <hauke.petersen@fu-berlin.de>
*
* @}
*/
#include "cpu.h"
#include "periph_conf.h"
static void clk_init(void);
void cpu_init(void)
{
/* set PendSV priority to the lowest possible priority */
NVIC_SetPriority(PendSV_IRQn, 0xff);
/* configure the vector table location to internal flash */
SCB->VTOR = FLASH_BASE;
/* initialize system clocks */
clk_init();
}
/**
* @brief Configure the clock system of the stm32f1
*
*/
static void clk_init(void)
{
/* Reset the RCC clock configuration to the default reset state(for debug purpose) */
/* Set HSION bit */
RCC->CR |= (uint32_t)0x00000001;
/* Reset SW, HPRE, PPRE1, PPRE2, ADCPRE and MCO bits */
RCC->CFGR &= (uint32_t)0xF0FF0000;
/* Reset HSEON, CSSON and PLLON bits */
RCC->CR &= (uint32_t)0xFEF6FFFF;
/* Reset HSEBYP bit */
RCC->CR &= (uint32_t)0xFFFBFFFF;
/* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE/OTGFSPRE bits */
RCC->CFGR &= (uint32_t)0xFF80FFFF;
/* Disable all interrupts and clear pending bits */
RCC->CIR = (uint32_t)0x009F0000;
/* SYSCLK, HCLK, PCLK2 and PCLK1 configuration */
/* Enable HSE */
RCC->CR |= ((uint32_t)RCC_CR_HSEON);
/* Wait till HSE is ready,
* NOTE: the MCU will stay here forever if no HSE clock is connected */
while ((RCC->CR & RCC_CR_HSERDY) == 0);
/* Enable Prefetch Buffer */
FLASH->ACR |= FLASH_ACR_PRFTBE;
/* Flash 2 wait state */
FLASH->ACR &= ~((uint32_t)FLASH_ACR_LATENCY);
FLASH->ACR |= (uint32_t)CLOCK_FLASH_LATENCY;
/* HCLK = SYSCLK */
RCC->CFGR |= (uint32_t)CLOCK_AHB_DIV;
/* PCLK2 = HCLK */
RCC->CFGR |= (uint32_t)CLOCK_APB2_DIV;
/* PCLK1 = HCLK */
RCC->CFGR |= (uint32_t)CLOCK_APB1_DIV;
/* PLL configuration: PLLCLK = HSE / HSE_DIV * HSE_MUL */
RCC->CFGR &= ~((uint32_t)(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | CLOCK_PLL_HSE_DIV | CLOCK_PLL_HSE_MUL);
/* Enable PLL */
RCC->CR |= RCC_CR_PLLON;
/* Wait till PLL is ready */
while ((RCC->CR & RCC_CR_PLLRDY) == 0);
/* Select PLL as system clock source */
RCC->CFGR &= ~((uint32_t)(RCC_CFGR_SW));
RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
/* Wait till PLL is used as system clock source */
while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != RCC_CFGR_SWS_PLL);
}