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cpu/stm32/periph_eth: Code style
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@ -174,8 +174,8 @@ static void stm32_eth_get_addr(char *out)
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static void stm32_eth_set_addr(const uint8_t *addr)
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{
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ETH->MACA0HR &= 0xffff0000;
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ETH->MACA0HR |= ((addr[5] << 8) | addr[4]);
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ETH->MACA0LR = ((addr[3] << 24) | (addr[2] << 16) | (addr[1] << 8) | addr[0]);
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ETH->MACA0HR |= (addr[5] << 8) | addr[4];
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ETH->MACA0LR = (addr[3] << 24) | (addr[2] << 16) | (addr[1] << 8) | addr[0];
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}
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/** Initialization of the DMA descriptors to be used */
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@ -322,10 +322,11 @@ static int stm32_eth_init(netdev_t *netdev)
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ETH->DMAOMR |= (ETH_DMAOMR_RSF | ETH_DMAOMR_TSF | ETH_DMAOMR_OSF);
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/* configure DMA */
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ETH->DMABMR = (ETH_DMABMR_DA | ETH_DMABMR_AAB | ETH_DMABMR_FB |
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ETH_DMABMR_RDP_32Beat | ETH_DMABMR_PBL_32Beat | ETH_DMABMR_EDE);
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ETH->DMABMR = ETH_DMABMR_DA | ETH_DMABMR_AAB | ETH_DMABMR_FB
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| ETH_DMABMR_RDP_32Beat | ETH_DMABMR_PBL_32Beat
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| ETH_DMABMR_EDE;
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if(eth_config.addr[0] != 0) {
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if (eth_config.addr[0] != 0) {
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stm32_eth_set_addr(eth_config.addr);
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}
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else {
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@ -429,7 +430,8 @@ static int get_rx_frame_size(void)
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DEBUG("[stm32_eth] RX not completed (spurious interrupt?)\n");
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return -EAGAIN;
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}
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DEBUG("[stm32_eth] get_rx_frame_size(): FS=%c, LS=%c, ES=%c, DE=%c, FL=%lu\n",
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DEBUG("[stm32_eth] get_rx_frame_size(): "
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"FS=%c, LS=%c, ES=%c, DE=%c, FL=%lu\n",
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(status & RX_DESC_STAT_FS) ? '1' : '0',
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(status & RX_DESC_STAT_LS) ? '1' : '0',
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(status & RX_DESC_STAT_ES) ? '1' : '0',
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@ -476,11 +478,12 @@ static void handle_lost_rx_irqs(void)
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break;
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}
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if (status & RX_DESC_STAT_LS) {
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DEBUG("[stm32_eth] Lost RX IRQ, sending event to upper layer now\n");
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DEBUG("[stm32_eth] Lost RX IRQ, sending event to upper layer\n");
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/* we use the ISR event for this, as the upper layer calls recv()
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* right away on an NETDEV_EVENT_RX_COMPLETE. Because there could be
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* potentially quite a lot of received frames in the queue, we might
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* risk a stack overflow if we would send an NETDEV_EVENT_RX_COMPLETE
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* risk a stack overflow if we would send an
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* NETDEV_EVENT_RX_COMPLETE
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*/
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netdev_trigger_event_isr(_netdev);
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break;
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