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cpu/stm32/periph/usbdev_fs: changes to support STM32F3

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This commit is contained in:
Gunar Schorcht 2022-10-03 07:03:20 +02:00
parent 1fde5a4401
commit 7f4613da34
3 changed files with 13 additions and 5 deletions
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2
cpu/stm32/Makefile.dep
View File

@ -4,7 +4,7 @@
USEMODULE += periph stm32_clk stm32_vectors
ifneq (,$(filter periph_usbdev,$(FEATURES_USED)))
ifneq (wb,$(CPU_FAM))
ifeq (,$(filter f3 wb,$(CPU_FAM)))
USEMODULE += usbdev_synopsys_dwc2
endif
USEMODULE += ztimer

2
cpu/stm32/periph/Makefile
View File

@ -51,7 +51,7 @@ endif
# Select the correct implementation for `periph_usbdev`
ifneq (,$(filter periph_usbdev,$(USEMODULE)))
ifeq (wb,$(CPU_FAM))
ifneq (,$(filter f3 wb,$(CPU_FAM)))
SRC += usbdev_fs.c
endif
endif

14
cpu/stm32/periph/usbdev_fs.c
View File

@ -279,10 +279,12 @@ static void _usbdev_init(usbdev_t *dev)
/* Configure GPIOs */
_enable_gpio(conf);
/* Reset USB IP */
_global_regs(conf)->CNTR = USB_CNTR_FRES;
/* Reset and power down USB IP */
_global_regs(conf)->CNTR = USB_CNTR_FRES | USB_CNTR_PDWN;
/* Clear power down */
_global_regs(conf)->CNTR &= ~USB_CNTR_PDWN;
/* Clear reset */
_global_regs(conf)->CNTR = 0;
_global_regs(conf)->CNTR &= ~USB_CNTR_FRES;
/* Clear interrupt register */
_global_regs(conf)->ISTR = 0x0000;
/* Set BTABLE at start of USB SRAM */
@ -291,6 +293,12 @@ static void _usbdev_init(usbdev_t *dev)
_global_regs(conf)->DADDR = USB_DADDR_EF;
/* Unmask the interrupt in the NVIC */
_enable_irq();
/* Disable remapping of USB IRQs if remapping defined */
#ifdef SYSCFG_CFGR1_USB_IT_RMP
SYSCFG->CFGR1 &= ~SYSCFG_CFGR1_USB_IT_RMP;
#endif
/* Enable USB IRQ */
NVIC_EnableIRQ(conf->irqn);
/* fill USB SRAM with zeroes */