From 8af4c9eb565ecb5176ef3ed7c5ce99da7c24cfe2 Mon Sep 17 00:00:00 2001 From: Gunar Schorcht Date: Thu, 2 Jun 2022 15:54:49 +0200 Subject: [PATCH] cpu/esp32/bootloader: move common configuration to a common file --- cpu/esp32/bootloader/sdkconfig.h | 2 + .../bootloader/sdkconfig_default_common.h | 56 +++++++++++++++++++ .../bootloader/sdkconfig_default_esp32.h | 20 +------ .../bootloader/sdkconfig_default_esp32c3.h | 30 ++-------- 4 files changed, 65 insertions(+), 43 deletions(-) create mode 100644 cpu/esp32/bootloader/sdkconfig_default_common.h diff --git a/cpu/esp32/bootloader/sdkconfig.h b/cpu/esp32/bootloader/sdkconfig.h index fd1d6a6c43..f4b35a1805 100644 --- a/cpu/esp32/bootloader/sdkconfig.h +++ b/cpu/esp32/bootloader/sdkconfig.h @@ -39,6 +39,8 @@ #error "ESP32x family implementation missing" #endif +#include "sdkconfig_default_common.h" + #ifdef __cplusplus extern "C" { #endif diff --git a/cpu/esp32/bootloader/sdkconfig_default_common.h b/cpu/esp32/bootloader/sdkconfig_default_common.h new file mode 100644 index 0000000000..ed2e759998 --- /dev/null +++ b/cpu/esp32/bootloader/sdkconfig_default_common.h @@ -0,0 +1,56 @@ +/* + * Copyright (C) 2022 Gunar Schorcht + * + * This file is subject to the terms and conditions of the GNU Lesser + * General Public License v2.1. See the file LICENSE in the top level + * directory for more details. + */ + +/** + * @ingroup cpu_esp32 + * @{ + * + * @file + * @brief Default SDK configuration for all ESP32x SoC bootloaders + * + * @author Gunar Schorcht + */ + +#ifndef SDKCONFIG_DEFAULT_COMMON_H +#define SDKCONFIG_DEFAULT_COMMON_H + +#ifndef DOXYGEN + +#ifdef __cplusplus +extern "C" { +#endif + +#define CONFIG_BOOTLOADER_COMPILER_OPTIMIZATION_SIZE 1 +#define CONFIG_BOOTLOADER_VDDSDIO_BOOST_1_9V 1 +#define CONFIG_BOOTLOADER_WDT_ENABLE 1 +#define CONFIG_BOOTLOADER_WDT_TIME_MS 9000 +#define CONFIG_BOOTLOADER_RESERVE_RTC_SIZE 0x0 +#define CONFIG_BOOTLOADER_FLASH_XMC_SUPPORT 1 + +#define CONFIG_ESP_CONSOLE_UART 1 +#define CONFIG_ESP_CONSOLE_UART_DEFAULT 1 +#define CONFIG_ESP_CONSOLE_UART_NUM 0 + +#define CONFIG_CONSOLE_UART_NUM CONFIG_ESP_CONSOLE_UART_NUM +#define CONFIG_CONSOLE_UART_DEFAULT CONFIG_ESP_CONSOLE_UART_DEFAULT + +#define CONFIG_LOG_DEFAULT_LEVEL 3 +#define CONFIG_LOG_TIMESTAMP_SOURCE_RTOS 1 + +#define CONFIG_PARTITION_TABLE_OFFSET 0x8000 +#define CONFIG_PARTITION_TABLE_MD5 1 + +#define CONFIG_SPI_FLASH_ROM_DRIVER_PATCH 1 + +#ifdef __cplusplus +} +#endif + +#endif /* DOXYGEN */ +#endif /* SDKCONFIG_DEFAULT_COMMON_H */ +/** @} */ diff --git a/cpu/esp32/bootloader/sdkconfig_default_esp32.h b/cpu/esp32/bootloader/sdkconfig_default_esp32.h index 6b68fa33b5..e8e7708498 100644 --- a/cpu/esp32/bootloader/sdkconfig_default_esp32.h +++ b/cpu/esp32/bootloader/sdkconfig_default_esp32.h @@ -29,28 +29,14 @@ extern "C" { #define CONFIG_ESP32_DEFAULT_CPU_FREQ_MHZ 160 #endif -#define CONFIG_BOOTLOADER_VDDSDIO_BOOST_1_9V 1 -#define CONFIG_BOOTLOADER_OFFSET_IN_FLASH 0x1000 -#define CONFIG_BOOTLOADER_FLASH_XMC_SUPPORT 1 -#define CONFIG_CONSOLE_UART_NUM 0 -#define CONFIG_EFUSE_CODE_SCHEME_COMPAT_3_4 1 -#define CONFIG_EFUSE_MAX_BLK_LEN 192 - -#define CONFIG_CONSOLE_UART_NUM 0 -#define CONFIG_ESP_CONSOLE_UART 1 -#define CONFIG_ESP_CONSOLE_UART_NUM 0 #define CONFIG_ESP32_DEBUG_OCDAWARE 1 #define CONFIG_ESP32_XTAL_FREQ 40 +#define CONFIG_BOOTLOADER_OFFSET_IN_FLASH 0x1000 +#define CONFIG_EFUSE_CODE_SCHEME_COMPAT_3_4 1 +#define CONFIG_EFUSE_MAX_BLK_LEN 192 #define CONFIG_IDF_FIRMWARE_CHIP_ID 0x0000 -#define CONFIG_LOG_DEFAULT_LEVEL 3 -#define CONFIG_LOG_TIMESTAMP_SOURCE_RTOS 1 - -#define CONFIG_PARTITION_TABLE_OFFSET 0x8000 - -#define CONFIG_SPI_FLASH_ROM_DRIVER_PATCH 1 - #ifdef __cplusplus } #endif diff --git a/cpu/esp32/bootloader/sdkconfig_default_esp32c3.h b/cpu/esp32/bootloader/sdkconfig_default_esp32c3.h index bab0fceb7b..9af2f293ca 100644 --- a/cpu/esp32/bootloader/sdkconfig_default_esp32c3.h +++ b/cpu/esp32/bootloader/sdkconfig_default_esp32c3.h @@ -11,7 +11,7 @@ * @{ * * @file - * @brief Default SDK configuration for the ESP32C3 SoC bootloader + * @brief Default SDK configuration for the ESP32-C3 SoC bootloader * * @author Gunar Schorcht */ @@ -29,36 +29,14 @@ extern "C" { #define CONFIG_ESP32C3_DEFAULT_CPU_FREQ_MHZ 160 #endif -#define CONFIG_BOOTLOADER_COMPILER_OPTIMIZATION_SIZE 1 -#define CONFIG_BOOTLOADER_FLASH_XMC_SUPPORT 1 -#define CONFIG_BOOTLOADER_OFFSET_IN_FLASH 0x0 -#define CONFIG_BOOTLOADER_RESERVE_RTC_SIZE 0x0 -#define CONFIG_BOOTLOADER_VDDSDIO_BOOST_1_9V 1 -#define CONFIG_BOOTLOADER_WDT_ENABLE 1 -#define CONFIG_BOOTLOADER_WDT_TIME_MS 9000 - -#define CONFIG_ESP_CONSOLE_SECONDARY_USB_SERIAL_JTAG 1 -#define CONFIG_ESP_CONSOLE_UART 1 -#define CONFIG_ESP_CONSOLE_UART_DEFAULT 1 -#define CONFIG_ESP_CONSOLE_UART_NUM 0 - -#define CONFIG_CONSOLE_UART_NUM CONFIG_ESP_CONSOLE_UART_NUM -#define CONFIG_CONSOLE_UART_DEFAULT CONFIG_ESP_CONSOLE_UART_DEFAULT - -#define CONFIG_EFUSE_MAX_BLK_LEN 192 - #define CONFIG_ESP32C3_DEBUG_OCDAWARE 1 #define CONFIG_ESP32C3_REV_MIN 3 +#define CONFIG_BOOTLOADER_OFFSET_IN_FLASH 0x0 +#define CONFIG_EFUSE_MAX_BLK_LEN 256 #define CONFIG_IDF_FIRMWARE_CHIP_ID 0x0005 -#define CONFIG_LOG_DEFAULT_LEVEL 3 -#define CONFIG_LOG_TIMESTAMP_SOURCE_RTOS 1 - -#define CONFIG_PARTITION_TABLE_OFFSET 0x8000 -#define CONFIG_PARTITION_TABLE_MD5 1 - -#define CONFIG_SPI_FLASH_ROM_DRIVER_PATCH 1 +#define CONFIG_ESP_CONSOLE_SECONDARY_USB_SERIAL_JTAG 1 #ifdef __cplusplus }