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tests/periph_gpio: bench port 1 on z1

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/* Port 1:
     *  P1.0 is not assigned by default
     *  P1.1 is the bootstrap-loader (BSL) TX pin -> input, special function, default to GND
     *       THIS PIN MUST *NEVER* BE USED IN NORMAL EXECUTION, SINCE IT INTERFERES WITH UART0 !!!
     *  P1.2 receives the FIFOP interrupt from CC2420 -> input, GPIO, default to GND
     *  P1.3 receives the FIFO/GIO0 interrupt from CC2420 -> input, GPIO, default to GND
     *  P1.4 receives the CCA/GIO1 signal from CC2420 -> input, GPIO, default to GND
     *  P1.5 is wired to Vcc -> input, GPIO, default to Vcc
     *  P1.6 receives interrupt INT1 from accelerometer -> input, GPIO, default to GND
     *  P1.7 receives interrupt INT2 from accelerometer -> input, GPIO, default to GND
     */

(test starts indexing at 0)
This commit is contained in:
Kaspar Schleiser 2020-07-30 13:32:39 +02:00
parent 789f10e816
commit 8afaf11bb5
1 changed files with 1 additions and 0 deletions
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1
tests/periph_gpio/Makefile
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@ -9,6 +9,7 @@ USEMODULE += benchmark
BOARDS_BENCH_PORT_1 = \
slstk3402a \
z1 \
#
# port 0 pins are used for serial output on these boards, e.g.: on slstk3402a